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From: Brijesh Singh <brijesh.singh@amd.com>
To: Dandan Bi <dandan.bi@intel.com>, edk2-devel@lists.01.org
Cc: brijesh.singh@amd.com, Jeff Fan <jeff.fan@intel.com>
Subject: Re: [patch] UefiCpuPkg: Fix coding style issues
Date: Wed, 28 Jun 2017 14:45:35 -0500	[thread overview]
Message-ID: <8d8e1e05-5496-1e0f-c869-8902d307f5fc@amd.com> (raw)
In-Reply-To: <1498617758-21960-1-git-send-email-dandan.bi@intel.com>

On 06/27/2017 09:42 PM, Dandan Bi wrote:
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Dandan Bi <dandan.bi@intel.com>
> ---
>   UefiCpuPkg/Include/Register/Amd/Fam17Msr.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
> index 2c5d973..9a79de1 100644
> --- a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
> +++ b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
> @@ -18,12 +18,12 @@
>     @par Specification Reference:
>     AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
>   
>   **/
>   
> -#ifndef __FAM17_MSR_H
> -#define __FAM17_MSR_H
> +#ifndef __FAM17_MSR_H__
> +#define __FAM17_MSR_H__
>   
>   /**
>     Secure Encrypted Virtualization (SEV) status register
>   
>   **/
> 

Thanks,

Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>


  reply	other threads:[~2017-06-28 19:44 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-28  2:42 [patch] UefiCpuPkg: Fix coding style issues Dandan Bi
2017-06-28 19:45 ` Brijesh Singh [this message]
2017-06-29  1:52 ` Fan, Jeff

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