From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) by mx.groups.io with SMTP id smtpd.web11.1760.1662483767124653270 for ; Tue, 06 Sep 2022 10:02:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=jYDhPApr; spf=pass (domain: gmail.com, ip: 209.85.160.169, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qt1-f169.google.com with SMTP id w28so8516892qtc.7 for ; Tue, 06 Sep 2022 10:02:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=e8KNzdqDdwolG6GgBdKi8jMjkKPI5FXog0QP7NZB55o=; b=jYDhPAprkSkVs16xOFKg79fEfwkQzuyricyZ9RQniqde9q8ACH14/JIcgm+nDO99zV o5NnU9iCSKsV7LguGrzbR+ttPxUuUwsZt30YUAI8JQP++CGCakTFaonIyww8qt8Cep45 bLf/2uoeH0q5U7E3f68CTymbzZmuKsDcSt7yKQm12A3QcXzZmdhembZwJKeo7Ts6VhWC tBW6z5/tlKsLyNmZNe9n2XHdzs1VAvINoafw8EMauA7ePvil5RgI1JHDd79wEFo00DpZ EoafRsI9XHz6Y0FePakR7USl6PoDAptqa1MeEJ1Vvkh+4w0klPnWNAdRyDTqtMiKmCjE 51aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=e8KNzdqDdwolG6GgBdKi8jMjkKPI5FXog0QP7NZB55o=; b=UACKgVmv4cwq0jkPU5UIeXbkI0Ldtlf/8IVCavVKWa8uOsHIcdfa/SmOErM2GPuknw pBEaV+Zcz0m8M0wrg6plqlsYnlrWPx9U/Y+pVv7vxOe8YZQh6o/JerkXPMUslitIo52K aJu6VU7agS0Joym9eVmo4qKVMjVvneF/hI1GdDzoGe/H1gAe5hRVR5J0Cr8BTVlvNGC1 q0szbYtXIY/1XajxKJypOo9X/YmvDGkmzXPx/aLTTg90AYLhivvXTiWb/CRqDWh1FtpE cD+3yyujCyV2/EeH2CQFfd2oQL1m4JmCQu9URR5vUTWTRCMPWAFtFJS1MWMuTRD5c1GU MWkg== X-Gm-Message-State: ACgBeo0qqyRpjhjc+j1NIjAavfxI1/OaXhlh0hAt5V9uT1O3f6IbRBR7 REQcNSt5oIgY9O2/LFVShD/AisYGVI75Dg== X-Google-Smtp-Source: AA6agR5aQwGGGBFm3AhApO7awHw/ZbOhvtukoZiPFm1JP754J+3WC1cqlut9TjLh05NyuFfOw63e7g== X-Received: by 2002:a05:622a:254:b0:343:55c0:1d84 with SMTP id c20-20020a05622a025400b0034355c01d84mr44111327qtx.225.1662483765927; Tue, 06 Sep 2022 10:02:45 -0700 (PDT) Return-Path: Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:46bc:db07:bbf3:df6d]) by smtp.gmail.com with ESMTPSA id bi13-20020a05620a318d00b006b59f02224asm10895809qkb.60.2022.09.06.10.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:02:45 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Ray Ni , Rangasai V Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support Date: Tue, 6 Sep 2022 13:02:25 -0400 Message-Id: <8dffa2473dfd2871443632ab2ba32a787471dafd.1662483691.git.benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access. Tested, working on Kabylake. Further testing required after the refactor for compatibility. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + 4 files changed, 373 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmContro= lLib.h diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c new file mode 100644 index 000000000000..cc6c7f8fe672 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.c @@ -0,0 +1,309 @@ +/** @file=0D + This is to publish the SMM Control Ppi instance.=0D +=0D + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', '= c')=0D +=0D +typedef struct {=0D + UINTN Signature;=0D + EFI_HANDLE Handle;=0D + EFI_PEI_MM_CONTROL_PPI SmmControl;=0D +} SMM_CONTROL_PRIVATE_DATA;=0D +=0D +#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \=0D + CR (a, \=0D + SMM_CONTROL_PRIVATE_DATA, \=0D + SmmControl, \=0D + SMM_CONTROL_DEV_SIGNATURE \=0D + )=0D +=0D +//=0D +// Common registers:=0D +//=0D +//=0D +// APM Registers=0D +//=0D +#define R_PCH_APM_CNT 0xB2=0D +//=0D +// ACPI and legacy I/O register offsets from ACPIBASE=0D +//=0D +#define R_PCH_ACPI_PM1_STS 0x00=0D +#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11=0D +=0D +#define R_PCH_SMI_EN 0x30=0D +=0D +#define R_PCH_SMI_STS 0x34=0D +#define B_PCH_SMI_STS_APM BIT5=0D +#define B_PCH_SMI_EN_APMC BIT5=0D +#define B_PCH_SMI_EN_EOS BIT1=0D +#define B_PCH_SMI_EN_GBL_SMI BIT0=0D +=0D +/**=0D + Trigger the software SMI=0D +=0D + @param[in] Data The value to be set on the software SMI = data port=0D +=0D + @retval EFI_SUCCESS Function completes successfully=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmTrigger (=0D + UINT8 Data=0D + )=0D +{=0D + UINT16 ABase;=0D + UINT32 OutputData;=0D + UINT32 OutputPort;=0D +=0D + ABase =3D FixedPcdGet16 (PcdAcpiBaseAddress);=0D +=0D + ///=0D + /// Enable the APMC SMI=0D + ///=0D + OutputPort =3D ABase + R_PCH_SMI_EN;=0D + OutputData =3D IoRead32 ((UINTN) OutputPort);=0D + OutputData |=3D (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);=0D + DEBUG (=0D + (DEBUG_EVENT,=0D + "The SMI Control Port at address %x will be written to %x.\n",=0D + OutputPort,=0D + OutputData)=0D + );=0D + IoWrite32 (=0D + (UINTN) OutputPort,=0D + (UINT32) (OutputData)=0D + );=0D +=0D + OutputPort =3D R_PCH_APM_CNT;=0D + OutputData =3D Data;=0D +=0D + ///=0D + /// Generate the APMC SMI=0D + ///=0D + IoWrite8 (=0D + (UINTN) OutputPort,=0D + (UINT8) (OutputData)=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Clear the SMI status=0D +=0D +=0D + @retval EFI_SUCCESS The function completes successfully=0D + @retval EFI_DEVICE_ERROR Something error occurred=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmClear (=0D + VOID=0D + )=0D +{=0D + UINT16 ABase;=0D + UINT32 OutputData;=0D + UINT32 OutputPort;=0D +=0D + ABase =3D FixedPcdGet16 (PcdAcpiBaseAddress);=0D +=0D + ///=0D + /// Clear the Power Button Override Status Bit, it gates EOS from being = set.=0D + ///=0D + OutputPort =3D ABase + R_PCH_ACPI_PM1_STS;=0D + OutputData =3D B_PCH_ACPI_PM1_STS_PRBTNOR;=0D + DEBUG (=0D + (DEBUG_EVENT,=0D + "The PM1 Status Port at address %x will be written to %x.\n",=0D + OutputPort,=0D + OutputData)=0D + );=0D + IoWrite16 (=0D + (UINTN) OutputPort,=0D + (UINT16) (OutputData)=0D + );=0D +=0D + ///=0D + /// Clear the APM SMI Status Bit=0D + ///=0D + OutputPort =3D ABase + R_PCH_SMI_STS;=0D + OutputData =3D B_PCH_SMI_STS_APM;=0D + DEBUG (=0D + (DEBUG_EVENT,=0D + "The SMI Status Port at address %x will be written to %x.\n",=0D + OutputPort,=0D + OutputData)=0D + );=0D + IoWrite32 (=0D + (UINTN) OutputPort,=0D + (UINT32) (OutputData)=0D + );=0D +=0D + ///=0D + /// Set the EOS Bit=0D + ///=0D + OutputPort =3D ABase + R_PCH_SMI_EN;=0D + OutputData =3D IoRead32 ((UINTN) OutputPort);=0D + OutputData |=3D B_PCH_SMI_EN_EOS;=0D + DEBUG (=0D + (DEBUG_EVENT,=0D + "The SMI Control Port at address %x will be written to %x.\n",=0D + OutputPort,=0D + OutputData)=0D + );=0D + IoWrite32 (=0D + (UINTN) OutputPort,=0D + (UINT32) (OutputData)=0D + );=0D +=0D + ///=0D + /// There is no need to read EOS back and check if it is set.=0D + /// This can lead to a reading of zero if an SMI occurs right after the = SMI_EN port read=0D + /// but before the data is returned to the CPU.=0D + /// SMM Dispatcher should make sure that EOS is set after all SMI source= s are processed.=0D + ///=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This routine generates an SMI=0D +=0D + @param[in] This The EFI SMM Control protocol insta= nce=0D + @param[in, out] ArgumentBuffer The buffer of argument=0D + @param[in, out] ArgumentBufferSize The size of the argument buffer=0D + @param[in] Periodic Periodic or not=0D + @param[in] ActivationInterval Interval of periodic SMI=0D +=0D + @retval EFI Status Describing the result of the opera= tion=0D + @retval EFI_INVALID_PARAMETER Some parameter value passed is not= supported=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +Activate (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_MM_CONTROL_PPI * This,=0D + IN OUT INT8 *ArgumentBuffer OPTIONAL,=0D + IN OUT UINTN *ArgumentBufferSize OPTIONAL,=0D + IN BOOLEAN Periodic OPTIONAL,=0D + IN UINTN ActivationInterval OPTIONAL=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT8 Data;=0D +=0D + if (Periodic) {=0D + DEBUG ((DEBUG_WARN, "Invalid parameter\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei=0D + if (ArgumentBuffer =3D=3D NULL) {=0D + Data =3D 0xFF;=0D + } else {=0D + if (ArgumentBufferSize =3D=3D NULL || *ArgumentBufferSize !=3D 1) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Data =3D *ArgumentBuffer;=0D + }=0D + ///=0D + /// Clear any pending the APM SMI=0D + ///=0D + Status =3D SmmClear ();=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + return SmmTrigger (Data);=0D +}=0D +=0D +/**=0D + This routine clears an SMI=0D +=0D + @param[in] This The EFI SMM Control protocol instance=0D + @param[in] Periodic Periodic or not=0D +=0D + @retval EFI Status Describing the result of the operation=0D + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +Deactivate (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_MM_CONTROL_PPI * This,=0D + IN BOOLEAN Periodic OPTIONAL=0D + )=0D +{=0D + if (Periodic) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + return SmmClear ();=0D +}=0D +=0D +/**=0D + This function is to install an SMM Control PPI=0D + - Introduction \n=0D + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard=0D + way for other modules to trigger software SMIs.=0D +=0D + @retval EFI_SUCCESS - Ppi successfully started and installed= .=0D + @retval EFI_NOT_FOUND - Ppi can't be found.=0D + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiInstallSmmControlPpi (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PEI_PPI_DESCRIPTOR *PpiList;=0D + SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate;=0D +=0D + //=0D + // Initialize private data=0D + //=0D + SmmControlPrivate =3D AllocateZeroPool (sizeof (*SmmControlPrivate));=0D + ASSERT (SmmControlPrivate !=3D NULL);=0D + if (SmmControlPrivate =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D + PpiList =3D AllocateZeroPool (sizeof (*PpiList));=0D + ASSERT (PpiList !=3D NULL);=0D + if (PpiList =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + SmmControlPrivate->Signature =3D SMM_CONTROL_PRIVATE_DATA_SIGNATURE;=0D + SmmControlPrivate->Handle =3D NULL;=0D +=0D + SmmControlPrivate->SmmControl.Trigger =3D Activate;=0D + SmmControlPrivate->SmmControl.Clear =3D Deactivate;=0D +=0D + //=0D + // Install PPI=0D + //=0D + PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR= _TERMINATE_LIST);=0D + PpiList->Guid =3D &gEfiPeiMmControlPpiGuid;=0D + PpiList->Ppi =3D &SmmControlPrivate->SmmControl;=0D +=0D + Status =3D PeiServicesInstallPpi (PpiList);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + // Unlike driver, do not disable SMIs as S3 resume continues=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Sm= mControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf new file mode 100644 index 000000000000..91c761366446 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.inf @@ -0,0 +1,34 @@ +## @file=0D +# Library description file for the SmmControl PPI=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiSmmControlLib=0D + FILE_GUID =3D F45D521A-C0DF-4283-A3CA-65AD01B479E7= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D PEIM=0D + LIBRARY_CLASS =3D SmmControlLib=0D +=0D +[LibraryClasses]=0D + IoLib=0D + DebugLib=0D + MemoryAllocationLib=0D + PeiServicesLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiSmmControlLib.c=0D +=0D +[Pcd]=0D + gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES=0D +=0D +[Ppis]=0D + gEfiPeiMmControlPpiGuid ## PRODUCES=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h = b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h new file mode 100644 index 000000000000..b532dd13f373 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h @@ -0,0 +1,26 @@ +/** @file=0D + This is to publish the SMM Control Ppi instance.=0D +=0D + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _SMM_CONTROL_LIB_H_=0D +#define _SMM_CONTROL_LIB_H_=0D +=0D +/**=0D + This function is to install an SMM Control PPI=0D + - Introduction \n=0D + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard=0D + way for other modules to trigger software SMIs.=0D +=0D + @retval EFI_SUCCESS - Ppi successfully started and installed= .=0D + @retval EFI_NOT_FOUND - Ppi can't be found.=0D + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiInstallSmmControlPpi (=0D + VOID=0D + );=0D +#endif=0D diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index deefdc55b5d6..440c7d0255ce 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -35,6 +35,10 @@ #=0D SmmAccessLib|Include/Library/SmmAccessLib.h=0D =0D + ## @libraryclass Provides services to trigger SMI=0D + #=0D + SmmControlLib|Include/Library/SmmControlLib.h=0D +=0D ## @libraryclass Provides services to access config block=0D #=0D ConfigBlockLib|Include/Library/ConfigBlockLib.h=0D --=20 2.37.2