* [patch 0/4] Add STM (Smi Tranfer Monitor) support
@ 2016-12-16 1:48 Feng Tian
2016-12-16 1:48 ` [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments Feng Tian
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Feng Tian @ 2016-12-16 1:48 UTC (permalink / raw)
To: edk2-devel
This patch series is used to add STM support to UefiCpuPkg.
More details about STM are described in:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf
https://firmware.intel.com/sites/default/files/STM_User_Guide-001.pdf
https://firmware.intel.com/sites/default/files/A_Tour_Beyond_BIOS_Launching_STM_to_Monitor_SMM_in_EFI_Developer_Kit_II.pdf
Michael Kinney (4):
UefiCpuPkg/Include: Update MSEG structure comments
UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs
UefiCpuPkg/SmmCpuFeaturesLib: Split into two files
UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
UefiCpuPkg/Include/Guid/MsegSmram.h | 30 +
UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 141 +++
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 +-
UefiCpuPkg/Include/Register/StmApi.h | 954 ++++++++++++++
.../Include/Register/StmResourceDescriptor.h | 228 ++++
UefiCpuPkg/Include/Register/StmStatusCode.h | 78 ++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 278 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 285 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 271 ++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiException.S | 174 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.asm | 170 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.nasm | 176 +++
.../Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c | 83 ++
.../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 77 +-
.../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +-
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c | 89 ++
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 88 ++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1299 ++++++++++++++++++++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 176 +++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 282 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 281 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 263 ++++
.../Library/SmmCpuFeaturesLib/X64/SmiException.S | 178 +++
.../Library/SmmCpuFeaturesLib/X64/SmiException.asm | 178 +++
.../SmmCpuFeaturesLib/X64/SmiException.nasm | 179 +++
.../Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c | 95 ++
UefiCpuPkg/UefiCpuPkg.dec | 12 +
UefiCpuPkg/UefiCpuPkg.dsc | 8 +
28 files changed, 6036 insertions(+), 65 deletions(-)
create mode 100644 UefiCpuPkg/Include/Guid/MsegSmram.h
create mode 100644 UefiCpuPkg/Include/Protocol/SmMonitorInit.h
create mode 100644 UefiCpuPkg/Include/Register/StmApi.h
create mode 100644 UefiCpuPkg/Include/Register/StmResourceDescriptor.h
create mode 100644 UefiCpuPkg/Include/Register/StmStatusCode.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
--
2.7.1.windows.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
@ 2016-12-16 1:48 ` Feng Tian
2016-12-16 1:48 ` [patch 2/4] UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs Feng Tian
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Feng Tian @ 2016-12-16 1:48 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael Kinney, Jiewen Yao, Jeff Fan
From: Michael Kinney <michael.d.kinney@intel.com>
Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index a7a221d..a74ea51 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -484,7 +484,19 @@ typedef union {
field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
**/
typedef struct {
+ ///
+ /// Different processors may use different MSEG revision identifiers. These
+ /// identifiers enable software to avoid using an MSEG header formatted for
+ /// one processor on a processor that uses a different format. Software can
+ /// discover the MSEG revision identifier that a processor uses by reading
+ /// the VMX capability MSR IA32_VMX_MISC.
+ //
UINT32 MsegHeaderRevision;
+ ///
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical
+ /// processor will be in IA-32e mode after the STM is activated.
+ ///
UINT32 MonitorFeatures;
UINT32 GdtrLimit;
UINT32 GdtrBaseOffset;
@@ -492,12 +504,19 @@ typedef struct {
UINT32 EipOffset;
UINT32 EspOffset;
UINT32 Cr3Offset;
- //
- // Pad header so total size is 2KB
- //
+ ///
+ /// Pad header so total size is 2KB
+ ///
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
+///
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
+///
+#define STM_FEATURES_IA32E 0x1
+///
+/// @}
+///
/**
Base address of the logical processor's SMRAM image (RO, SMM only). If
--
2.7.1.windows.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [patch 2/4] UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
2016-12-16 1:48 ` [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments Feng Tian
@ 2016-12-16 1:48 ` Feng Tian
2016-12-16 1:48 ` [patch 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Split into two files Feng Tian
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Feng Tian @ 2016-12-16 1:48 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael Kinney, Jiewen Yao, Jeff Fan
From: Michael Kinney <michael.d.kinney@intel.com>
* Add GUIDed HOB that described MSEG region in SMRAM
* Add SM Monitor Init Protocol
* Add PCD to configure size of SMM exception stack
* Add PCD to configure MSEG region size if it is not
described by the gMsegSmramGuid GUIDed HOB.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/Include/Guid/MsegSmram.h | 30 +
UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 141 +++
UefiCpuPkg/Include/Register/StmApi.h | 954 +++++++++++++++++++++
.../Include/Register/StmResourceDescriptor.h | 228 +++++
UefiCpuPkg/Include/Register/StmStatusCode.h | 78 ++
UefiCpuPkg/UefiCpuPkg.dec | 12 +
6 files changed, 1443 insertions(+)
create mode 100644 UefiCpuPkg/Include/Guid/MsegSmram.h
create mode 100644 UefiCpuPkg/Include/Protocol/SmMonitorInit.h
create mode 100644 UefiCpuPkg/Include/Register/StmApi.h
create mode 100644 UefiCpuPkg/Include/Register/StmResourceDescriptor.h
create mode 100644 UefiCpuPkg/Include/Register/StmStatusCode.h
diff --git a/UefiCpuPkg/Include/Guid/MsegSmram.h b/UefiCpuPkg/Include/Guid/MsegSmram.h
new file mode 100644
index 0000000..ab337c4
--- /dev/null
+++ b/UefiCpuPkg/Include/Guid/MsegSmram.h
@@ -0,0 +1,30 @@
+/** @file
+
+ Defines the HOB GUID used to describe the MSEG memory region allocated in PEI.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MSEG_SMRAM_H_
+#define _MSEG_SMRAM_H_
+
+#define MSEG_SMRAM_GUID \
+ { \
+ 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 } \
+ }
+
+extern EFI_GUID gMsegSmramGuid;
+
+//
+// The data portion of this HOB is type EFI_SMRAM_DESCRIPTOR
+//
+
+#endif
diff --git a/UefiCpuPkg/Include/Protocol/SmMonitorInit.h b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h
new file mode 100644
index 0000000..7b0aab0
--- /dev/null
+++ b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h
@@ -0,0 +1,141 @@
+/** @file
+ STM service protocol definition
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SM_MONITOR_INIT_PROTOCOL_H_
+#define _SM_MONITOR_INIT_PROTOCOL_H_
+
+#include <PiSmm.h>
+#include <Register/StmApi.h>
+
+#define EFI_SM_MONITOR_INIT_PROTOCOL_GUID \
+ { 0x228f344d, 0xb3de, 0x43bb, 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82}
+
+//
+// STM service
+//
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval EFI_SUCCESS Load STM to MSEG successfully
+ @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG
+ @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image
+ @retval EFI_UNSUPPORTED MSEG is not enabled
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR) (
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
+ );
+
+/**
+
+ Add resources in list to database.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are added
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+ @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE) (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ );
+
+/**
+
+ Delete resources in list to database.
+
+ @param ResourceList A pointer to resource list to be deleted
+ NULL means delete all resources.
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are deleted
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE) (
+ IN STM_RSC *ResourceList OPTIONAL,
+ IN UINT32 NumEntries OPTIONAL
+ );
+
+/**
+
+ Get BIOS resources.
+
+ @param ResourceList A pointer to resource list to be filled
+ @param ResourceSize On input it means size of resource list input.
+ On output it means size of resource list filled,
+ or the size of resource list to be filled if size of too small.
+
+ @retval EFI_SUCCESS If resources are returned.
+ @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE) (
+ OUT STM_RSC *ResourceList,
+ IN OUT UINT32 *ResourceSize
+ );
+
+typedef UINT32 EFI_SM_MONITOR_STATE;
+#define EFI_SM_MONITOR_STATE_ENABLED 0x1
+#define EFI_SM_MONITOR_STATE_ACTIVATED 0x2
+
+/**
+
+ Get STM state
+
+ @return STM state
+
+**/
+typedef
+EFI_SM_MONITOR_STATE
+(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE) (
+ VOID
+ );
+
+typedef struct _EFI_SM_MONITOR_INIT_PROTOCOL {
+ //
+ // Valid at boot-time only
+ //
+ EFI_SM_MONITOR_LOAD_MONITOR LoadMonitor;
+ EFI_SM_MONITOR_ADD_PI_RESOURCE AddPiResource;
+ EFI_SM_MONITOR_DELETE_PI_RESOURCE DeletePiResource;
+ EFI_SM_MONITOR_GET_PI_RESOURCE GetPiResource;
+ //
+ // Valid at runtime
+ //
+ EFI_SM_MONITOR_GET_MONITOR_STATE GetMonitorState;
+} EFI_SM_MONITOR_INIT_PROTOCOL;
+
+extern EFI_GUID gEfiSmMonitorInitProtocolGuid;
+
+#endif
diff --git a/UefiCpuPkg/Include/Register/StmApi.h b/UefiCpuPkg/Include/Register/StmApi.h
new file mode 100644
index 0000000..6fb5971
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/StmApi.h
@@ -0,0 +1,954 @@
+/** @file
+ STM API definition
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _STM_API_H_
+#define _STM_API_H_
+
+#include <Register/StmStatusCode.h>
+#include <Register/StmResourceDescriptor.h>
+#include <Register/ArchitecturalMsr.h>
+
+#pragma pack (1)
+
+/**
+ STM Header Structures
+**/
+
+typedef struct {
+ UINT32 Intel64ModeSupported :1; ///> bitfield
+ UINT32 EptSupported :1; ///> bitfield
+ UINT32 Reserved :30; ///> must be 0
+} STM_FEAT;
+
+#define STM_SPEC_VERSION_MAJOR 1
+#define STM_SPEC_VERSION_MINOR 0
+
+typedef struct {
+ UINT8 StmSpecVerMajor;
+ UINT8 StmSpecVerMinor;
+ ///
+ /// Must be zero
+ ///
+ UINT16 Reserved;
+ UINT32 StaticImageSize;
+ UINT32 PerProcDynamicMemorySize;
+ UINT32 AdditionalDynamicMemorySize;
+ STM_FEAT StmFeatures;
+ UINT32 NumberOfRevIDs;
+ UINT32 StmSmmRevID[1];
+ ///
+ /// The total STM_HEADER should be 4K.
+ ///
+} SOFTWARE_STM_HEADER;
+
+typedef struct {
+ MSEG_HEADER HwStmHdr;
+ SOFTWARE_STM_HEADER SwStmHdr;
+} STM_HEADER;
+
+
+/**
+ VMCALL API Numbers
+ API number convention: BIOS facing VMCALL interfaces have bit 16 clear
+**/
+
+/**
+ StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
+ physical mapping of an address range into the SMM guest's virtual
+ memory space.
+
+ @param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)
+ @param EBX Low 32 bits of physical address of caller allocated
+ STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
+ @param ECX High 32 bits of physical address of caller allocated
+ STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
+ clear (0), ECX must be 0.
+
+ @note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
+ are not modified by StmMapAddressRange.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS.
+ The memory range was mapped as requested.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_SECURITY_VIOLATION
+ The requested mapping contains a protected resource.
+ @retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
+ The requested cache type could not be satisfied.
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND
+ Page count must not be zero.
+ @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
+ STM supports EPT and has not implemented StmMapAddressRange().
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_MAP_ADDRESS_RANGE 0x00000001
+
+/**
+ STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
+**/
+typedef struct {
+ UINT64 PhysicalAddress;
+ UINT64 VirtualAddress;
+ UINT32 PageCount;
+ UINT32 PatCacheType;
+} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
+
+/**
+ Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
+ @{
+**/
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF
+/// @}
+
+/**
+ StmUnmapAddressRange enables a SMM guest to remove mappings from its page
+ table.
+
+ If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
+ control its own page tables. In this case, the STM implementation may
+ optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
+
+ @param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
+ @param EBX Low 32 bits of virtual address of caller allocated
+ STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
+ @param ECX High 32 bits of virtual address of caller allocated
+ STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
+ clear (0), ECX must be zero.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The memory range was unmapped
+ as requested.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
+ STM supports EPT and has not implemented StmUnmapAddressRange().
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
+
+/**
+ STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
+**/
+typedef struct {
+ UINT64 VirtualAddress;
+ UINT32 Length;
+} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
+
+
+/**
+ Since the normal OS environment runs with a different set of page tables than
+ the SMM guest, virtual mappings will certainly be different. In order to do a
+ guest virtual to host physical translation of an address from the normal OS
+ code (EIP for example), it is necessary to walk the page tables governing the
+ OS page mappings. Since the SMM guest has no direct access to the page tables,
+ it must ask the STM to do this page table walk. This is supported via the
+ StmAddressLookup VMCALL. All OS page table formats need to be supported,
+ (e.g. PAE, PSE, Intel64, EPT, etc.)
+
+ StmAddressLookup takes a CR3 value and a virtual address from the interrupted
+ code as input and returns the corresponding physical address. It also
+ optionally maps the physical address into the SMM guest's virtual address
+ space. This new mapping persists ONLY for the duration of the SMI and if
+ needed in subsequent SMIs it must be remapped. PAT cache types follow the
+ interrupted environment's page table.
+
+ If EPT is enabled, OS CR3 only provides guest physical address information,
+ but the SMM guest might also need to know the host physical address. Since
+ SMM does not have direct access rights to EPT (it is protected by the STM),
+ SMM can input InterruptedEptp to let STM help to walk through it, and output
+ the host physical address.
+
+ @param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)
+ @param EBX Low 32 bits of virtual address of caller allocated
+ STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
+ @param ECX High 32 bits of virtual address of caller allocated
+ STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
+ clear (0), ECX must be zero.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. PhysicalAddress contains the
+ host physical address determined by walking the interrupted SMM
+ guest's page tables. SmmGuestVirtualAddress contains the SMM
+ guest's virtual mapping of the requested address.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_SECURITY_VIOLATION
+ The requested page was a protected page.
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND
+ The requested virtual address did not exist in the page given
+ page table.
+ @retval EAX #ERROR_STM_BAD_CR3
+ The CR3 input was invalid. CR3 values must be from one of the
+ interrupted guest, or from the interrupted guest of another
+ processor.
+ @retval EAX #ERROR_STM_PHYSICAL_OVER_4G
+ The resulting physical address is greater than 4G and no virtual
+ address was supplied. The STM could not determine what address
+ within the SMM guest's virtual address space to do the mapping.
+ STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
+ physical address determined by walking the interrupted
+ environment's page tables.
+ @retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
+ A specific virtual mapping was requested, but
+ SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
+ is running in 32 bit mode.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_ADDRESS_LOOKUP 0x00000003
+
+/**
+ STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
+**/
+typedef struct {
+ UINT64 InterruptedGuestVirtualAddress;
+ UINT32 Length;
+ UINT64 InterruptedCr3;
+ UINT64 InterruptedEptp;
+ UINT32 MapToSmmGuest:2;
+ UINT32 InterruptedCr4Pae:1;
+ UINT32 InterruptedCr4Pse:1;
+ UINT32 InterruptedIa32eMode:1;
+ UINT32 Reserved1:27;
+ UINT32 Reserved2;
+ UINT64 PhysicalAddress;
+ UINT64 SmmGuestVirtualAddress;
+} STM_ADDRESS_LOOKUP_DESCRIPTOR;
+
+/**
+ Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
+ @{
+**/
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3
+/// @}
+
+
+/**
+ When returning from a protection exception (see section 6.2), the SMM guest
+ can instruct the STM to take one of two paths. It can either request a value
+ be logged to the TXT.ERRORCODE register and subsequently reset the machine
+ (indicating it couldn't resolve the problem), or it can request that the STM
+ resume the SMM guest again with the specified register state.
+
+ Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
+ like a jump or an IRET instruction than a "call". It does not return directly
+ to the caller, but indirectly to a different location specified on the
+ caller's stack (see section 6.2) or not at all.
+
+ If the SMM guest STM protection exception handler itself causes a protection
+ exception (e.g. a single nested exception), or more than 100 un-nested
+ exceptions occur within the scope of a single SMI event, the STM must write
+ STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
+ assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
+ the code requirements while still enabling a reasonable debugging capability.
+
+ @param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
+ @param EBX If 0, resume SMM guest using register state found on exception
+ stack. If in range 0x01..0x0F, EBX contains a BIOS error code
+ which the STM must record in the TXT.ERRORCODE register and
+ subsequently reset the system via TXT.CMD.SYS_RESET. The value
+ of the TXT.ERRORCODE register is calculated as follows:
+
+ TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
+
+ Values 0x10..0xFFFFFFFF are reserved, do not use.
+
+**/
+#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
+
+
+/**
+ VMCALL API Numbers
+ API number convention: MLE facing VMCALL interfaces have bit 16 set.
+
+ The STM configuration lifecycle is as follows:
+ 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
+ 2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
+ setup of initial protection profile. This is done on a single CPU and
+ has global effect.
+ 3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
+ protection profile. The protection profile is global across all CPUs.
+ 4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
+ SMI events. This must be done on every logical CPU.
+ 5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
+ #STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
+ necessary.
+ 6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
+ following #STM_API_STOP VMCALL.
+**/
+
+/**
+ StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
+ should remain disabled from the invocation of GETSEC[SENTER] until they are
+ re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
+ enabled and the STM has been started and is active. Prior to invoking
+ StartStmVMCALL(), the MLE root should first invoke
+ InitializeProtectionVMCALL() followed by as many iterations of
+ ProtectResourceVMCALL() as necessary to establish the initial protection
+ profile. StartStmVmcall() must be invoked on all processor threads.
+
+ @param EAX #STM_API_START (0x00010001)
+ @param EDX STM configuration options. These provide the MLE with the
+ ability to pass configuration parameters to the STM.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The STM has been configured
+ and is now active and the guarding all requested resources.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_ALREADY_STARTED
+ The STM is already configured and active. STM remains active and
+ guarding previously enabled resource list.
+ @retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
+ The StartStmVMCALL() was invoked from VMX root mode, but outside
+ of SMX. This error code indicates the STM or platform does not
+ support the STM outside of SMX. The SMI handler remains active
+ and operates in legacy mode. See Appendix C
+ @retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT
+ The CPU doesn't support the MSR bit. The STM is not active.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_START (BIT16 | 1)
+
+/**
+ Bit values for EDX input parameter to #STM_API_START VMCALL
+ @{
+**/
+#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0
+/// @}
+
+
+/**
+ The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
+ normally done as part of a full teardown of the SMX environment when the
+ system is being shut down. At the time the call is invoked, SMI is enabled
+ and the STM is active. When the call returns, the STM has been stopped and
+ all STM context is discarded and SMI is disabled.
+
+ @param EAX #STM_API_STOP (0x00010002)
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The STM has been stopped and
+ is no longer processing SMI events. SMI is blocked.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_STOPPED
+ The STM was not active.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_STOP (BIT16 | 2)
+
+
+/**
+ The ProtectResourceVMCALL() is invoked by the MLE root to request protection
+ of specific resources. The request is defined by a STM_RESOURCE_LIST, which
+ may contain more than one resource descriptor. Each resource descriptor is
+ processed separately by the STM. Whether or not protection for any specific
+ resource is granted is returned by the STM via the ReturnStatus bit in the
+ associated STM_RSC_DESC_HEADER.
+
+ @param EAX #STM_API_PROTECT_RESOURCE (0x00010003)
+ @param EBX Low 32 bits of physical address of caller allocated
+ STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
+ making the buffer 4K aligned.
+ @param ECX High 32 bits of physical address of caller allocated
+ STM_RESOURCE_LIST.
+
+ @note All fields of STM_RESOURCE_LIST are inputs only, except for the
+ ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
+ return, the ReturnStatus bit is set for each resource request granted,
+ and clear for each resource request denied. There are no other fields
+ modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
+ contained entirely within a single 4K page.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The STM has successfully
+ merged the entire protection request into the active protection
+ profile. There is therefore no need to check the ReturnStatus
+ bits in the STM_RESOURCE_LIST.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE
+ At least one of the requested resource protections intersects a
+ BIOS required resource. Therefore, the caller must walk through
+ the STM_RESOURCE_LIST to determine which of the requested
+ resources was not granted protection. The entire list must be
+ traversed since there may be multiple failures.
+ @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
+ The resource list could not be parsed correctly, or did not
+ terminate before crossing a 4K page boundary. The caller must
+ walk through the STM_RESOURCE_LIST to determine which of the
+ requested resources was not granted protection. The entire list
+ must be traversed since there may be multiple failures.
+ @retval EAX #ERROR_STM_OUT_OF_RESOURCES
+ The STM has encountered an internal error and cannot complete
+ the request.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_PROTECT_RESOURCE (BIT16 | 3)
+
+
+/**
+ The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
+ STM allow the SMI handler access to the specified resources.
+
+ @param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)
+ @param EBX Low 32 bits of physical address of caller allocated
+ STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
+ making the buffer 4K aligned.
+ @param ECX High 32 bits of physical address of caller allocated
+ STM_RESOURCE_LIST.
+
+ @note All fields of STM_RESOURCE_LIST are inputs only, except for the
+ ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
+ return, the ReturnStatus bit is set for each resource processed. For
+ a properly formed STM_RESOURCE_LIST, this should be all resources
+ listed. There are no other fields modified by
+ UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
+ entirely within a single 4K page.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The requested resources are
+ not being guarded by the STM.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
+ The resource list could not be parsed correctly, or did not
+ terminate before crossing a 4K page boundary. The caller must
+ walk through the STM_RESOURCE_LIST to determine which of the
+ requested resources were not able to be unprotected. The entire
+ list must be traversed since there may be multiple failures.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)
+
+
+/**
+ The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
+ of BIOS required resources from the STM.
+
+ @param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)
+ @param EBX Low 32 bits of physical address of caller allocated destination
+ buffer. Bits 11:0 are ignored and assumed to be zero, making the
+ buffer 4K aligned.
+ @param ECX High 32 bits of physical address of caller allocated destination
+ buffer.
+ @param EDX Indicates which page of the BIOS resource list to copy into the
+ destination buffer. The first page is indicated by 0, the second
+ page by 1, etc.
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS. The destination buffer
+ contains the BIOS required resources. If the page retrieved is
+ the last page, EDX will be cleared to 0. If there are more pages
+ to retrieve, EDX is incremented to the next page index. Calling
+ software should iterate on GetBiosResourcesVMCALL() until EDX is
+ returned cleared to 0.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND
+ The page index supplied in EDX input was out of range.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+ @retval EDX Page index of next page to read. A return of EDX=0 signifies
+ that the entire list has been read.
+ @note EDX is both an input and an output register.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)
+
+
+/**
+ The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
+ MLE guest (including the MLE root) from the list of protected domains.
+
+ @param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
+ @param EBX Low 32 bits of physical address of caller allocated
+ STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
+ be zero, making the buffer 4K aligned.
+ @param ECX High 32 bits of physical address of caller allocated
+ STM_VMCS_DATABASE_REQUEST.
+
+ @note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not
+ modified by ManageVmcsDatabaseVMCALL().
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_INVALID_VMCS
+ Indicates a request to remove a VMCS from the database was made,
+ but the referenced VMCS was not found in the database.
+ @retval EAX #ERROR_STM_VMCS_PRESENT
+ Indicates a request to add a VMCS to the database was made, but
+ the referenced VMCS was already present in the database.
+ @retval EAX #ERROR_INVALID_PARAMETER
+ Indicates non-zero reserved field.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred
+
+ @note All other registers unmodified.
+**/
+#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)
+
+/**
+ STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
+**/
+typedef struct {
+ ///
+ /// bits 11:0 are reserved and must be 0
+ ///
+ UINT64 VmcsPhysPointer;
+ UINT32 DomainType :4;
+ UINT32 XStatePolicy :2;
+ UINT32 DegradationPolicy :4;
+ ///
+ /// Must be 0
+ ///
+ UINT32 Reserved1 :22;
+ UINT32 AddOrRemove;
+} STM_VMCS_DATABASE_REQUEST;
+
+/**
+ Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
+ @{
+**/
+#define DOMAIN_UNPROTECTED 0
+#define DOMAIN_DISALLOWED_IO_OUT BIT0
+#define DOMAIN_DISALLOWED_IO_IN BIT1
+#define DOMAIN_INTEGRITY BIT2
+#define DOMAIN_CONFIDENTIALITY BIT3
+#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
+#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
+#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
+/// @}
+
+/**
+ Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
+ @{
+**/
+#define XSTATE_READWRITE 0x00
+#define XSTATE_READONLY 0x01
+#define XSTATE_SCRUB 0x03
+/// @}
+
+/**
+ Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
+ @{
+**/
+#define STM_VMCS_DATABASE_REQUEST_ADD 1
+#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
+/// @}
+
+
+/**
+ InitializeProtectionVMCALL() prepares the STM for setup of the initial
+ protection profile which is subsequently communicated via one or more
+ invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
+ It is only necessary to invoke InitializeProtectionVMCALL() on one processor
+ thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked
+ or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
+ to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
+ MLE guest.
+
+ @param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)
+
+ @retval CF 0
+ No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
+ capabilities as defined below. The STM has set up an empty
+ protection profile, except for the resources that it sets up to
+ protect itself. The STM must not allow the SMI handler to map
+ any pages from the MSEG Base to the top of TSEG. The STM must
+ also not allow SMI handler access to those MSRs which the STM
+ requires for its own protection.
+ @retval CF 1
+ An error occurred, EAX holds relevant error value.
+ @retval EAX #ERROR_STM_ALREADY_STARTED
+ The STM is already configured and active. The STM remains active
+ and guarding the previously enabled resource list.
+ @retval EAX #ERROR_STM_UNPROTECTABLE
+ The STM determines that based on the platform configuration, the
+ STM is unable to protect itself. For example, the BIOS required
+ resource list contains memory pages in MSEG.
+ @retval EAX #ERROR_STM_UNSPECIFIED
+ An unspecified error occurred.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)
+
+/**
+ Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
+ @{
+**/
+#define STM_RSC_BGI BIT1
+#define STM_RSC_BGM BIT2
+#define STM_RSC_MSR BIT3
+/// @}
+
+
+/**
+ The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
+ feature. It consists of several sub-functions to facilitate establishment of
+ the log itself, configuring what events will be logged, and functions to
+ start, stop, and clear the log.
+
+ @param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)
+ @param EBX Low 32 bits of physical address of caller allocated
+ STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
+ assumed to be zero, making the buffer 4K aligned.
+ @param ECX High 32 bits of physical address of caller allocated
+ STM_EVENT_LOG_MANAGEMENT_REQUEST.
+
+ @retval CF=0
+ No error, EAX set to STM_SUCCESS.
+ @retval CF=1
+ An error occurred, EAX holds relevant error value. See subfunction
+ descriptions below for details.
+
+ @note All other registers unmodified.
+**/
+#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)
+
+///
+/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
+///
+typedef struct {
+ UINT32 SubFunctionIndex;
+ union {
+ struct {
+ UINT32 PageCount;
+ //
+ // number of elements is PageCount
+ //
+ UINT64 Pages[];
+ } LogBuffer;
+ //
+ // bitmap of EVENT_TYPE
+ //
+ UINT32 EventEnableBitmap;
+ } Data;
+} STM_EVENT_LOG_MANAGEMENT_REQUEST;
+
+/**
+ Defines values for the SubFunctionIndex field of
+ #STM_EVENT_LOG_MANAGEMENT_REQUEST
+ @{
+**/
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6
+/// @}
+
+/**
+ Log Entry Header
+**/
+typedef struct {
+ UINT32 EventSerialNumber;
+ UINT16 Type;
+ UINT16 Lock :1;
+ UINT16 Valid :1;
+ UINT16 ReadByMle :1;
+ UINT16 Wrapped :1;
+ UINT16 Reserved :12;
+} LOG_ENTRY_HEADER;
+
+/**
+ Enum values for the Type field of #LOG_ENTRY_HEADER
+**/
+typedef enum {
+ EvtLogStarted,
+ EvtLogStopped,
+ EvtLogInvalidParameterDetected,
+ EvtHandledProtectionException,
+ ///
+ /// unhandled protection exceptions result in reset & cannot be logged
+ ///
+ EvtBiosAccessToUnclaimedResource,
+ EvtMleResourceProtectionGranted,
+ EvtMleResourceProtectionDenied,
+ EvtMleResourceUnprotect,
+ EvtMleResourceUnprotectError,
+ EvtMleDomainTypeDegraded,
+ ///
+ /// add more here
+ ///
+ EvtMleMax,
+ ///
+ /// Not used
+ ///
+ EvtInvalid = 0xFFFFFFFF,
+} EVENT_TYPE;
+
+typedef struct {
+ UINT32 Reserved;
+} ENTRY_EVT_LOG_STARTED;
+
+typedef struct {
+ UINT32 Reserved;
+} ENTRY_EVT_LOG_STOPPED;
+
+typedef struct {
+ UINT32 VmcallApiNumber;
+} ENTRY_EVT_LOG_INVALID_PARAM;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_PROT_DENIED;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
+
+typedef struct {
+ UINT64 VmcsPhysPointer;
+ UINT8 ExpectedDomainType;
+ UINT8 DegradedDomainType;
+} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
+
+typedef union {
+ ENTRY_EVT_LOG_STARTED Started;
+ ENTRY_EVT_LOG_STOPPED Stopped;
+ ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
+ ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
+ ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
+ ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
+ ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
+ ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
+ ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
+ ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
+} LOG_ENTRY_DATA;
+
+typedef struct {
+ LOG_ENTRY_HEADER Hdr;
+ LOG_ENTRY_DATA Data;
+} STM_LOG_ENTRY;
+
+/**
+ Maximum STM Log Entry Size
+**/
+#define STM_LOG_ENTRY_SIZE 256
+
+
+/**
+ STM Protection Exception Stack Frame Structures
+**/
+
+typedef struct {
+ UINT32 Rdi;
+ UINT32 Rsi;
+ UINT32 Rbp;
+ UINT32 Rdx;
+ UINT32 Rcx;
+ UINT32 Rbx;
+ UINT32 Rax;
+ UINT32 Cr3;
+ UINT32 Cr2;
+ UINT32 Cr0;
+ UINT32 VmcsExitInstructionInfo;
+ UINT32 VmcsExitInstructionLength;
+ UINT64 VmcsExitQualification;
+ ///
+ /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
+ ///
+ UINT32 ErrorCode;
+ UINT32 Rip;
+ UINT32 Cs;
+ UINT32 Rflags;
+ UINT32 Rsp;
+ UINT32 Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
+
+typedef struct {
+ UINT64 R15;
+ UINT64 R14;
+ UINT64 R13;
+ UINT64 R12;
+ UINT64 R11;
+ UINT64 R10;
+ UINT64 R9;
+ UINT64 R8;
+ UINT64 Rdi;
+ UINT64 Rsi;
+ UINT64 Rbp;
+ UINT64 Rdx;
+ UINT64 Rcx;
+ UINT64 Rbx;
+ UINT64 Rax;
+ UINT64 Cr8;
+ UINT64 Cr3;
+ UINT64 Cr2;
+ UINT64 Cr0;
+ UINT64 VmcsExitInstructionInfo;
+ UINT64 VmcsExitInstructionLength;
+ UINT64 VmcsExitQualification;
+ ///
+ /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
+ ///
+ UINT64 ErrorCode;
+ UINT64 Rip;
+ UINT64 Cs;
+ UINT64 Rflags;
+ UINT64 Rsp;
+ UINT64 Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
+
+typedef union {
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME;
+
+/**
+ Enum values for the ErrorCode field in
+ #STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
+ #STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
+**/
+typedef enum {
+ TxtSmmPageViolation = 1,
+ TxtSmmMsrViolation,
+ TxtSmmRegisterViolation,
+ TxtSmmIoViolation,
+ TxtSmmPciViolation
+} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
+
+/**
+ TXT Pocessor SMM Descriptor (PSD) structures
+**/
+
+typedef struct {
+ UINT64 SpeRip;
+ UINT64 SpeRsp;
+ UINT16 SpeSs;
+ UINT16 PageViolationException:1;
+ UINT16 MsrViolationException:1;
+ UINT16 RegisterViolationException:1;
+ UINT16 IoViolationException:1;
+ UINT16 PciViolationException:1;
+ UINT16 Reserved1:11;
+ UINT32 Reserved2;
+} STM_PROTECTION_EXCEPTION_HANDLER;
+
+typedef struct {
+ UINT8 ExecutionDisableOutsideSmrr:1;
+ UINT8 Intel64Mode:1;
+ UINT8 Cr4Pae : 1;
+ UINT8 Cr4Pse : 1;
+ UINT8 Reserved1 : 4;
+} STM_SMM_ENTRY_STATE;
+
+typedef struct {
+ UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
+ UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request
+ UINT8 Reserved2 : 6;
+} STM_SMM_RESUME_STATE;
+
+typedef struct {
+ UINT8 DomainType : 4; ///> STM input to BIOS on each SMI
+ UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI
+ UINT8 EptEnabled : 1;
+ UINT8 Reserved3 : 1;
+} STM_SMM_STATE;
+
+#define TXT_SMM_PSD_OFFSET 0xfb00
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
+
+typedef struct {
+ UINT64 Signature;
+ UINT16 Size;
+ UINT8 SmmDescriptorVerMajor;
+ UINT8 SmmDescriptorVerMinor;
+ UINT32 LocalApicId;
+ STM_SMM_ENTRY_STATE SmmEntryState;
+ STM_SMM_RESUME_STATE SmmResumeState;
+ STM_SMM_STATE StmSmmState;
+ UINT8 Reserved4;
+ UINT16 SmmCs;
+ UINT16 SmmDs;
+ UINT16 SmmSs;
+ UINT16 SmmOtherSegment;
+ UINT16 SmmTr;
+ UINT16 Reserved5;
+ UINT64 SmmCr3;
+ UINT64 SmmStmSetupRip;
+ UINT64 SmmStmTeardownRip;
+ UINT64 SmmSmiHandlerRip;
+ UINT64 SmmSmiHandlerRsp;
+ UINT64 SmmGdtPtr;
+ UINT32 SmmGdtSize;
+ UINT32 RequiredStmSmmRevId;
+ STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
+ UINT64 Reserved6;
+ UINT64 BiosHwResourceRequirementsPtr;
+ // extend area
+ UINT64 AcpiRsdp;
+ UINT8 PhysicalAddressBits;
+} TXT_PROCESSOR_SMM_DESCRIPTOR;
+
+#pragma pack ()
+
+#endif
diff --git a/UefiCpuPkg/Include/Register/StmResourceDescriptor.h b/UefiCpuPkg/Include/Register/StmResourceDescriptor.h
new file mode 100644
index 0000000..1518462
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/StmResourceDescriptor.h
@@ -0,0 +1,228 @@
+/** @file
+ STM Resource Descriptor
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _STM_RESOURCE_DESCRIPTOR_H_
+#define _STM_RESOURCE_DESCRIPTOR_H_
+
+#pragma pack (1)
+
+/**
+ STM Resource Descriptor Header
+**/
+typedef struct {
+ UINT32 RscType;
+ UINT16 Length;
+ UINT16 ReturnStatus:1;
+ UINT16 Reserved:14;
+ UINT16 IgnoreResource:1;
+} STM_RSC_DESC_HEADER;
+
+/**
+ Define values for the RscType field of #STM_RSC_DESC_HEADER
+ @{
+**/
+#define END_OF_RESOURCES 0
+#define MEM_RANGE 1
+#define IO_RANGE 2
+#define MMIO_RANGE 3
+#define MACHINE_SPECIFIC_REG 4
+#define PCI_CFG_RANGE 5
+#define TRAPPED_IO_RANGE 6
+#define ALL_RESOURCES 7
+#define REGISTER_VIOLATION 8
+#define MAX_DESC_TYPE 8
+/// @}
+
+/**
+ STM Resource End Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT64 ResourceListContinuation;
+} STM_RSC_END;
+
+/**
+ STM Resource Memory Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT64 Base;
+ UINT64 Length;
+ UINT32 RWXAttributes:3;
+ UINT32 Reserved:29;
+ UINT32 Reserved_2;
+} STM_RSC_MEM_DESC;
+
+/**
+ Define values for the RWXAttributes field of #STM_RSC_MEM_DESC
+ @{
+**/
+#define STM_RSC_MEM_R 0x1
+#define STM_RSC_MEM_W 0x2
+#define STM_RSC_MEM_X 0x4
+/// @}
+
+/**
+ STM Resource I/O Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT16 Base;
+ UINT16 Length;
+ UINT32 Reserved;
+} STM_RSC_IO_DESC;
+
+/**
+ STM Resource MMIO Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT64 Base;
+ UINT64 Length;
+ UINT32 RWXAttributes:3;
+ UINT32 Reserved:29;
+ UINT32 Reserved_2;
+} STM_RSC_MMIO_DESC;
+
+/**
+ Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC
+ @{
+**/
+#define STM_RSC_MMIO_R 0x1
+#define STM_RSC_MMIO_W 0x2
+#define STM_RSC_MMIO_X 0x4
+/// @}
+
+/**
+ STM Resource MSR Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT32 MsrIndex;
+ UINT32 KernelModeProcessing:1;
+ UINT32 Reserved:31;
+ UINT64 ReadMask;
+ UINT64 WriteMask;
+} STM_RSC_MSR_DESC;
+
+/**
+ STM PCI Device Path node used for the PciDevicePath field of
+ #STM_RSC_PCI_CFG_DESC
+**/
+typedef struct {
+ ///
+ /// Must be 1, indicating Hardware Device Path
+ ///
+ UINT8 Type;
+ ///
+ /// Must be 1, indicating PCI
+ ///
+ UINT8 Subtype;
+ ///
+ /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
+ ///
+ UINT16 Length;
+ UINT8 PciFunction;
+ UINT8 PciDevice;
+} STM_PCI_DEVICE_PATH_NODE;
+
+/**
+ STM Resource PCI Configuration Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT16 RWAttributes:2;
+ UINT16 Reserved:14;
+ UINT16 Base;
+ UINT16 Length;
+ UINT8 OriginatingBusNumber;
+ UINT8 LastNodeIndex;
+ STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
+//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];
+} STM_RSC_PCI_CFG_DESC;
+
+/**
+ Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC
+ @{
+**/
+#define STM_RSC_PCI_CFG_R 0x1
+#define STM_RSC_PCI_CFG_W 0x2
+/// @}
+
+/**
+ STM Resource Trapped I/O Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT16 Base;
+ UINT16 Length;
+ UINT16 In:1;
+ UINT16 Out:1;
+ UINT16 Api:1;
+ UINT16 Reserved1:13;
+ UINT16 Reserved2;
+} STM_RSC_TRAPPED_IO_DESC;
+
+/**
+ STM Resource All Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+} STM_RSC_ALL_RESOURCES_DESC;
+
+/**
+ STM Register Volation Descriptor
+**/
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ UINT32 RegisterType;
+ UINT32 Reserved;
+ UINT64 ReadMask;
+ UINT64 WriteMask;
+} STM_REGISTER_VIOLATION_DESC;
+
+/**
+ Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC
+**/
+typedef enum {
+ StmRegisterCr0,
+ StmRegisterCr2,
+ StmRegisterCr3,
+ StmRegisterCr4,
+ StmRegisterCr8,
+ StmRegisterMax,
+} STM_REGISTER_VIOLATION_TYPE;
+
+/**
+ Union of all STM resource types
+**/
+typedef union {
+ STM_RSC_DESC_HEADER Header;
+ STM_RSC_END End;
+ STM_RSC_MEM_DESC Mem;
+ STM_RSC_IO_DESC Io;
+ STM_RSC_MMIO_DESC Mmio;
+ STM_RSC_MSR_DESC Msr;
+ STM_RSC_PCI_CFG_DESC PciCfg;
+ STM_RSC_TRAPPED_IO_DESC TrappedIo;
+ STM_RSC_ALL_RESOURCES_DESC All;
+ STM_REGISTER_VIOLATION_DESC RegisterViolation;
+} STM_RSC;
+
+#pragma pack ()
+
+#endif
diff --git a/UefiCpuPkg/Include/Register/StmStatusCode.h b/UefiCpuPkg/Include/Register/StmStatusCode.h
new file mode 100644
index 0000000..f1fcb8b6
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/StmStatusCode.h
@@ -0,0 +1,78 @@
+/** @file
+ STM Status Codes
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _STM_STATUS_CODE_H_
+#define _STM_STATUS_CODE_H_
+
+/**
+ STM Status Codes
+**/
+typedef UINT32 STM_STATUS;
+
+/**
+ Success code have BIT31 clear.
+ All error codes have BIT31 set.
+ STM errors have BIT16 set.
+ SMM errors have BIT17 set
+ Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.
+ STM TXT.ERRORCODE codes have BIT30 set.
+ @{
+**/
+#define STM_SUCCESS 0x00000000
+#define SMM_SUCCESS 0x00000000
+#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)
+#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)
+#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)
+#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)
+#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)
+#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)
+#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)
+#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)
+#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009)
+#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A)
+#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B)
+#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C)
+#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D)
+#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E)
+#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F)
+#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010)
+#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011)
+#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012)
+#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013)
+#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014)
+#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015)
+#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016)
+#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017)
+#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018)
+#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF)
+#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
+#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
+#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
+#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
+#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
+#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
+#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
+#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
+#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
+#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
+#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
+#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
+#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
+#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
+/// @}
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index ca56039..c37b4d5 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -60,6 +60,7 @@
[Guids]
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
+ gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
## Include/Guid/MicrocodeFmp.h
gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
@@ -68,6 +69,9 @@
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
+ ## Include/Protocol/SmMonitorInit.h
+ gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
+
#
# [Error.gUefiCpuPkgTokenSpaceGuid]
# 0x80000001 | Invalid value provided.
@@ -169,6 +173,14 @@
# @Prompt Number of reserved variable MTRRs.
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
+ ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
+ # @Prompt STM exception stack size.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
+
+ ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
+ # @Prompt MSEG size.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processors
--
2.7.1.windows.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [patch 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Split into two files
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
2016-12-16 1:48 ` [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments Feng Tian
2016-12-16 1:48 ` [patch 2/4] UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs Feng Tian
@ 2016-12-16 1:48 ` Feng Tian
2016-12-16 1:48 ` [patch 4/4] UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance Feng Tian
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Feng Tian @ 2016-12-16 1:48 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael Kinney, Jiewen Yao, Jeff Fan
From: Michael Kinney <michael.d.kinney@intel.com>
Split the default implementation of the SmmCpuFeaturesLib
into two files to prepare for the addition of the STM
specific SmmCpuFeaturesLib implementation. The STM
specific implementation installs a different SMI entry
handler and initialize the MSEG specific MSR at the end
of SmmCpuFeaturesInitializeProcessor().
This patch does not introduce any functional changes
to the default implementation of the SmmCpuFeaturesLib.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
.../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 77 ++++---------------
.../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +-
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c | 89 ++++++++++++++++++++++
3 files changed, 107 insertions(+), 62 deletions(-)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 1754f2d..31d73cd 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -41,6 +41,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
#define SMM_CODE_ACCESS_CHK_BIT BIT58
+/**
+ Internal worker function that is called to complete CPU initialization at the
+ end of SmmCpuFeaturesInitializeProcessor()
+
+**/
+VOID
+FinishSmmCpuFeaturesInitializeProcessor (
+ VOID
+ );
+
//
// Set default value to assume SMRR is not supported
//
@@ -257,7 +267,7 @@ SmmCpuFeaturesInitializeProcessor (
// Print message and halt if CPU is Monarch
//
if (IsMonarch) {
- DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
+ DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
CpuDeadLoop ();
}
} else {
@@ -296,6 +306,11 @@ SmmCpuFeaturesInitializeProcessor (
}
}
}
+
+ //
+ // Call internal worker function that completes the CPU initialization
+ //
+ FinishSmmCpuFeaturesInitializeProcessor ();
}
/**
@@ -357,66 +372,6 @@ SmmCpuFeaturesSmmRelocationComplete (
}
/**
- Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
- returned, then a custom SMI handler is not provided by this library,
- and the default SMI handler must be used.
-
- @retval 0 Use the default SMI handler.
- @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
- The caller is required to allocate enough SMRAM for each CPU to
- support the size of the custom SMI handler.
-**/
-UINTN
-EFIAPI
-SmmCpuFeaturesGetSmiHandlerSize (
- VOID
- )
-{
- return 0;
-}
-
-/**
- Install a custom SMI handler for the CPU specified by CpuIndex. This function
- is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
- than zero and is called by the CPU that was elected as monarch during System
- Management Mode initialization.
-
- @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
- The value must be between 0 and the NumberOfCpus field
- in the System Management System Table (SMST).
- @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
- @param[in] SmiStack The stack to use when an SMI is processed by the
- the CPU specified by CpuIndex.
- @param[in] StackSize The size, in bytes, if the stack used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] GdtBase The base address of the GDT to use when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] IdtBase The base address of the IDT to use when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
- processed by the CPU specified by CpuIndex.
- @param[in] Cr3 The base address of the page tables to use when an SMI
- is processed by the CPU specified by CpuIndex.
-**/
-VOID
-EFIAPI
-SmmCpuFeaturesInstallSmiHandler (
- IN UINTN CpuIndex,
- IN UINT32 SmBase,
- IN VOID *SmiStack,
- IN UINTN StackSize,
- IN UINTN GdtBase,
- IN UINTN GdtSize,
- IN UINTN IdtBase,
- IN UINTN IdtSize,
- IN UINT32 Cr3
- )
-{
-}
-
-/**
Determines if MTRR registers must be configured to set SMRAM cache-ability
when executing in System Management Mode.
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
index 1735062..77908b0 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
@@ -1,7 +1,7 @@
## @file
# The CPU specific programming for PiSmmCpuDxeSmm module.
#
-# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -24,6 +24,7 @@
[Sources]
SmmCpuFeaturesLib.c
+ SmmCpuFeaturesLibNoStm.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
new file mode 100644
index 0000000..e872eec
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
@@ -0,0 +1,89 @@
+/** @file
+The CPU specific programming for PiSmmCpuDxeSmm module when STM support
+is not included.
+
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiSmm.h>
+#include <Library/SmmCpuFeaturesLib.h>
+
+/**
+ Internal worker function that is called to complete CPU initialization at the
+ end of SmmCpuFeaturesInitializeProcessor()
+
+**/
+VOID
+FinishSmmCpuFeaturesInitializeProcessor (
+ VOID
+ )
+{
+}
+
+/**
+ Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
+ returned, then a custom SMI handler is not provided by this library,
+ and the default SMI handler must be used.
+
+ @retval 0 Use the default SMI handler.
+ @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
+ The caller is required to allocate enough SMRAM for each CPU to
+ support the size of the custom SMI handler.
+**/
+UINTN
+EFIAPI
+SmmCpuFeaturesGetSmiHandlerSize (
+ VOID
+ )
+{
+ return 0;
+}
+
+/**
+ Install a custom SMI handler for the CPU specified by CpuIndex. This function
+ is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
+ than zero and is called by the CPU that was elected as monarch during System
+ Management Mode initialization.
+
+ @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
+ The value must be between 0 and the NumberOfCpus field
+ in the System Management System Table (SMST).
+ @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
+ @param[in] SmiStack The stack to use when an SMI is processed by the
+ the CPU specified by CpuIndex.
+ @param[in] StackSize The size, in bytes, if the stack used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] GdtBase The base address of the GDT to use when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] IdtBase The base address of the IDT to use when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] Cr3 The base address of the page tables to use when an SMI
+ is processed by the CPU specified by CpuIndex.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInstallSmiHandler (
+ IN UINTN CpuIndex,
+ IN UINT32 SmBase,
+ IN VOID *SmiStack,
+ IN UINTN StackSize,
+ IN UINTN GdtBase,
+ IN UINTN GdtSize,
+ IN UINTN IdtBase,
+ IN UINTN IdtSize,
+ IN UINT32 Cr3
+ )
+{
+}
--
2.7.1.windows.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [patch 4/4] UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
` (2 preceding siblings ...)
2016-12-16 1:48 ` [patch 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Split into two files Feng Tian
@ 2016-12-16 1:48 ` Feng Tian
2016-12-19 1:00 ` [patch 0/4] Add STM (Smi Tranfer Monitor) support Fan, Jeff
2016-12-19 1:24 ` Yao, Jiewen
5 siblings, 0 replies; 7+ messages in thread
From: Feng Tian @ 2016-12-16 1:48 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael Kinney, Jiewen Yao, Jeff Fan
From: Michael Kinney <michael.d.kinney@intel.com>
Add a new instances of the SmmCpuFeaturesLib that is used by
platforms to enable the SMI Transfer Monitor(STM) feature.
This new instance is in the same directory as the default
SmmCpuFeaturesLib instance in order to share source files.
The DSC file is updated to build both SmmCpuFeatureLib
instances and to build two versions of the PiSmmCpuDxeSmm
module using each of the SmmCpuFeatureLib instances.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 278 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 285 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 271 ++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiException.S | 174 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.asm | 170 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.nasm | 176 +++
.../Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c | 83 ++
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 88 ++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1299 ++++++++++++++++++++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 176 +++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 282 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 281 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 263 ++++
.../Library/SmmCpuFeaturesLib/X64/SmiException.S | 178 +++
.../Library/SmmCpuFeaturesLib/X64/SmiException.asm | 178 +++
.../SmmCpuFeaturesLib/X64/SmiException.nasm | 179 +++
.../Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c | 95 ++
UefiCpuPkg/UefiCpuPkg.dsc | 8 +
18 files changed, 4464 insertions(+)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
new file mode 100644
index 0000000..4c0f8c8
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
@@ -0,0 +1,278 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# SmiEntry.S
+#
+# Abstract:
+#
+# Code template of the SMI handler for a particular processor
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerTemplate)
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerSize)
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerOffset)
+ASM_GLOBAL ASM_PFX(gStmSmiCr3)
+ASM_GLOBAL ASM_PFX(gStmSmiStack)
+ASM_GLOBAL ASM_PFX(gStmSmbase)
+ASM_GLOBAL ASM_PFX(gStmXdSupported)
+ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
+ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
+
+.equ MSR_IA32_MISC_ENABLE, 0x1A0
+.equ MSR_EFER, 0xc0000080
+.equ MSR_EFER_XD, 0x800
+
+#
+# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+#
+.equ DSC_OFFSET, 0xfb00
+.equ DSC_GDTPTR, 0x48
+.equ DSC_GDTSIZ, 0x50
+.equ DSC_CS, 0x14
+.equ DSC_DS, 0x16
+.equ DSC_SS, 0x18
+.equ DSC_OTHERSEG, 0x1A
+
+.equ PROTECT_MODE_CS, 0x08
+.equ PROTECT_MODE_DS, 0x20
+.equ TSS_SEGMENT, 0x40
+
+ .text
+ASM_PFX(gcStmSmiHandlerTemplate):
+
+_StmSmiEntryPoint:
+ .byte 0xbb # mov bx, imm16
+ .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
+ .byte 0x2e,0xa1 # mov ax, cs:[offset16]
+ .word DSC_OFFSET + DSC_GDTSIZ
+ decl %eax
+ movl %eax, %cs:(%edi) # mov cs:[bx], ax
+ .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
+ .word DSC_OFFSET + DSC_GDTPTR
+ movw %ax, %cs:2(%edi)
+ movw %ax, %bp # ebp = GDT base
+ .byte 0x66
+ lgdt %cs:(%edi)
+# Patch ProtectedMode Segment
+ .byte 0xb8 # mov ax, imm16
+ .word PROTECT_MODE_CS # set AX for segment directly
+ movl %eax, %cs:-2(%edi) # mov cs:[bx - 2], ax
+# Patch ProtectedMode entry
+ .byte 0x66, 0xbf # mov edi, SMBASE
+ASM_PFX(gStmSmbase): .space 4
+ .byte 0x67
+ lea ((Start32bit - _StmSmiEntryPoint) + 0x8000)(%edi), %ax
+ movw %ax, %cs:-6(%edi)
+ movl %cr0, %ebx
+ .byte 0x66
+ andl $0x9ffafff3, %ebx
+ .byte 0x66
+ orl $0x23, %ebx
+ movl %ebx, %cr0
+ .byte 0x66,0xea
+ .space 4
+ .space 2
+_StmGdtDesc: .space 4
+ .space 2
+
+Start32bit:
+ movw $PROTECT_MODE_DS, %ax
+ movl %eax,%ds
+ movl %eax,%es
+ movl %eax,%fs
+ movl %eax,%gs
+ movl %eax,%ss
+ .byte 0xbc # mov esp, imm32
+ASM_PFX(gStmSmiStack): .space 4
+ movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
+ lidt (%eax)
+ jmp ProtFlatMode
+
+ProtFlatMode:
+ .byte 0xb8 # mov eax, imm32
+ASM_PFX(gStmSmiCr3): .space 4
+ movl %eax, %cr3
+#
+# Need to test for CR4 specific bit support
+#
+ movl $1, %eax
+ cpuid # use CPUID to determine if specific CR4 bits are supported
+ xorl %eax, %eax # Clear EAX
+ testl $BIT2, %edx # Check for DE capabilities
+ jz L8
+ orl $BIT3, %eax
+L8:
+ testl $BIT6, %edx # Check for PAE capabilities
+ jz L9
+ orl $BIT5, %eax
+L9:
+ testl $BIT7, %edx # Check for MCE capabilities
+ jz L10
+ orl $BIT6, %eax
+L10:
+ testl $BIT24, %edx # Check for FXSR capabilities
+ jz L11
+ orl $BIT9, %eax
+L11:
+ testl $BIT25, %edx # Check for SSE capabilities
+ jz L12
+ orl $BIT10, %eax
+L12: # as cr4.PGE is not set here, refresh cr3
+ movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
+
+ cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
+ jz L5
+# Load TSS
+ movb $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
+ movl $TSS_SEGMENT, %eax
+ ltrw %ax
+L5:
+
+# enable NXE if supported
+ .byte 0xb0 # mov al, imm8
+ASM_PFX(gStmXdSupported): .byte 1
+ cmpb $0, %al
+ jz SkipXd
+#
+# Check XD disable bit
+#
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ pushl %edx # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L13
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L13:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+ jmp XdDone
+SkipXd:
+ subl $4, %esp
+XdDone:
+
+ movl %cr0, %ebx
+ orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
+ movl %ebx, %cr0
+ leal DSC_OFFSET(%edi),%ebx
+ movw DSC_DS(%ebx),%ax
+ movl %eax, %ds
+ movw DSC_OTHERSEG(%ebx),%ax
+ movl %eax, %es
+ movl %eax, %fs
+ movl %eax, %gs
+ movw DSC_SS(%ebx),%ax
+ movl %eax, %ss
+
+CommonHandler:
+ movl 4(%esp), %ebx
+
+ pushl %ebx
+ movl $ASM_PFX(CpuSmmDebugEntry), %eax
+ call *%eax
+ addl $4, %esp
+
+ pushl %ebx
+ movl $ASM_PFX(SmiRendezvous), %eax
+ call *%eax
+ addl $4, %esp
+
+ pushl %ebx
+ movl $ASM_PFX(CpuSmmDebugExit), %eax
+ call *%eax
+ addl $4, %esp
+
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz L16
+ popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L16
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+L16:
+ rsm
+
+_StmSmiHandler:
+#
+# Check XD disable bit
+#
+ xorl %esi, %esi
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz StmXdDone
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L14
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L14:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone:
+ push %esi
+
+ # below step is needed, because STM does not run above code.
+ # we have to run below code to set IDT/CR0/CR4
+ movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
+ lidt (%eax)
+
+ movl %cr0, %eax
+ orl $0x80010023, %eax # enable paging + WP + NE + MP + PE
+ movl %eax, %cr0
+#
+# Need to test for CR4 specific bit support
+#
+ movl $1, %eax
+ cpuid # use CPUID to determine if specific CR4 bits are supported
+ movl %cr4, %eax # init EAX
+ testl $BIT2, %edx # Check for DE capabilities
+ jz L28
+ orl $BIT3, %eax
+L28:
+ testl $BIT6, %edx # Check for PAE capabilities
+ jz L29
+ orl $BIT5, %eax
+L29:
+ testl $BIT7, %edx # Check for MCE capabilities
+ jz L30
+ orl $BIT6, %eax
+L30:
+ testl $BIT24, %edx # Check for FXSR capabilities
+ jz L31
+ orl $BIT9, %eax
+L31:
+ testl $BIT25, %edx # Check for SSE capabilities
+ jz L32
+ orl $BIT10, %eax
+L32: # as cr4.PGE is not set here, refresh cr3
+ movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
+ # STM init finish
+ jmp CommonHandler
+
+
+ASM_PFX(gcStmSmiHandlerSize) : .word . - _StmSmiEntryPoint
+ASM_PFX(gcStmSmiHandlerOffset): .word _StmSmiHandler - _StmSmiEntryPoint
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
new file mode 100644
index 0000000..94888d5
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
@@ -0,0 +1,285 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiEntry.asm
+;
+; Abstract:
+;
+; Code template of the SMI handler for a particular processor
+;
+;-------------------------------------------------------------------------------
+
+ .686p
+ .model flat,C
+ .xmm
+
+MSR_IA32_MISC_ENABLE EQU 1A0h
+MSR_EFER EQU 0c0000080h
+MSR_EFER_XD EQU 0800h
+
+;
+; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+;
+DSC_OFFSET EQU 0fb00h
+DSC_GDTPTR EQU 48h
+DSC_GDTSIZ EQU 50h
+DSC_CS EQU 14h
+DSC_DS EQU 16h
+DSC_SS EQU 18h
+DSC_OTHERSEG EQU 1Ah
+
+PROTECT_MODE_CS EQU 08h
+PROTECT_MODE_DS EQU 20h
+TSS_SEGMENT EQU 40h
+
+SmiRendezvous PROTO C
+CpuSmmDebugEntry PROTO C
+CpuSmmDebugExit PROTO C
+
+EXTERNDEF gcStmSmiHandlerTemplate:BYTE
+EXTERNDEF gcStmSmiHandlerSize:WORD
+EXTERNDEF gcStmSmiHandlerOffset:WORD
+EXTERNDEF gStmSmiCr3:DWORD
+EXTERNDEF gStmSmiStack:DWORD
+EXTERNDEF gStmSmbase:DWORD
+EXTERNDEF gStmXdSupported:BYTE
+EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
+EXTERNDEF gStmSmiHandlerIdtr:FWORD
+
+ .code
+
+gcStmSmiHandlerTemplate LABEL BYTE
+
+_StmSmiEntryPoint:
+ DB 0bbh ; mov bx, imm16
+ DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
+ DB 2eh, 0a1h ; mov ax, cs:[offset16]
+ DW DSC_OFFSET + DSC_GDTSIZ
+ dec eax
+ mov cs:[edi], eax ; mov cs:[bx], ax
+ DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
+ DW DSC_OFFSET + DSC_GDTPTR
+ mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
+ mov bp, ax ; ebp = GDT base
+ DB 66h
+ lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]
+; Patch ProtectedMode Segment
+ DB 0b8h ; mov ax, imm16
+ DW PROTECT_MODE_CS ; set AX for segment directly
+ mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax
+; Patch ProtectedMode entry
+ DB 66h, 0bfh ; mov edi, SMBASE
+gStmSmbase DD ?
+ DB 67h
+ lea ax, [edi + (@32bit - _StmSmiEntryPoint) + 8000h]
+ mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax
+ mov ebx, cr0
+ DB 66h
+ and ebx, 9ffafff3h
+ DB 66h
+ or ebx, 23h
+ mov cr0, ebx
+ DB 66h, 0eah
+ DD ?
+ DW ?
+_StmGdtDesc FWORD ?
+
+@32bit:
+ mov ax, PROTECT_MODE_DS
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+ DB 0bch ; mov esp, imm32
+gStmSmiStack DD ?
+ mov eax, offset gStmSmiHandlerIdtr
+ lidt fword ptr [eax]
+ jmp ProtFlatMode
+
+ProtFlatMode:
+ DB 0b8h ; mov eax, imm32
+gStmSmiCr3 DD ?
+ mov cr3, eax
+;
+; Need to test for CR4 specific bit support
+;
+ mov eax, 1
+ cpuid ; use CPUID to determine if specific CR4 bits are supported
+ xor eax, eax ; Clear EAX
+ test edx, BIT2 ; Check for DE capabilities
+ jz @f
+ or eax, BIT3
+@@:
+ test edx, BIT6 ; Check for PAE capabilities
+ jz @f
+ or eax, BIT5
+@@:
+ test edx, BIT7 ; Check for MCE capabilities
+ jz @f
+ or eax, BIT6
+@@:
+ test edx, BIT24 ; Check for FXSR capabilities
+ jz @f
+ or eax, BIT9
+@@:
+ test edx, BIT25 ; Check for SSE capabilities
+ jz @f
+ or eax, BIT10
+@@: ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
+
+ cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0
+ jz @F
+; Load TSS
+ mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag
+ mov eax, TSS_SEGMENT
+ ltr ax
+@@:
+
+; enable NXE if supported
+ DB 0b0h ; mov al, imm8
+gStmXdSupported DB 1
+ cmp al, 0
+ jz @SkipXd
+;
+; Check XD disable bit
+;
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ push edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+ jmp @XdDone
+@SkipXd:
+ sub esp, 4
+@XdDone:
+
+ mov ebx, cr0
+ or ebx, 080010023h ; enable paging + WP + NE + MP + PE
+ mov cr0, ebx
+ lea ebx, [edi + DSC_OFFSET]
+ mov ax, [ebx + DSC_DS]
+ mov ds, eax
+ mov ax, [ebx + DSC_OTHERSEG]
+ mov es, eax
+ mov fs, eax
+ mov gs, eax
+ mov ax, [ebx + DSC_SS]
+ mov ss, eax
+
+CommonHandler:
+ mov ebx, [esp + 4] ; CPU Index
+ push ebx
+ mov eax, CpuSmmDebugEntry
+ call eax
+ add esp, 4
+
+ push ebx
+ mov eax, SmiRendezvous
+ call eax
+ add esp, 4
+
+ push ebx
+ mov eax, CpuSmmDebugExit
+ call eax
+ add esp, 4
+
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @f
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+@@:
+ rsm
+
+_StmSmiHandler:
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone:
+ push esi
+
+ ; below step is needed, because STM does not run above code.
+ ; we have to run below code to set IDT/CR0/CR4
+ mov eax, offset gStmSmiHandlerIdtr
+ lidt fword ptr [eax]
+
+
+ mov eax, cr0
+ or eax, 80010023h ; enable paging + WP + NE + MP + PE
+ mov cr0, eax
+;
+; Need to test for CR4 specific bit support
+;
+ mov eax, 1
+ cpuid ; use CPUID to determine if specific CR4 bits are supported
+ mov eax, cr4 ; init EAX
+ test edx, BIT2 ; Check for DE capabilities
+ jz @f
+ or eax, BIT3
+@@:
+ test edx, BIT6 ; Check for PAE capabilities
+ jz @f
+ or eax, BIT5
+@@:
+ test edx, BIT7 ; Check for MCE capabilities
+ jz @f
+ or eax, BIT6
+@@:
+ test edx, BIT24 ; Check for FXSR capabilities
+ jz @f
+ or eax, BIT9
+@@:
+ test edx, BIT25 ; Check for SSE capabilities
+ jz @f
+ or eax, BIT10
+@@: ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
+ ; STM init finish
+ jmp CommonHandler
+
+gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint
+gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint
+
+ END
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
new file mode 100644
index 0000000..b1c84a4
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -0,0 +1,271 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiEntry.nasm
+;
+; Abstract:
+;
+; Code template of the SMI handler for a particular processor
+;
+;-------------------------------------------------------------------------------
+
+%define MSR_IA32_MISC_ENABLE 0x1A0
+%define MSR_EFER 0xc0000080
+%define MSR_EFER_XD 0x800
+
+;
+; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+;
+%define DSC_OFFSET 0xfb00
+%define DSC_GDTPTR 0x48
+%define DSC_GDTSIZ 0x50
+%define DSC_CS 0x14
+%define DSC_DS 0x16
+%define DSC_SS 0x18
+%define DSC_OTHERSEG 0x1a
+
+%define PROTECT_MODE_CS 0x8
+%define PROTECT_MODE_DS 0x20
+%define TSS_SEGMENT 0x40
+
+extern ASM_PFX(SmiRendezvous)
+extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
+extern ASM_PFX(CpuSmmDebugEntry)
+extern ASM_PFX(CpuSmmDebugExit)
+
+global ASM_PFX(gcStmSmiHandlerTemplate)
+global ASM_PFX(gcStmSmiHandlerSize)
+global ASM_PFX(gcStmSmiHandlerOffset)
+global ASM_PFX(gStmSmiCr3)
+global ASM_PFX(gStmSmiStack)
+global ASM_PFX(gStmSmbase)
+global ASM_PFX(gStmXdSupported)
+extern ASM_PFX(gStmSmiHandlerIdtr)
+
+ SECTION .text
+
+BITS 16
+ASM_PFX(gcStmSmiHandlerTemplate):
+_StmSmiEntryPoint:
+ mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
+ mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+ dec ax
+ mov [cs:bx], ax
+ mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov [cs:bx + 2], eax
+ mov ebp, eax ; ebp = GDT base
+o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
+ mov ax, PROTECT_MODE_CS
+ mov [cs:bx-0x2],ax
+ DB 0x66, 0xbf ; mov edi, SMBASE
+ASM_PFX(gStmSmbase): DD 0
+ lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]
+ mov [cs:bx-0x6],eax
+ mov ebx, cr0
+ and ebx, 0x9ffafff3
+ or ebx, 0x23
+ mov cr0, ebx
+ jmp dword 0x0:0x0
+_StmGdtDesc:
+ DW 0
+ DD 0
+
+BITS 32
+@32bit:
+ mov ax, PROTECT_MODE_DS
+o16 mov ds, ax
+o16 mov es, ax
+o16 mov fs, ax
+o16 mov gs, ax
+o16 mov ss, ax
+ DB 0xbc ; mov esp, imm32
+ASM_PFX(gStmSmiStack): DD 0
+ mov eax, ASM_PFX(gStmSmiHandlerIdtr)
+ lidt [eax]
+ jmp ProtFlatMode
+
+ProtFlatMode:
+ DB 0xb8 ; mov eax, imm32
+ASM_PFX(gStmSmiCr3): DD 0
+ mov cr3, eax
+;
+; Need to test for CR4 specific bit support
+;
+ mov eax, 1
+ cpuid ; use CPUID to determine if specific CR4 bits are supported
+ xor eax, eax ; Clear EAX
+ test edx, BIT2 ; Check for DE capabilities
+ jz .0
+ or eax, BIT3
+.0:
+ test edx, BIT6 ; Check for PAE capabilities
+ jz .1
+ or eax, BIT5
+.1:
+ test edx, BIT7 ; Check for MCE capabilities
+ jz .2
+ or eax, BIT6
+.2:
+ test edx, BIT24 ; Check for FXSR capabilities
+ jz .3
+ or eax, BIT9
+.3:
+ test edx, BIT25 ; Check for SSE capabilities
+ jz .4
+ or eax, BIT10
+.4: ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
+
+ cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
+ jz .6
+; Load TSS
+ mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
+ mov eax, TSS_SEGMENT
+ ltr ax
+.6:
+
+; enable NXE if supported
+ DB 0b0h ; mov al, imm8
+ASM_PFX(gStmXdSupported): DB 1
+ cmp al, 0
+ jz @SkipXd
+;
+; Check XD disable bit
+;
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ push edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .5
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.5:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+ jmp @XdDone
+@SkipXd:
+ sub esp, 4
+@XdDone:
+
+ mov ebx, cr0
+ or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
+ mov cr0, ebx
+ lea ebx, [edi + DSC_OFFSET]
+ mov ax, [ebx + DSC_DS]
+ mov ds, eax
+ mov ax, [ebx + DSC_OTHERSEG]
+ mov es, eax
+ mov fs, eax
+ mov gs, eax
+ mov ax, [ebx + DSC_SS]
+ mov ss, eax
+
+CommonHandler:
+ mov ebx, [esp + 4] ; CPU Index
+ push ebx
+ mov eax, ASM_PFX(CpuSmmDebugEntry)
+ call eax
+ add esp, 4
+
+ push ebx
+ mov eax, ASM_PFX(SmiRendezvous)
+ call eax
+ add esp, 4
+
+ push ebx
+ mov eax, ASM_PFX(CpuSmmDebugExit)
+ call eax
+ add esp, 4
+
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz .7
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .7
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.7:
+ rsm
+
+
+_StmSmiHandler:
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .5
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.5:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone:
+ push esi
+
+ ; below step is needed, because STM does not run above code.
+ ; we have to run below code to set IDT/CR0/CR4
+ mov eax, ASM_PFX(gStmSmiHandlerIdtr)
+ lidt [eax]
+
+ mov eax, cr0
+ or eax, 0x80010023 ; enable paging + WP + NE + MP + PE
+ mov cr0, eax
+;
+; Need to test for CR4 specific bit support
+;
+ mov eax, 1
+ cpuid ; use CPUID to determine if specific CR4 bits are supported
+ mov eax, cr4 ; init EAX
+ test edx, BIT2 ; Check for DE capabilities
+ jz .0
+ or eax, BIT3
+.0:
+ test edx, BIT6 ; Check for PAE capabilities
+ jz .1
+ or eax, BIT5
+.1:
+ test edx, BIT7 ; Check for MCE capabilities
+ jz .2
+ or eax, BIT6
+.2:
+ test edx, BIT24 ; Check for FXSR capabilities
+ jz .3
+ or eax, BIT9
+.3:
+ test edx, BIT25 ; Check for SSE capabilities
+ jz .4
+ or eax, BIT10
+.4: ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
+ ; STM init finish
+ jmp CommonHandler
+
+ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
+ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
new file mode 100644
index 0000000..7d0057a
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
@@ -0,0 +1,174 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# SmiException.S
+#
+# Abstract:
+#
+# Exception handlers used in SM mode
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(gcStmPsd)
+
+ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)
+ASM_GLOBAL ASM_PFX(SmmStmSetup)
+ASM_GLOBAL ASM_PFX(SmmStmTeardown)
+
+.equ MSR_IA32_MISC_ENABLE, 0x1A0
+.equ MSR_EFER, 0xc0000080
+.equ MSR_EFER_XD, 0x800
+
+.equ CODE_SEL, 0x08
+.equ DATA_SEL, 0x20
+.equ TSS_SEL, 0x40
+
+ .data
+
+ASM_PFX(gcStmPsd):
+ .ascii "TXTPSSIG"
+ .word PSD_SIZE
+ .word 1 # Version
+ .long 0 # LocalApicId
+ .byte 0x5 # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ .byte 0 # BIOS to STM
+ .byte 0 # STM to BIOS
+ .byte 0
+ .word CODE_SEL
+ .word DATA_SEL
+ .word DATA_SEL
+ .word DATA_SEL
+ .word TSS_SEL
+ .word 0
+ .quad 0 # SmmCr3
+ .long ASM_PFX(_OnStmSetup)
+ .long 0
+ .long ASM_PFX(_OnStmTeardown)
+ .long 0
+ .quad 0 # SmmSmiHandlerRip - SMM guest entrypoint
+ .quad 0 # SmmSmiHandlerRsp
+ .quad 0
+ .long 0
+ .long 0x80010100 # RequiredStmSmmRevId
+ .long ASM_PFX(_OnException)
+ .long 0
+ .quad 0 # ExceptionStack
+ .word DATA_SEL
+ .word 0x1F # ExceptionFilter
+ .long 0
+ .quad 0
+ .quad 0 # BiosHwResourceRequirementsPtr
+ .quad 0 # AcpiRsdp
+ .byte 0 # PhysicalAddressBits
+.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)
+
+ .text
+
+#------------------------------------------------------------------------------
+# SMM Exception handlers
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(_OnException)
+ASM_PFX(_OnException):
+ movl %esp, %ecx
+ pushl %ecx
+ call ASM_PFX(SmmStmExceptionHandler)
+ addl $4, %esp
+
+ movl %eax, %ebx
+ movl $4, %eax
+ .byte 0xf, 0x1, 0xc1 # VMCALL
+ jmp .
+
+ASM_GLOBAL ASM_PFX(_OnStmSetup)
+ASM_PFX(_OnStmSetup):
+#
+# Check XD disable bit
+#
+ xorl %esi, %esi
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz StmXdDone1
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L13
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L13:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone1:
+ push %esi
+
+ call ASM_PFX(SmmStmSetup)
+
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz L14
+ popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L14
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+L14:
+
+ rsm
+
+ASM_GLOBAL ASM_PFX(_OnStmTeardown)
+ASM_PFX(_OnStmTeardown):
+#
+# Check XD disable bit
+#
+ xorl %esi, %esi
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz StmXdDone2
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L15
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L15:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone2:
+ push %esi
+
+ call ASM_PFX(SmmStmTeardown)
+
+ movl $ASM_PFX(gStmXdSupported), %eax
+ movb (%eax), %al
+ cmpb $0, %al
+ jz L16
+ popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L16
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+L16:
+
+ rsm
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
new file mode 100644
index 0000000..7c04ad9
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
@@ -0,0 +1,170 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiException.asm
+;
+; Abstract:
+;
+; Exception handlers used in SM mode
+;
+;-------------------------------------------------------------------------------
+
+ .686p
+ .model flat,C
+
+EXTERNDEF gcStmPsd:BYTE
+
+EXTERNDEF SmmStmExceptionHandler:PROC
+EXTERNDEF SmmStmSetup:PROC
+EXTERNDEF SmmStmTeardown:PROC
+
+CODE_SEL = 08h
+DATA_SEL = 20h
+TSS_SEL = 40h
+
+ .data
+
+gcStmPsd LABEL BYTE
+ DB 'TXTPSSIG'
+ DW PSD_SIZE
+ DW 1 ; Version
+ DD 0 ; LocalApicId
+ DB 05h ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ DB 0 ; BIOS to STM
+ DB 0 ; STM to BIOS
+ DB 0
+ DW CODE_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW TSS_SEL
+ DW 0
+ DQ 0 ; SmmCr3
+ DQ _OnStmSetup
+ DQ _OnStmTeardown
+ DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
+ DQ 0 ; SmmSmiHandlerRsp
+ DQ 0
+ DD 0
+ DD 80010100h ; RequiredStmSmmRevId
+ DQ _OnException
+ DQ 0 ; ExceptionStack
+ DW DATA_SEL
+ DW 01Fh ; ExceptionFilter
+ DD 0
+ DQ 0
+ DQ 0 ; BiosHwResourceRequirementsPtr
+ DQ 0 ; AcpiRsdp
+ DB 0 ; PhysicalAddressBits
+PSD_SIZE = $ - offset gcStmPsd
+
+ .code
+;------------------------------------------------------------------------------
+; SMM Exception handlers
+;------------------------------------------------------------------------------
+_OnException PROC
+ mov ecx, esp
+ push ecx
+ call SmmStmExceptionHandler
+ add esp, 4
+
+ mov ebx, eax
+ mov eax, 4
+ DB 0fh, 01h, 0c1h ; VMCALL
+ jmp $
+_OnException ENDP
+
+_OnStmSetup PROC
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone1:
+ push esi
+
+ call SmmStmSetup
+
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @f
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmSetup ENDP
+
+_OnStmTeardown PROC
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone2
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone2:
+ push esi
+
+ call SmmStmTeardown
+
+ mov eax, gStmXdSupported
+ mov al, [eax]
+ cmp al, 0
+ jz @f
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmTeardown ENDP
+
+ END
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
new file mode 100644
index 0000000..0ce8501
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
@@ -0,0 +1,176 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiException.nasm
+;
+; Abstract:
+;
+; Exception handlers used in SM mode
+;
+;-------------------------------------------------------------------------------
+
+global ASM_PFX(gcStmPsd)
+
+extern ASM_PFX(SmmStmExceptionHandler)
+extern ASM_PFX(SmmStmSetup)
+extern ASM_PFX(SmmStmTeardown)
+extern ASM_PFX(gStmXdSupported)
+extern ASM_PFX(gStmSmiHandlerIdtr)
+
+%define MSR_IA32_MISC_ENABLE 0x1A0
+%define MSR_EFER 0xc0000080
+%define MSR_EFER_XD 0x800
+
+CODE_SEL equ 0x08
+DATA_SEL equ 0x20
+TSS_SEL equ 0x40
+
+ SECTION .data
+
+ASM_PFX(gcStmPsd):
+ DB 'TXTPSSIG'
+ DW PSD_SIZE
+ DW 1 ; Version
+ DD 0 ; LocalApicId
+ DB 0x05 ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ DB 0 ; BIOS to STM
+ DB 0 ; STM to BIOS
+ DB 0
+ DW CODE_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW TSS_SEL
+ DW 0
+ DQ 0 ; SmmCr3
+ DD ASM_PFX(OnStmSetup)
+ DD 0
+ DD ASM_PFX(OnStmTeardown)
+ DD 0
+ DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
+ DQ 0 ; SmmSmiHandlerRsp
+ DQ 0
+ DD 0
+ DD 0x80010100 ; RequiredStmSmmRevId
+ DD ASM_PFX(OnException)
+ DD 0
+ DQ 0 ; ExceptionStack
+ DW DATA_SEL
+ DW 0x01F ; ExceptionFilter
+ DD 0
+ DD 0
+ DD 0
+ DQ 0 ; BiosHwResourceRequirementsPtr
+ DQ 0 ; AcpiRsdp
+ DB 0 ; PhysicalAddressBits
+PSD_SIZE equ $ - ASM_PFX(gcStmPsd)
+
+ SECTION .text
+;------------------------------------------------------------------------------
+; SMM Exception handlers
+;------------------------------------------------------------------------------
+global ASM_PFX(OnException)
+ASM_PFX(OnException):
+ mov ecx, esp
+ push ecx
+ call ASM_PFX(SmmStmExceptionHandler)
+ add esp, 4
+
+ mov ebx, eax
+ mov eax, 4
+ DB 0x0f, 0x01, 0x0c1 ; VMCALL
+ jmp $
+
+global ASM_PFX(OnStmSetup)
+ASM_PFX(OnStmSetup):
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .51
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.51:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone1:
+ push esi
+
+ call ASM_PFX(SmmStmSetup)
+
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz .71
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .71
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.71:
+ rsm
+
+global ASM_PFX(OnStmTeardown)
+ASM_PFX(OnStmTeardown):
+;
+; Check XD disable bit
+;
+ xor esi, esi
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz @StmXdDone2
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .52
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.52:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone2:
+ push esi
+
+ call ASM_PFX(SmmStmTeardown)
+
+ mov eax, ASM_PFX(gStmXdSupported)
+ mov al, [eax]
+ cmp al, 0
+ jz .72
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .72
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.72:
+ rsm
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
new file mode 100644
index 0000000..0154c7c
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
@@ -0,0 +1,83 @@
+/** @file
+ SMM STM support functions
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiSmm.h>
+#include <Library/DebugLib.h>
+
+#include "SmmStm.h"
+
+///
+/// Page Table Entry
+///
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_PS BIT7
+
+/**
+
+ Create 4G page table for STM.
+ 4M Non-PAE page table in IA32 version.
+
+ @param PageTableBase The page table base in MSEG
+
+**/
+VOID
+StmGen4GPageTable (
+ IN UINTN PageTableBase
+ )
+{
+ UINTN Index;
+ UINT32 *Pte;
+ UINT32 Address;
+
+ Pte = (UINT32*)(UINTN)PageTableBase;
+
+ Address = 0;
+ for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {
+ *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
+ Pte++;
+ Address += SIZE_4MB;
+ }
+}
+
+/**
+ This is SMM exception handle.
+ Consumed by STM when exception happen.
+
+ @param Context STM protection exception stack frame
+
+ @return the EBX value for STM reference.
+ EBX = 0: resume SMM guest using register state found on exception stack.
+ EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the
+ TXT.ERRORCODE register and subsequently reset the system via
+ TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as
+ follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
+ EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
+
+**/
+UINT32
+EFIAPI
+SmmStmExceptionHandler (
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ )
+{
+ // TBD - SmmStmExceptionHandler, record information
+ DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));
+ //
+ // Skip this instruction and continue;
+ //
+ Context.Ia32StackFrame->Rip += Context.Ia32StackFrame->VmcsExitInstructionLength;
+
+ return 0;
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
new file mode 100644
index 0000000..db8dcdc
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
@@ -0,0 +1,88 @@
+## @file
+# The CPU specific programming for PiSmmCpuDxeSmm module when STM support
+# is included.
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmCpuFeaturesLibStm
+ MODULE_UNI_FILE = SmmCpuFeaturesLib.uni
+ FILE_GUID = 374DE830-81C5-4CC8-B2AB-28F0AB73710B
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SmmCpuFeaturesLib
+ CONSTRUCTOR = SmmCpuFeaturesLibStmConstructor
+
+[Sources]
+ SmmCpuFeaturesLib.c
+ SmmStm.c
+ SmmStm.h
+
+[Sources.Ia32]
+ Ia32/SmmStmSupport.c
+
+ Ia32/SmiEntry.asm
+ Ia32/SmiException.asm
+
+ Ia32/SmiEntry.nasm
+ Ia32/SmiException.nasm
+
+ Ia32/SmiEntry.S
+ Ia32/SmiException.S
+
+[Sources.X64]
+ X64/SmmStmSupport.c
+
+ X64/SmiEntry.asm
+ X64/SmiException.asm
+
+ X64/SmiEntry.nasm
+ X64/SmiException.nasm
+
+ X64/SmiEntry.S
+ X64/SmiException.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ HobLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ SmmServicesTableLib
+ TpmMeasurementLib
+
+[Protocols]
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiSmmEndOfDxeProtocolGuid ## CONSUMES
+ gEfiSmMonitorInitProtocolGuid ## PRODUCES
+
+[Guids]
+ gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB
+ gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## SystemTable
+ gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## SystemTable
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES
+
+[Depex]
+ gEfiMpServiceProtocolGuid
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
new file mode 100644
index 0000000..59c49e3
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -0,0 +1,1299 @@
+/** @file
+ SMM STM support functions
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiSmm.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/TpmMeasurementLib.h>
+#include <Register/Cpuid.h>
+#include <Register/ArchitecturalMsr.h>
+#include <Register/SmramSaveStateMap.h>
+
+#include <Protocol/MpService.h>
+
+#include "SmmStm.h"
+
+#define TXT_EVTYPE_BASE 0x400
+#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
+
+#define RDWR_ACCS 3
+#define FULL_ACCS 7
+
+/**
+ The constructor function
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+EFI_HANDLE mStmSmmCpuHandle = NULL;
+
+BOOLEAN mLockLoadMonitor = FALSE;
+
+//
+// Template of STM_RSC_END structure for copying.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = {
+ {END_OF_RESOURCES, sizeof (STM_RSC_END)},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 *mStmResourcesPtr = NULL;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mStmResourceTotalSize = 0x0;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mStmResourceSizeUsed = 0x0;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mStmResourceSizeAvailable = 0x0;
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mStmState = 0;
+
+//
+// System Configuration Table pointing to STM Configuration Table
+//
+GLOBAL_REMOVE_IF_UNREFERENCED
+EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
+ LoadMonitor,
+ AddPiResource,
+ DeletePiResource,
+ GetPiResource,
+ GetMonitorState,
+};
+
+
+
+
+#define CPUID1_EDX_XD_SUPPORT 0x100000
+
+//
+// External global variables associated with SMI Handler Template
+//
+extern CONST TXT_PROCESSOR_SMM_DESCRIPTOR gcStmPsd;
+extern UINT32 gStmSmbase;
+extern volatile UINT32 gStmSmiStack;
+extern UINT32 gStmSmiCr3;
+extern volatile UINT8 gcStmSmiHandlerTemplate[];
+extern CONST UINT16 gcStmSmiHandlerSize;
+extern UINT16 gcStmSmiHandlerOffset;
+extern BOOLEAN gStmXdSupported;
+
+//
+// Variables used by SMI Handler
+//
+IA32_DESCRIPTOR gStmSmiHandlerIdtr;
+
+//
+// MP Services Protocol
+//
+EFI_MP_SERVICES_PROTOCOL *mSmmCpuFeaturesLibMpService = NULL;
+
+//
+// MSEG Base and Length in SMRAM
+//
+UINTN mMsegBase = 0;
+UINTN mMsegSize = 0;
+
+BOOLEAN mStmConfigurationTableInitialized = FALSE;
+
+
+/**
+ The constructor function
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesLibStmConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ CPUID_VERSION_INFO_ECX RegEcx;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
+
+ //
+ // Call the common constructor function
+ //
+ Status = SmmCpuFeaturesLibConstructor (ImageHandle, SystemTable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Lookup the MP Services Protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **)&mSmmCpuFeaturesLibMpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // If CPU supports VMX, then determine SMRAM range for MSEG.
+ //
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &RegEcx.Uint32, NULL);
+ if (RegEcx.Bits.VMX == 1) {
+ GuidHob = GetFirstGuidHob (&gMsegSmramGuid);
+ if (GuidHob != NULL) {
+ //
+ // Retrieve MSEG location from MSEG SRAM HOB
+ //
+ SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
+ if (SmramDescriptor->PhysicalSize > 0) {
+ mMsegBase = (UINTN)SmramDescriptor->CpuStart;
+ mMsegSize = (UINTN)SmramDescriptor->PhysicalSize;
+ }
+ } else if (PcdGet32 (PcdCpuMsegSize) > 0) {
+ //
+ // Allocate MSEG from SMRAM memory
+ //
+ mMsegBase = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuMsegSize)));
+ if (mMsegBase > 0) {
+ mMsegSize = ALIGN_VALUE (PcdGet32 (PcdCpuMsegSize), EFI_PAGE_SIZE);
+ } else {
+ DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize)));
+ }
+ }
+ if (mMsegBase > 0) {
+ DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Internal worker function that is called to complete CPU initialization at the
+ end of SmmCpuFeaturesInitializeProcessor()
+
+**/
+VOID
+FinishSmmCpuFeaturesInitializeProcessor (
+ VOID
+ )
+{
+ MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
+
+ //
+ // Set MSEG Base Address in SMM Monitor Control MSR.
+ //
+ if (mMsegBase > 0) {
+ SmmMonitorCtl.Uint64 = 0;
+ SmmMonitorCtl.Bits.MsegBase = (UINT32)mMsegBase >> 12;
+ SmmMonitorCtl.Bits.Valid = 1;
+ AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, SmmMonitorCtl.Uint64);
+ }
+}
+
+/**
+ Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
+ returned, then a custom SMI handler is not provided by this library,
+ and the default SMI handler must be used.
+
+ @retval 0 Use the default SMI handler.
+ @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
+ The caller is required to allocate enough SMRAM for each CPU to
+ support the size of the custom SMI handler.
+**/
+UINTN
+EFIAPI
+SmmCpuFeaturesGetSmiHandlerSize (
+ VOID
+ )
+{
+ return gcStmSmiHandlerSize;
+}
+
+/**
+ Install a custom SMI handler for the CPU specified by CpuIndex. This function
+ is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
+ than zero and is called by the CPU that was elected as monarch during System
+ Management Mode initialization.
+
+ @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
+ The value must be between 0 and the NumberOfCpus field
+ in the System Management System Table (SMST).
+ @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
+ @param[in] SmiStack The stack to use when an SMI is processed by the
+ the CPU specified by CpuIndex.
+ @param[in] StackSize The size, in bytes, if the stack used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] GdtBase The base address of the GDT to use when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] IdtBase The base address of the IDT to use when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
+ processed by the CPU specified by CpuIndex.
+ @param[in] Cr3 The base address of the page tables to use when an SMI
+ is processed by the CPU specified by CpuIndex.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInstallSmiHandler (
+ IN UINTN CpuIndex,
+ IN UINT32 SmBase,
+ IN VOID *SmiStack,
+ IN UINTN StackSize,
+ IN UINTN GdtBase,
+ IN UINTN GdtSize,
+ IN UINTN IdtBase,
+ IN UINTN IdtSize,
+ IN UINT32 Cr3
+ )
+{
+ EFI_STATUS Status;
+ TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
+ VOID *Hob;
+ UINT32 RegEax;
+ UINT32 RegEdx;
+ EFI_PROCESSOR_INFORMATION ProcessorInfo;
+
+ CopyMem ((VOID *)(UINTN)(SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof (gcStmPsd));
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + TXT_SMM_PSD_OFFSET);
+ Psd->SmmGdtPtr = GdtBase;
+ Psd->SmmGdtSize = (UINT32)GdtSize;
+
+ //
+ // Initialize values in template before copy
+ //
+ gStmSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
+ gStmSmiCr3 = Cr3;
+ gStmSmbase = SmBase;
+ gStmSmiHandlerIdtr.Base = IdtBase;
+ gStmSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
+
+ if (gStmXdSupported) {
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
+ if (RegEax <= CPUID_EXTENDED_FUNCTION) {
+ //
+ // Extended CPUID functions are not supported on this processor.
+ //
+ gStmXdSupported = FALSE;
+ }
+
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
+ if ((RegEdx & CPUID1_EDX_XD_SUPPORT) == 0) {
+ //
+ // Execute Disable Bit feature is not supported on this processor.
+ //
+ gStmXdSupported = FALSE;
+ }
+ }
+
+ //
+ // Set the value at the top of the CPU stack to the CPU Index
+ //
+ *(UINTN*)(UINTN)gStmSmiStack = CpuIndex;
+
+ //
+ // Copy template to CPU specific SMI handler location
+ //
+ CopyMem (
+ (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET),
+ (VOID*)gcStmSmiHandlerTemplate,
+ gcStmSmiHandlerSize
+ );
+
+ Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset;
+ Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN);
+ Psd->SmmCr3 = Cr3;
+
+ DEBUG((DEBUG_ERROR, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32(PcdCpuSmmStmExceptionStackSize)));
+ DEBUG((DEBUG_ERROR, "Pages - %x\n", EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize))));
+ Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
+ Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
+
+ Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource ();
+
+ //
+ // Get the APIC ID for the CPU specified by CpuIndex
+ //
+ Status = mSmmCpuFeaturesLibMpService->GetProcessorInfo (
+ mSmmCpuFeaturesLibMpService,
+ CpuIndex,
+ &ProcessorInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Psd->LocalApicId = (UINT32)ProcessorInfo.ProcessorId;
+ Psd->AcpiRsdp = 0;
+
+ Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
+ if (Hob != NULL) {
+ Psd->PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
+ } else {
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ Psd->PhysicalAddressBits = (UINT8) RegEax;
+ } else {
+ Psd->PhysicalAddressBits = 36;
+ }
+ }
+
+ if (!mStmConfigurationTableInitialized) {
+ StmSmmConfigurationTableInit ();
+ mStmConfigurationTableInitialized = TRUE;
+ }
+}
+
+/**
+ SMM End Of Dxe event notification handler.
+
+ STM support need patch AcpiRsdp in TXT_PROCESSOR_SMM_DESCRIPTOR.
+
+ @param[in] Protocol Points to the protocol's unique identifier.
+ @param[in] Interface Points to the interface instance.
+ @param[in] Handle The handle on which the interface was installed.
+
+ @retval EFI_SUCCESS Notification handler runs successfully.
+**/
+EFI_STATUS
+EFIAPI
+SmmEndOfDxeEventNotify (
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ VOID *Rsdp;
+ UINTN Index;
+ TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
+
+ DEBUG ((DEBUG_INFO, "SmmEndOfDxeEventNotify\n"));
+
+ //
+ // found ACPI table RSD_PTR from system table
+ //
+ Rsdp = NULL;
+ for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
+ if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi20TableGuid)) {
+ //
+ // A match was found.
+ //
+ Rsdp = gST->ConfigurationTable[Index].VendorTable;
+ break;
+ }
+ }
+ if (Rsdp == NULL) {
+ for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
+ if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) {
+ //
+ // A match was found.
+ //
+ Rsdp = gST->ConfigurationTable[Index].VendorTable;
+ break;
+ }
+ }
+ }
+
+ for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
+ DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd, Rsdp));
+ Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
+ }
+
+ mLockLoadMonitor = TRUE;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function initializes the STM configuration table.
+**/
+VOID
+StmSmmConfigurationTableInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *Registration;
+
+ Status = gSmst->SmmInstallProtocolInterface (
+ &mStmSmmCpuHandle,
+ &gEfiSmMonitorInitProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mSmMonitorInitProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ //
+ // Register SMM End of DXE Event
+ //
+ Status = gSmst->SmmRegisterProtocolNotify (
+ &gEfiSmmEndOfDxeProtocolGuid,
+ SmmEndOfDxeEventNotify,
+ &Registration
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+
+ Get STM state.
+
+ @return STM state
+
+**/
+EFI_SM_MONITOR_STATE
+EFIAPI
+GetMonitorState (
+ VOID
+ )
+{
+ return mStmState;
+}
+
+/**
+
+ Handle single Resource to see if it can be merged into Record.
+
+ @param Resource A pointer to resource node to be added
+ @param Record A pointer to record node to be merged
+
+ @retval TRUE resource handled
+ @retval FALSE resource is not handled
+
+**/
+BOOLEAN
+HandleSingleResource (
+ IN STM_RSC *Resource,
+ IN STM_RSC *Record
+ )
+{
+ UINT64 ResourceLo;
+ UINT64 ResourceHi;
+ UINT64 RecordLo;
+ UINT64 RecordHi;
+
+ ResourceLo = 0;
+ ResourceHi = 0;
+ RecordLo = 0;
+ RecordHi = 0;
+
+ //
+ // Calling code is responsible for making sure that
+ // Resource->Header.RscType == (*Record)->Header.RscType
+ // thus we use just one of them as switch variable.
+ //
+ switch (Resource->Header.RscType) {
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ ResourceLo = Resource->Mem.Base;
+ ResourceHi = Resource->Mem.Base + Resource->Mem.Length;
+ RecordLo = Record->Mem.Base;
+ RecordHi = Record->Mem.Base + Record->Mem.Length;
+ if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ }
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ ResourceLo = (UINT64) Resource->Io.Base;
+ ResourceHi = (UINT64) Resource->Io.Base + (UINT64) Resource->Io.Length;
+ RecordLo = (UINT64) Record->Io.Base;
+ RecordHi = (UINT64) Record->Io.Base + (UINT64) Record->Io.Length;
+ break;
+ case PCI_CFG_RANGE:
+ if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
+ (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) {
+ return FALSE;
+ }
+ if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
+ return FALSE;
+ }
+ ResourceLo = (UINT64) Resource->PciCfg.Base;
+ ResourceHi = (UINT64) Resource->PciCfg.Base + (UINT64) Resource->PciCfg.Length;
+ RecordLo = (UINT64) Record->PciCfg.Base;
+ RecordHi = (UINT64) Record->PciCfg.Base + (UINT64) Record->PciCfg.Length;
+ if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ }
+ break;
+ case MACHINE_SPECIFIC_REG:
+ //
+ // Special case - merge MSR masks in place.
+ //
+ if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
+ return FALSE;
+ }
+ Record->Msr.ReadMask |= Resource->Msr.ReadMask;
+ Record->Msr.WriteMask |= Resource->Msr.WriteMask;
+ return TRUE;
+ default:
+ return FALSE;
+ }
+ //
+ // If resources are disjoint
+ //
+ if ((ResourceHi < RecordLo) || (ResourceLo > RecordHi)) {
+ return FALSE;
+ }
+
+ //
+ // If resource is consumed by record.
+ //
+ if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {
+ return TRUE;
+ }
+ //
+ // Resources are overlapping.
+ // Resource and record are merged.
+ //
+ ResourceLo = (ResourceLo < RecordLo) ? ResourceLo : RecordLo;
+ ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi;
+
+ switch (Resource->Header.RscType) {
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ Record->Mem.Base = ResourceLo;
+ Record->Mem.Length = ResourceHi - ResourceLo;
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ Record->Io.Base = (UINT16) ResourceLo;
+ Record->Io.Length = (UINT16) (ResourceHi - ResourceLo);
+ break;
+ case PCI_CFG_RANGE:
+ Record->PciCfg.Base = (UINT16) ResourceLo;
+ Record->PciCfg.Length = (UINT16) (ResourceHi - ResourceLo);
+ break;
+ default:
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+
+ Add resource node.
+
+ @param Resource A pointer to resource node to be added
+
+**/
+VOID
+AddSingleResource (
+ IN STM_RSC *Resource
+ )
+{
+ STM_RSC *Record;
+
+ Record = (STM_RSC *)mStmResourcesPtr;
+
+ while (TRUE) {
+ if (Record->Header.RscType == END_OF_RESOURCES) {
+ break;
+ }
+ //
+ // Go to next record if resource and record types don't match.
+ //
+ if (Resource->Header.RscType != Record->Header.RscType) {
+ Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
+ continue;
+ }
+ //
+ // Record is handled inside of procedure - don't adjust.
+ //
+ if (HandleSingleResource (Resource, Record)) {
+ return ;
+ }
+ Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
+ }
+
+ //
+ // Add resource to the end of area.
+ //
+ CopyMem (
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode),
+ Resource,
+ Resource->Header.Length
+ );
+ CopyMem (
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length,
+ &mRscEndNode,
+ sizeof(mRscEndNode)
+ );
+ mStmResourceSizeUsed += Resource->Header.Length;
+ mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed;
+
+ return ;
+}
+
+/**
+
+ Add resource list.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+**/
+VOID
+AddResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ )
+{
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
+
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Resource->Header.RscType == END_OF_RESOURCES) {
+ return ;
+ }
+ AddSingleResource (Resource);
+ Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
+ }
+ return ;
+}
+
+/**
+
+ Validate resource list.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval TRUE resource valid
+ @retval FALSE resource invalid
+
+**/
+BOOLEAN
+ValidateResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ )
+{
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
+ UINTN SubIndex;
+
+ //
+ // If NumEntries == 0 make it very big. Scan will be terminated by
+ // END_OF_RESOURCES.
+ //
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ //
+ // Start from beginning of resource list.
+ //
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ DEBUG ((DEBUG_ERROR, "ValidateResource (%d) - RscType(%x)\n", Index, Resource->Header.RscType));
+ //
+ // Validate resource.
+ //
+ switch (Resource->Header.RscType) {
+ case END_OF_RESOURCES:
+ if (Resource->Header.Length != sizeof (STM_RSC_END)) {
+ return FALSE;
+ }
+ //
+ // If we are passed actual number of resources to add,
+ // END_OF_RESOURCES structure between them is considered an
+ // error. If NumEntries == 0 END_OF_RESOURCES is a termination.
+ //
+ if (NumEntries != 0) {
+ return FALSE;
+ } else {
+ //
+ // If NumEntries == 0 and list reached end - return success.
+ //
+ return TRUE;
+ }
+ break;
+
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ if (Resource->Header.Length != sizeof (STM_RSC_MEM_DESC)) {
+ return FALSE;
+ }
+
+ if (Resource->Mem.RWXAttributes > FULL_ACCS) {
+ return FALSE;
+ }
+ break;
+
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ if (Resource->Header.Length != sizeof (STM_RSC_IO_DESC)) {
+ return FALSE;
+ }
+
+ if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {
+ return FALSE;
+ }
+ break;
+
+ case PCI_CFG_RANGE:
+ DEBUG ((DEBUG_ERROR, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction));
+ if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
+ return FALSE;
+ }
+ for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {
+ if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {
+ return FALSE;
+ }
+ }
+ if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {
+ return FALSE;
+ }
+ break;
+
+ case MACHINE_SPECIFIC_REG:
+ if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {
+ return FALSE;
+ }
+ break;
+
+ default :
+ DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType));
+ return FALSE;
+ }
+ Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
+ }
+ return TRUE;
+}
+
+/**
+
+ Get resource list.
+ EndResource is excluded.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval TRUE resource valid
+ @retval FALSE resource invalid
+
+**/
+UINTN
+GetResourceSize (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ )
+{
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
+
+ Resource = ResourceList;
+
+ //
+ // If NumEntries == 0 make it very big. Scan will be terminated by
+ // END_OF_RESOURCES.
+ //
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ //
+ // Start from beginning of resource list.
+ //
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Resource->Header.RscType == END_OF_RESOURCES) {
+ break;
+ }
+ Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
+ }
+
+ return (UINTN)Resource - (UINTN)ResourceList;
+}
+
+/**
+
+ Add resources in list to database. Allocate new memory areas as needed.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are added
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+ @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas.
+
+**/
+EFI_STATUS
+EFIAPI
+AddPiResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ UINTN ResourceSize;
+ EFI_PHYSICAL_ADDRESS NewResource;
+ UINTN NewResourceSize;
+
+ DEBUG ((DEBUG_INFO, "AddPiResource - Enter\n"));
+
+ if (!ValidateResource (ResourceList, NumEntries)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ResourceSize = GetResourceSize (ResourceList, NumEntries);
+ DEBUG ((DEBUG_INFO, "ResourceSize - 0x%08x\n", ResourceSize));
+ if (ResourceSize == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (mStmResourcesPtr == NULL) {
+ //
+ // First time allocation
+ //
+ NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof(mRscEndNode)));
+ DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize));
+ Status = gSmst->SmmAllocatePages (
+ AllocateAnyPages,
+ EfiRuntimeServicesData,
+ EFI_SIZE_TO_PAGES (NewResourceSize),
+ &NewResource
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Copy EndResource for intialization
+ //
+ mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
+ mStmResourceTotalSize = NewResourceSize;
+ CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
+ mStmResourceSizeUsed = sizeof(mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+
+ //
+ // Let SmmCore change resource ptr
+ //
+ NotifyStmResourceChange (mStmResourcesPtr);
+ } else if (mStmResourceSizeAvailable < ResourceSize) {
+ //
+ // Need enlarge
+ //
+ NewResourceSize = mStmResourceTotalSize + (ResourceSize - mStmResourceSizeAvailable);
+ NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (NewResourceSize));
+ DEBUG ((DEBUG_INFO, "ReAllocate - 0x%08x\n", NewResourceSize));
+ Status = gSmst->SmmAllocatePages (
+ AllocateAnyPages,
+ EfiRuntimeServicesData,
+ EFI_SIZE_TO_PAGES (NewResourceSize),
+ &NewResource
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed);
+ mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed;
+
+ gSmst->SmmFreePages (
+ (EFI_PHYSICAL_ADDRESS)(UINTN)mStmResourcesPtr,
+ EFI_SIZE_TO_PAGES (mStmResourceTotalSize)
+ );
+
+ mStmResourceTotalSize = NewResourceSize;
+ mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
+
+ //
+ // Let SmmCore change resource ptr
+ //
+ NotifyStmResourceChange (mStmResourcesPtr);
+ }
+
+ //
+ // Check duplication
+ //
+ AddResource (ResourceList, NumEntries);
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Delete resources in list to database.
+
+ @param ResourceList A pointer to resource list to be deleted
+ NULL means delete all resources.
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are deleted
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+
+**/
+EFI_STATUS
+EFIAPI
+DeletePiResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ )
+{
+ if (ResourceList != NULL) {
+ // TBD
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Delete all
+ //
+ CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
+ mStmResourceSizeUsed = sizeof(mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Get BIOS resources.
+
+ @param ResourceList A pointer to resource list to be filled
+ @param ResourceSize On input it means size of resource list input.
+ On output it means size of resource list filled,
+ or the size of resource list to be filled if size of too small.
+
+ @retval EFI_SUCCESS If resources are returned.
+ @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetPiResource (
+ OUT STM_RSC *ResourceList,
+ IN OUT UINT32 *ResourceSize
+ )
+{
+ if (*ResourceSize < mStmResourceSizeUsed) {
+ *ResourceSize = (UINT32)mStmResourceSizeUsed;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ CopyMem (ResourceList, mStmResourcesPtr, mStmResourceSizeUsed);
+ *ResourceSize = (UINT32)mStmResourceSizeUsed;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Set valid bit for MSEG MSR.
+
+ @param Buffer Ap function buffer. (not used)
+
+**/
+VOID
+EFIAPI
+EnableMsegMsr (
+ IN VOID *Buffer
+ )
+{
+ MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
+
+ SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
+ SmmMonitorCtl.Bits.Valid = 1;
+ AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, SmmMonitorCtl.Uint64);
+}
+
+/**
+
+ Get 4K page aligned VMCS size.
+
+ @return 4K page aligned VMCS size
+
+**/
+UINT32
+GetVmcsSize (
+ VOID
+ )
+{
+ MSR_IA32_VMX_BASIC_REGISTER VmxBasic;
+
+ //
+ // Read VMCS size and and align to 4KB
+ //
+ VmxBasic.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
+ return ALIGN_VALUE (VmxBasic.Bits.VmcsSize, SIZE_4KB);
+}
+
+/**
+
+ Check STM image size.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval TRUE check pass
+ @retval FALSE check fail
+**/
+BOOLEAN
+StmCheckStmImage (
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
+ )
+{
+ UINTN MinMsegSize;
+ STM_HEADER *StmHeader;
+ IA32_VMX_MISC_REGISTER VmxMiscMsr;
+
+ //
+ // Check to see if STM image is compatible with CPU
+ //
+ StmHeader = (STM_HEADER *)(UINTN)StmImage;
+ VmxMiscMsr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
+ if (StmHeader->HwStmHdr.MsegHeaderRevision != VmxMiscMsr.Bits.MsegRevisionIdentifier) {
+ DEBUG ((DEBUG_ERROR, "STM Image not compatible with CPU\n"));
+ DEBUG ((DEBUG_ERROR, " StmHeader->HwStmHdr.MsegHeaderRevision = %08x\n", StmHeader->HwStmHdr.MsegHeaderRevision));
+ DEBUG ((DEBUG_ERROR, " VmxMiscMsr.Bits.MsegRevisionIdentifier = %08x\n", VmxMiscMsr.Bits.MsegRevisionIdentifier));
+ return FALSE;
+ }
+
+ //
+ // Get Minimal required Mseg size
+ //
+ MinMsegSize = (EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (StmHeader->SwStmHdr.StaticImageSize)) +
+ StmHeader->SwStmHdr.AdditionalDynamicMemorySize +
+ (StmHeader->SwStmHdr.PerProcDynamicMemorySize + GetVmcsSize () * 2) * gSmst->NumberOfCpus);
+ if (MinMsegSize < StmImageSize) {
+ MinMsegSize = StmImageSize;
+ }
+
+ if (StmHeader->HwStmHdr.Cr3Offset >= StmHeader->SwStmHdr.StaticImageSize) {
+ //
+ // We will create page table, just in case that SINIT does not create it.
+ //
+ if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6)) {
+ MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6);
+ }
+ }
+
+ //
+ // Check if it exceeds MSEG size
+ //
+ if (MinMsegSize > mMsegSize) {
+ DEBUG ((DEBUG_ERROR, "MSEG too small. Min MSEG Size = %08x Current MSEG Size = %08x\n", MinMsegSize, mMsegSize));
+ DEBUG ((DEBUG_ERROR, " StmHeader->SwStmHdr.StaticImageSize = %08x\n", StmHeader->SwStmHdr.StaticImageSize));
+ DEBUG ((DEBUG_ERROR, " StmHeader->SwStmHdr.AdditionalDynamicMemorySize = %08x\n", StmHeader->SwStmHdr.AdditionalDynamicMemorySize));
+ DEBUG ((DEBUG_ERROR, " StmHeader->SwStmHdr.PerProcDynamicMemorySize = %08x\n", StmHeader->SwStmHdr.PerProcDynamicMemorySize));
+ DEBUG ((DEBUG_ERROR, " VMCS Size = %08x\n", GetVmcsSize ()));
+ DEBUG ((DEBUG_ERROR, " Max CPUs = %08x\n", gSmst->NumberOfCpus));
+ DEBUG ((DEBUG_ERROR, " StmHeader->HwStmHdr.Cr3Offset = %08x\n", StmHeader->HwStmHdr.Cr3Offset));
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+**/
+VOID
+StmLoadStmImage (
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
+ )
+{
+ MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
+ UINT32 MsegBase;
+ STM_HEADER *StmHeader;
+
+ //
+ // Get MSEG base address from MSR_IA32_SMM_MONITOR_CTL
+ //
+ SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
+ MsegBase = SmmMonitorCtl.Bits.MsegBase << 12;
+
+ //
+ // Zero all of MSEG base address
+ //
+ ZeroMem ((VOID *)(UINTN)MsegBase, mMsegSize);
+
+ //
+ // Copy STM Image into MSEG
+ //
+ CopyMem ((VOID *)(UINTN)MsegBase, (VOID *)(UINTN)StmImage, StmImageSize);
+
+ //
+ // STM Header is at the beginning of the STM Image
+ //
+ StmHeader = (STM_HEADER *)(UINTN)StmImage;
+
+ StmGen4GPageTable ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset);
+}
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval EFI_SUCCESS Load STM to MSEG successfully
+ @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG
+ @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image
+ @retval EFI_UNSUPPORTED MSEG is not enabled
+
+**/
+EFI_STATUS
+EFIAPI
+LoadMonitor (
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
+ )
+{
+ MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
+
+ if (mLockLoadMonitor) {
+ return EFI_ACCESS_DENIED;
+ }
+
+ SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
+ if (SmmMonitorCtl.Bits.MsegBase == 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (!StmCheckStmImage (StmImage, StmImageSize)) {
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence.
+ TpmMeasureAndLogData(
+ 0, // PcrIndex
+ TXT_EVTYPE_STM_HASH, // EventType
+ NULL, // EventLog
+ 0, // LogLen
+ (VOID *)(UINTN)StmImage, // HashData
+ StmImageSize // HashDataLen
+ );
+
+ StmLoadStmImage (StmImage, StmImageSize);
+
+ mStmState |= EFI_SM_MONITOR_STATE_ENABLED;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function return BIOS STM resource.
+ Produced by SmmStm.
+ Comsumed by SmmMpService when Init.
+
+ @return BIOS STM resource
+
+**/
+VOID *
+GetStmResource(
+ VOID
+ )
+{
+ return mStmResourcesPtr;
+}
+
+/**
+ This function notify STM resource change.
+
+ @param StmResource BIOS STM resource
+
+**/
+VOID
+NotifyStmResourceChange (
+ VOID *StmResource
+ )
+{
+ UINTN Index;
+ TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
+
+ for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
+ Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
+ }
+ return ;
+}
+
+
+/**
+ This is STM setup BIOS callback.
+**/
+VOID
+EFIAPI
+SmmStmSetup (
+ VOID
+ )
+{
+ mStmState |= EFI_SM_MONITOR_STATE_ACTIVATED;
+}
+
+/**
+ This is STM teardown BIOS callback.
+**/
+VOID
+EFIAPI
+SmmStmTeardown (
+ VOID
+ )
+{
+ mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED;
+}
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
new file mode 100644
index 0000000..92a4dc0
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
@@ -0,0 +1,176 @@
+/** @file
+ SMM STM support
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMM_STM_H_
+#define _SMM_STM_H_
+
+#include <Protocol/SmMonitorInit.h>
+
+/**
+
+ Create 4G page table for STM.
+ 2M PAE page table in X64 version.
+
+ @param PageTableBase The page table base in MSEG
+
+**/
+VOID
+StmGen4GPageTable (
+ IN UINTN PageTableBase
+ );
+
+/**
+ This is SMM exception handle.
+ Consumed by STM when exception happen.
+
+ @param Context STM protection exception stack frame
+
+ @return the EBX value for STM reference.
+ EBX = 0: resume SMM guest using register state found on exception stack.
+ EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the
+ TXT.ERRORCODE register and subsequently reset the system via
+ TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as
+ follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
+ EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
+
+**/
+UINT32
+EFIAPI
+SmmStmExceptionHandler (
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ );
+
+
+/**
+
+ Get STM state.
+
+ @return STM state
+
+**/
+EFI_SM_MONITOR_STATE
+EFIAPI
+GetMonitorState (
+ VOID
+ );
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval EFI_SUCCESS Load STM to MSEG successfully
+ @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image
+
+**/
+EFI_STATUS
+EFIAPI
+LoadMonitor (
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
+ );
+
+/**
+
+ Add resources in list to database. Allocate new memory areas as needed.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are added
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+ @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas.
+
+**/
+EFI_STATUS
+EFIAPI
+AddPiResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ );
+
+/**
+
+ Delete resources in list to database.
+
+ @param ResourceList A pointer to resource list to be deleted
+ NULL means delete all resources.
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are deleted
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+
+**/
+EFI_STATUS
+EFIAPI
+DeletePiResource (
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
+ );
+
+/**
+
+ Get BIOS resources.
+
+ @param ResourceList A pointer to resource list to be filled
+ @param ResourceSize On input it means size of resource list input.
+ On output it means size of resource list filled,
+ or the size of resource list to be filled if size of too small.
+
+ @retval EFI_SUCCESS If resources are returned.
+ @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetPiResource (
+ OUT STM_RSC *ResourceList,
+ IN OUT UINT32 *ResourceSize
+ );
+
+/**
+ This functin initialize STM configuration table.
+**/
+VOID
+StmSmmConfigurationTableInit (
+ VOID
+ );
+
+/**
+ This function notify STM resource change.
+
+ @param StmResource BIOS STM resource
+
+**/
+VOID
+NotifyStmResourceChange (
+ IN VOID *StmResource
+ );
+
+/**
+ This function return BIOS STM resource.
+
+ @return BIOS STM resource
+
+**/
+VOID *
+GetStmResource (
+ VOID
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
new file mode 100644
index 0000000..1f9f91c
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
@@ -0,0 +1,282 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# SmiEntry.S
+#
+# Abstract:
+#
+# Code template of the SMI handler for a particular processor
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerTemplate)
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerSize)
+ASM_GLOBAL ASM_PFX(gcStmSmiHandlerOffset)
+ASM_GLOBAL ASM_PFX(gStmSmiCr3)
+ASM_GLOBAL ASM_PFX(gStmSmiStack)
+ASM_GLOBAL ASM_PFX(gStmSmbase)
+ASM_GLOBAL ASM_PFX(gStmXdSupported)
+ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
+
+.equ MSR_IA32_MISC_ENABLE, 0x1A0
+.equ MSR_EFER, 0xc0000080
+.equ MSR_EFER_XD, 0x800
+
+#
+# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+#
+.equ DSC_OFFSET, 0xfb00
+.equ DSC_GDTPTR, 0x48
+.equ DSC_GDTSIZ, 0x50
+.equ DSC_CS, 0x14
+.equ DSC_DS, 0x16
+.equ DSC_SS, 0x18
+.equ DSC_OTHERSEG, 0x1a
+#
+# Constants relating to CPU State Save Area
+#
+.equ SSM_DR6, 0xffd0
+.equ SSM_DR7, 0xffc8
+
+.equ PROTECT_MODE_CS, 0x08
+.equ PROTECT_MODE_DS, 0x20
+.equ LONG_MODE_CS, 0x38
+.equ TSS_SEGMENT, 0x40
+.equ GDT_SIZE, 0x50
+
+ .text
+
+ASM_PFX(gcStmSmiHandlerTemplate):
+
+_StmSmiEntryPoint:
+ #
+ # The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
+ # bit addressing mode. And that coincidence has been used in the following
+ # "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
+ # base address register, it is actually BX that is referenced.
+ #
+ .byte 0xbb # mov bx, imm16
+ .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
+ #
+ # fix GDT descriptor
+ #
+ .byte 0x2e,0xa1 # mov ax, cs:[offset16]
+ .word DSC_OFFSET + DSC_GDTSIZ
+ .byte 0x48 # dec ax
+ .byte 0x2e
+ movl %eax, (%rdi) # mov cs:[bx], ax
+ .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
+ .word DSC_OFFSET + DSC_GDTPTR
+ .byte 0x2e
+ movw %ax, 2(%rdi)
+ .byte 0x66,0x2e
+ lgdt (%rdi)
+ #
+ # Patch ProtectedMode Segment
+ #
+ .byte 0xb8
+ .word PROTECT_MODE_CS
+ .byte 0x2e
+ movl %eax, -2(%rdi)
+ #
+ # Patch ProtectedMode entry
+ #
+ .byte 0x66, 0xbf # mov edi, SMBASE
+ASM_PFX(gStmSmbase): .space 4
+ lea ((ProtectedMode - _StmSmiEntryPoint) + 0x8000)(%edi), %ax
+ .byte 0x2e
+ movw %ax, -6(%rdi)
+ #
+ # Switch into ProtectedMode
+ #
+ movq %cr0, %rbx
+ .byte 0x66
+ andl $0x9ffafff3, %ebx
+ .byte 0x66
+ orl $0x00000023, %ebx
+
+ movq %rbx, %cr0
+ .byte 0x66, 0xea
+ .space 6
+
+_StmGdtDesc: .space 6
+
+ProtectedMode:
+ movw $PROTECT_MODE_DS, %ax
+ movl %eax, %ds
+ movl %eax, %es
+ movl %eax, %fs
+ movl %eax, %gs
+ movl %eax, %ss
+ .byte 0xbc # mov esp, imm32
+ASM_PFX(gStmSmiStack): .space 4
+ jmp ProtFlatMode
+
+ProtFlatMode:
+ .byte 0xb8
+ASM_PFX(gStmSmiCr3): .space 4
+ movq %rax, %cr3
+ movl $0x668,%eax # as cr4.PGE is not set here, refresh cr3
+ movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
+# Load TSS
+ subl $8, %esp # reserve room in stack
+ sgdt (%rsp)
+ movl 2(%rsp), %eax # eax = GDT base
+ addl $8, %esp
+ movb $0x89, %dl
+ movb %dl, (TSS_SEGMENT + 5)(%rax) # clear busy flag
+ movl $TSS_SEGMENT, %eax
+ ltr %ax
+
+# enable NXE if supported
+ .byte 0xb0 # mov al, imm8
+ASM_PFX(gStmXdSupported): .byte 1
+ cmpb $0, %al
+ jz SkipXd
+#
+# Check XD disable bit
+#
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ subl $4, %esp
+ pushq %rdx # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L13
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L13:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+ jmp XdDone
+SkipXd:
+ subl $8, %esp
+XdDone:
+
+ #
+ # Switch to LongMode
+ #
+ pushq $LONG_MODE_CS # push cs hardcore here
+ call Base # push return address for retf later
+Base:
+ addl $(LongMode - Base), (%rsp) # offset for far retf, seg is the 1st arg
+
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orb $1,%ah # enable LME
+ wrmsr
+ movq %cr0, %rbx
+ orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
+ movq %rbx, %cr0
+ retf
+LongMode: # long mode (64-bit code) starts here
+ movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
+ lidt (%rax)
+ lea (DSC_OFFSET)(%rdi), %ebx
+ movw DSC_DS(%rbx), %ax
+ movl %eax,%ds
+ movw DSC_OTHERSEG(%rbx), %ax
+ movl %eax,%es
+ movl %eax,%fs
+ movl %eax,%gs
+ movw DSC_SS(%rbx), %ax
+ movl %eax,%ss
+
+CommonHandler:
+ movq 8(%rsp), %rbx
+ # Save FP registers
+
+ subq $0x200, %rsp
+ .byte 0x48 # FXSAVE64
+ fxsave (%rsp)
+
+ addq $-0x20, %rsp
+
+ movq %rbx, %rcx
+ movabsq $ASM_PFX(CpuSmmDebugEntry), %rax
+ call *%rax
+
+ movq %rbx, %rcx
+ movabsq $ASM_PFX(SmiRendezvous), %rax
+ call *%rax
+
+ movq %rbx, %rcx
+ movabsq $ASM_PFX(CpuSmmDebugExit), %rax
+ call *%rax
+
+ addq $0x20, %rsp
+
+ #
+ # Restore FP registers
+ #
+ .byte 0x48 # FXRSTOR64
+ fxrstor (%rsp)
+
+ addq $0x200, %rsp
+
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz L16
+ popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L16
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+L16:
+ rsm
+
+_StmSmiHandler:
+#
+# Check XD disable bit
+#
+ xorq %r8, %r8
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz StmXdDone
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L14
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L14:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone:
+ pushq %r8
+
+ # below step is needed, because STM does not run above code.
+ # we have to run below code to set IDT/CR0/CR4
+ movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
+ lidt (%rax)
+
+ movq %cr0, %rax
+ orl $0x80010023, %eax
+ movq %rax, %cr0
+ movq %cr4, %rax
+ movl $0x668, %eax # as cr4.PGE is not set here, refresh cr3
+ movq %rax, %cr4 # in PreModifyMtrrs() to flush TLB.
+ # STM init finish
+ jmp CommonHandler
+
+ASM_PFX(gcStmSmiHandlerSize) : .word . - _StmSmiEntryPoint
+ASM_PFX(gcStmSmiHandlerOffset): .word _StmSmiHandler - _StmSmiEntryPoint
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
new file mode 100644
index 0000000..ad51e07
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
@@ -0,0 +1,281 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiEntry.asm
+;
+; Abstract:
+;
+; Code template of the SMI handler for a particular processor
+;
+;-------------------------------------------------------------------------------
+
+;
+; Variables referenced by C code
+;
+EXTERNDEF SmiRendezvous:PROC
+EXTERNDEF CpuSmmDebugEntry:PROC
+EXTERNDEF CpuSmmDebugExit:PROC
+EXTERNDEF gcStmSmiHandlerTemplate:BYTE
+EXTERNDEF gcStmSmiHandlerSize:WORD
+EXTERNDEF gcStmSmiHandlerOffset:WORD
+EXTERNDEF gStmSmiCr3:DWORD
+EXTERNDEF gStmSmiStack:DWORD
+EXTERNDEF gStmSmbase:DWORD
+EXTERNDEF gStmXdSupported:BYTE
+EXTERNDEF gStmSmiHandlerIdtr:FWORD
+
+MSR_IA32_MISC_ENABLE EQU 1A0h
+MSR_EFER EQU 0c0000080h
+MSR_EFER_XD EQU 0800h
+
+;
+; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+;
+DSC_OFFSET EQU 0fb00h
+DSC_GDTPTR EQU 48h
+DSC_GDTSIZ EQU 50h
+DSC_CS EQU 14h
+DSC_DS EQU 16h
+DSC_SS EQU 18h
+DSC_OTHERSEG EQU 1ah
+;
+; Constants relating to CPU State Save Area
+;
+SSM_DR6 EQU 0ffd0h
+SSM_DR7 EQU 0ffc8h
+
+PROTECT_MODE_CS EQU 08h
+PROTECT_MODE_DS EQU 20h
+LONG_MODE_CS EQU 38h
+TSS_SEGMENT EQU 40h
+GDT_SIZE EQU 50h
+
+ .code
+
+gcStmSmiHandlerTemplate LABEL BYTE
+
+_StmSmiEntryPoint:
+ ;
+ ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
+ ; bit addressing mode. And that coincidence has been used in the following
+ ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
+ ; base address register, it is actually BX that is referenced.
+ ;
+ DB 0bbh ; mov bx, imm16
+ DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc offset
+; fix GDT descriptor
+ DB 2eh, 0a1h ; mov ax, cs:[offset16]
+ DW DSC_OFFSET + DSC_GDTSIZ
+ DB 48h ; dec ax
+ DB 2eh
+ mov [rdi], eax ; mov cs:[bx], ax
+ DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
+ DW DSC_OFFSET + DSC_GDTPTR
+ DB 2eh
+ mov [rdi + 2], ax ; mov cs:[bx + 2], eax
+ DB 66h, 2eh
+ lgdt fword ptr [rdi] ; lgdt fword ptr cs:[bx]
+; Patch ProtectedMode Segment
+ DB 0b8h ; mov ax, imm16
+ DW PROTECT_MODE_CS ; set AX for segment directly
+ DB 2eh
+ mov [rdi - 2], eax ; mov cs:[bx - 2], ax
+; Patch ProtectedMode entry
+ DB 66h, 0bfh ; mov edi, SMBASE
+gStmSmbase DD ?
+ lea ax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 8000h]
+ DB 2eh
+ mov [rdi - 6], ax ; mov cs:[bx - 6], eax
+; Switch into @ProtectedMode
+ mov rbx, cr0
+ DB 66h
+ and ebx, 9ffafff3h
+ DB 66h
+ or ebx, 00000023h
+
+ mov cr0, rbx
+ DB 66h, 0eah
+ DD ?
+ DW ?
+
+_StmGdtDesc FWORD ?
+@ProtectedMode:
+ mov ax, PROTECT_MODE_DS
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+ DB 0bch ; mov esp, imm32
+gStmSmiStack DD ?
+ jmp ProtFlatMode
+
+ProtFlatMode:
+ DB 0b8h ; mov eax, offset gStmSmiCr3
+gStmSmiCr3 DD ?
+ mov cr3, rax
+ mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
+; Load TSS
+ sub esp, 8 ; reserve room in stack
+ sgdt fword ptr [rsp]
+ mov eax, [rsp + 2] ; eax = GDT base
+ add esp, 8
+ mov dl, 89h
+ mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
+ mov eax, TSS_SEGMENT
+ ltr ax
+
+; enable NXE if supported
+ DB 0b0h ; mov al, imm8
+gStmXdSupported DB 1
+ cmp al, 0
+ jz @SkipXd
+;
+; Check XD disable bit
+;
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ sub esp, 4
+ push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+ jmp @XdDone
+@SkipXd:
+ sub esp, 8
+@XdDone:
+
+; Switch into @LongMode
+ push LONG_MODE_CS ; push cs hardcore here
+ call Base ; push return address for retf later
+Base:
+ add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
+
+ mov ecx, MSR_EFER
+ rdmsr
+ or ah, 1 ; enable LME
+ wrmsr
+ mov rbx, cr0
+ or ebx, 080010023h ; enable paging + WP + NE + MP + PE
+ mov cr0, rbx
+ retf
+@LongMode: ; long mode (64-bit code) starts here
+ mov rax, offset gStmSmiHandlerIdtr
+ lidt fword ptr [rax]
+ lea ebx, [rdi + DSC_OFFSET]
+ mov ax, [rbx + DSC_DS]
+ mov ds, eax
+ mov ax, [rbx + DSC_OTHERSEG]
+ mov es, eax
+ mov fs, eax
+ mov gs, eax
+ mov ax, [rbx + DSC_SS]
+ mov ss, eax
+
+CommonHandler:
+ mov rbx, [rsp + 0x08] ; rbx <- CpuIndex
+
+ ;
+ ; Save FP registers
+ ;
+ sub rsp, 200h
+ DB 48h ; FXSAVE64
+ fxsave [rsp]
+
+ add rsp, -20h
+
+ mov rcx, rbx
+ mov rax, CpuSmmDebugEntry
+ call rax
+
+ mov rcx, rbx
+ mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
+ call rax
+
+ mov rcx, rbx
+ mov rax, CpuSmmDebugExit
+ call rax
+
+ add rsp, 20h
+
+ ;
+ ; Restore FP registers
+ ;
+ DB 48h ; FXRSTOR64
+ fxrstor [rsp]
+
+ add rsp, 200h
+
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @f
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+@@:
+ rsm
+
+_StmSmiHandler:
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone:
+ push r8
+
+ ; below step is needed, because STM does not run above code.
+ ; we have to run below code to set IDT/CR0/CR4
+ mov rax, offset gStmSmiHandlerIdtr
+ lidt fword ptr [rax]
+
+ mov rax, cr0
+ or eax, 80010023h ; enable paging + WP + NE + MP + PE
+ mov cr0, rax
+ mov rax, cr4
+ mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
+ ; STM init finish
+ jmp CommonHandler
+
+gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint
+gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint
+
+ END
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
new file mode 100644
index 0000000..c801591
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -0,0 +1,263 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiEntry.nasm
+;
+; Abstract:
+;
+; Code template of the SMI handler for a particular processor
+;
+;-------------------------------------------------------------------------------
+
+;
+; Variables referrenced by C code
+;
+
+%define MSR_IA32_MISC_ENABLE 0x1A0
+%define MSR_EFER 0xc0000080
+%define MSR_EFER_XD 0x800
+
+;
+; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+;
+%define DSC_OFFSET 0xfb00
+%define DSC_GDTPTR 0x48
+%define DSC_GDTSIZ 0x50
+%define DSC_CS 0x14
+%define DSC_DS 0x16
+%define DSC_SS 0x18
+%define DSC_OTHERSEG 0x1a
+;
+; Constants relating to CPU State Save Area
+;
+%define SSM_DR6 0xffd0
+%define SSM_DR7 0xffc8
+
+%define PROTECT_MODE_CS 0x8
+%define PROTECT_MODE_DS 0x20
+%define LONG_MODE_CS 0x38
+%define TSS_SEGMENT 0x40
+%define GDT_SIZE 0x50
+
+extern ASM_PFX(SmiRendezvous)
+extern ASM_PFX(gStmSmiHandlerIdtr)
+extern ASM_PFX(CpuSmmDebugEntry)
+extern ASM_PFX(CpuSmmDebugExit)
+
+global ASM_PFX(gStmSmbase)
+global ASM_PFX(gStmXdSupported)
+global ASM_PFX(gStmSmiStack)
+global ASM_PFX(gStmSmiCr3)
+global ASM_PFX(gcStmSmiHandlerTemplate)
+global ASM_PFX(gcStmSmiHandlerSize)
+global ASM_PFX(gcStmSmiHandlerOffset)
+
+ DEFAULT REL
+ SECTION .text
+
+BITS 16
+ASM_PFX(gcStmSmiHandlerTemplate):
+_StmSmiEntryPoint:
+ mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
+ mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+ dec ax
+ mov [cs:bx], ax
+ mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov [cs:bx + 2], eax
+o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
+ mov ax, PROTECT_MODE_CS
+ mov [cs:bx-0x2],ax
+ DB 0x66, 0xbf ; mov edi, SMBASE
+ASM_PFX(gStmSmbase): DD 0
+ lea eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]
+ mov [cs:bx-0x6],eax
+ mov ebx, cr0
+ and ebx, 0x9ffafff3
+ or ebx, 0x23
+ mov cr0, ebx
+ jmp dword 0x0:0x0
+_StmGdtDesc:
+ DW 0
+ DD 0
+
+BITS 32
+@ProtectedMode:
+ mov ax, PROTECT_MODE_DS
+o16 mov ds, ax
+o16 mov es, ax
+o16 mov fs, ax
+o16 mov gs, ax
+o16 mov ss, ax
+ DB 0xbc ; mov esp, imm32
+ASM_PFX(gStmSmiStack): DD 0
+ jmp ProtFlatMode
+
+BITS 64
+ProtFlatMode:
+ DB 0xb8 ; mov eax, offset gStmSmiCr3
+ASM_PFX(gStmSmiCr3): DD 0
+ mov cr3, rax
+ mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
+; Load TSS
+ sub esp, 8 ; reserve room in stack
+ sgdt [rsp]
+ mov eax, [rsp + 2] ; eax = GDT base
+ add esp, 8
+ mov dl, 0x89
+ mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
+ mov eax, TSS_SEGMENT
+ ltr ax
+
+; enable NXE if supported
+ DB 0xb0 ; mov al, imm8
+ASM_PFX(gStmXdSupported): DB 1
+ cmp al, 0
+ jz @SkipXd
+;
+; Check XD disable bit
+;
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ sub esp, 4
+ push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .0
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.0:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+ jmp @XdDone
+@SkipXd:
+ sub esp, 8
+@XdDone:
+
+; Switch into @LongMode
+ push LONG_MODE_CS ; push cs hardcore here
+ call Base ; push return address for retf later
+Base:
+ add dword [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
+
+ mov ecx, MSR_EFER
+ rdmsr
+ or ah, 1 ; enable LME
+ wrmsr
+ mov rbx, cr0
+ or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
+ mov cr0, rbx
+ retf
+@LongMode: ; long mode (64-bit code) starts here
+ mov rax, ASM_PFX(gStmSmiHandlerIdtr)
+ lidt [rax]
+ lea ebx, [rdi + DSC_OFFSET]
+ mov ax, [rbx + DSC_DS]
+ mov ds, eax
+ mov ax, [rbx + DSC_OTHERSEG]
+ mov es, eax
+ mov fs, eax
+ mov gs, eax
+ mov ax, [rbx + DSC_SS]
+ mov ss, eax
+
+CommonHandler:
+ mov rbx, [rsp + 0x08] ; rbx <- CpuIndex
+
+ ;
+ ; Save FP registers
+ ;
+ sub rsp, 0x200
+ DB 0x48 ; FXSAVE64
+ fxsave [rsp]
+
+ add rsp, -0x20
+
+ mov rcx, rbx
+ mov rax, CpuSmmDebugEntry
+ call rax
+
+ mov rcx, rbx
+ mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
+ call rax
+
+ mov rcx, rbx
+ mov rax, CpuSmmDebugExit
+ call rax
+
+ add rsp, 0x20
+
+ ;
+ ; Restore FP registers
+ ;
+ DB 0x48 ; FXRSTOR64
+ fxrstor [rsp]
+
+ add rsp, 0x200
+
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz .1
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.1:
+ rsm
+
+_StmSmiHandler:
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .0
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.0:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone:
+ push r8
+
+ ; below step is needed, because STM does not run above code.
+ ; we have to run below code to set IDT/CR0/CR4
+
+ mov rax, ASM_PFX(gStmSmiHandlerIdtr)
+ lidt [rax]
+
+ mov rax, cr0
+ or eax, 0x80010023 ; enable paging + WP + NE + MP + PE
+ mov cr0, rax
+ mov rax, cr4
+ mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
+ mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
+ ; STM init finish
+ jmp CommonHandler
+
+ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
+ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
new file mode 100644
index 0000000..4d0cd9a
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
@@ -0,0 +1,178 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# SmiException.S
+#
+# Abstract:
+#
+# Exception handlers used in SM mode
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(gcStmPsd)
+
+ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)
+ASM_GLOBAL ASM_PFX(SmmStmSetup)
+ASM_GLOBAL ASM_PFX(SmmStmTeardown)
+
+.equ CODE_SEL, 0x38
+.equ DATA_SEL, 0x20
+.equ TR_SEL, 0x40
+
+.equ MSR_IA32_MISC_ENABLE, 0x1A0
+.equ MSR_EFER, 0x0c0000080
+.equ MSR_EFER_XD, 0x0800
+
+ .data
+
+#
+# This structure serves as a template for all processors.
+#
+ASM_PFX(gcStmPsd):
+ .ascii "TXTPSSIG"
+ .word PSD_SIZE
+ .word 1 # Version
+ .long 0 # LocalApicId
+ .byte 0xF # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ .byte 0 # BIOS to STM
+ .byte 0 # STM to BIOS
+ .byte 0
+ .word CODE_SEL
+ .word DATA_SEL
+ .word DATA_SEL
+ .word DATA_SEL
+ .word TR_SEL
+ .word 0
+ .quad 0 # SmmCr3
+ .quad ASM_PFX(_OnStmSetup)
+ .quad ASM_PFX(_OnStmTeardown)
+ .quad 0 # SmmSmiHandlerRip - SMM guest entrypoint
+ .quad 0 # SmmSmiHandlerRsp
+ .quad 0
+ .long 0
+ .long 0x80010100 # RequiredStmSmmRevId
+ .quad ASM_PFX(_OnException)
+ .quad 0 # ExceptionStack
+ .word DATA_SEL
+ .word 0x1F # ExceptionFilter
+ .long 0
+ .quad 0
+ .quad 0 # BiosHwResourceRequirementsPtr
+ .quad 0 # AcpiRsdp
+ .byte 0 # PhysicalAddressBits
+.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)
+
+ .text
+#------------------------------------------------------------------------------
+# SMM Exception handlers
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(_OnException)
+ASM_PFX(_OnException):
+ movq %rsp, %rcx
+ subq $0x28, %rsp
+ call ASM_PFX(SmmStmExceptionHandler)
+ addq $0x28, %rsp
+ movl %eax, %ebx
+ movl $4, %eax
+ .byte 0xf, 0x1, 0xc1 # VMCALL
+ jmp .
+
+ASM_GLOBAL ASM_PFX(_OnStmSetup)
+ASM_PFX(_OnStmSetup):
+#
+# Check XD disable bit
+#
+ xorq %r8, %r8
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz StmXdDone1
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L13
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L13:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone1:
+ pushq %r8
+
+ subq $0x20, %rsp
+ call ASM_PFX(SmmStmSetup)
+ addq 0x20, %rsp
+
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz L14
+ popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L14
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+L14:
+
+ rsm
+
+ASM_GLOBAL ASM_PFX(_OnStmTeardown)
+ASM_PFX(_OnStmTeardown):
+#
+# Check XD disable bit
+#
+ xorq %r8, %r8
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz StmXdDone2
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
+ jz L15
+ andw $0x0FFFB, %dx # clear XD Disable bit if it is set
+ wrmsr
+L15:
+ movl $MSR_EFER, %ecx
+ rdmsr
+ orw $MSR_EFER_XD,%ax # enable NXE
+ wrmsr
+StmXdDone2:
+ pushq %r8
+
+ subq $0x20, %rsp
+ call ASM_PFX(SmmStmTeardown)
+ addq $0x20, %rsp
+
+ movabsq $ASM_PFX(gStmXdSupported), %rax
+ movb (%rax), %al
+ cmpb $0, %al
+ jz L16
+ popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
+ testl $BIT2, %edx
+ jz L16
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
+ wrmsr
+L16:
+
+ rsm
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
new file mode 100644
index 0000000..33e9860
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
@@ -0,0 +1,178 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiException.asm
+;
+; Abstract:
+;
+; Exception handlers used in SM mode
+;
+;-------------------------------------------------------------------------------
+
+EXTERNDEF gcStmPsd:BYTE
+
+EXTERNDEF SmmStmExceptionHandler:PROC
+EXTERNDEF SmmStmSetup:PROC
+EXTERNDEF SmmStmTeardown:PROC
+EXTERNDEF gStmXdSupported:BYTE
+
+CODE_SEL EQU 38h
+DATA_SEL EQU 20h
+TR_SEL EQU 40h
+
+MSR_IA32_MISC_ENABLE EQU 1A0h
+MSR_EFER EQU 0c0000080h
+MSR_EFER_XD EQU 0800h
+
+ .data
+
+;
+; This structure serves as a template for all processors.
+;
+gcStmPsd LABEL BYTE
+ DB 'TXTPSSIG'
+ DW PSD_SIZE
+ DW 1 ; Version
+ DD 0 ; LocalApicId
+ DB 0Fh ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ DB 0 ; BIOS to STM
+ DB 0 ; STM to BIOS
+ DB 0
+ DW CODE_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW TR_SEL
+ DW 0
+ DQ 0 ; SmmCr3
+ DQ _OnStmSetup
+ DQ _OnStmTeardown
+ DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
+ DQ 0 ; SmmSmiHandlerRsp
+ DQ 0
+ DD 0
+ DD 80010100h ; RequiredStmSmmRevId
+ DQ _OnException
+ DQ 0 ; ExceptionStack
+ DW DATA_SEL
+ DW 01Fh ; ExceptionFilter
+ DD 0
+ DQ 0
+ DQ 0 ; BiosHwResourceRequirementsPtr
+ DQ 0 ; AcpiRsdp
+ DB 0 ; PhysicalAddressBits
+PSD_SIZE = $ - offset gcStmPsd
+
+ .code
+;------------------------------------------------------------------------------
+; SMM Exception handlers
+;------------------------------------------------------------------------------
+_OnException PROC
+ mov rcx, rsp
+ add rsp, -28h
+ call SmmStmExceptionHandler
+ add rsp, 28h
+ mov ebx, eax
+ mov eax, 4
+ DB 0fh, 01h, 0c1h ; VMCALL
+ jmp $
+_OnException ENDP
+
+_OnStmSetup PROC
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone1:
+ push r8
+
+ add rsp, -20h
+ call SmmStmSetup
+ add rsp, 20h
+
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @f
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmSetup ENDP
+
+_OnStmTeardown PROC
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone2
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz @f
+ and dx, 0FFFBh ; clear XD Disable bit if it is set
+ wrmsr
+@@:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone2:
+ push r8
+
+ add rsp, -20h
+ call SmmStmTeardown
+ add rsp, 20h
+
+ mov rax, offset ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @f
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz @f
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+@@:
+
+ rsm
+_OnStmTeardown ENDP
+
+ END
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
new file mode 100644
index 0000000..fe1bf3f
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
@@ -0,0 +1,179 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmiException.nasm
+;
+; Abstract:
+;
+; Exception handlers used in SM mode
+;
+;-------------------------------------------------------------------------------
+
+global ASM_PFX(gcStmPsd)
+
+extern ASM_PFX(SmmStmExceptionHandler)
+extern ASM_PFX(SmmStmSetup)
+extern ASM_PFX(SmmStmTeardown)
+extern ASM_PFX(gStmXdSupported)
+extern ASM_PFX(gStmSmiHandlerIdtr)
+
+%define MSR_IA32_MISC_ENABLE 0x1A0
+%define MSR_EFER 0xc0000080
+%define MSR_EFER_XD 0x800
+
+CODE_SEL equ 0x38
+DATA_SEL equ 0x20
+TR_SEL equ 0x40
+
+ SECTION .data
+
+;
+; This structure serves as a template for all processors.
+;
+ASM_PFX(gcStmPsd):
+ DB 'TXTPSSIG'
+ DW PSD_SIZE
+ DW 1 ; Version
+ DD 0 ; LocalApicId
+ DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
+ DB 0 ; BIOS to STM
+ DB 0 ; STM to BIOS
+ DB 0
+ DW CODE_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW DATA_SEL
+ DW TR_SEL
+ DW 0
+ DQ 0 ; SmmCr3
+ DQ ASM_PFX(OnStmSetup)
+ DQ ASM_PFX(OnStmTeardown)
+ DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
+ DQ 0 ; SmmSmiHandlerRsp
+ DQ 0
+ DD 0
+ DD 0x80010100 ; RequiredStmSmmRevId
+ DQ ASM_PFX(OnException)
+ DQ 0 ; ExceptionStack
+ DW DATA_SEL
+ DW 0x01F ; ExceptionFilter
+ DD 0
+ DQ 0
+ DQ 0 ; BiosHwResourceRequirementsPtr
+ DQ 0 ; AcpiRsdp
+ DB 0 ; PhysicalAddressBits
+PSD_SIZE equ $ - ASM_PFX(gcStmPsd)
+
+ DEFAULT REL
+ SECTION .text
+;------------------------------------------------------------------------------
+; SMM Exception handlers
+;------------------------------------------------------------------------------
+global ASM_PFX(OnException)
+ASM_PFX(OnException):
+ mov rcx, rsp
+ add rsp, -0x28
+ call ASM_PFX(SmmStmExceptionHandler)
+ add rsp, 0x28
+ mov ebx, eax
+ mov eax, 4
+ DB 0x0f, 0x01, 0x0c1 ; VMCALL
+ jmp $
+
+global ASM_PFX(OnStmSetup)
+ASM_PFX(OnStmSetup):
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone1
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .01
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.01:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone1:
+ push r8
+
+ add rsp, -0x20
+ call ASM_PFX(SmmStmSetup)
+ add rsp, 0x20
+
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz .11
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .11
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.11:
+ rsm
+
+global ASM_PFX(OnStmTeardown)
+ASM_PFX(OnStmTeardown):
+;
+; Check XD disable bit
+;
+ xor r8, r8
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz @StmXdDone2
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
+ jz .02
+ and dx, 0xFFFB ; clear XD Disable bit if it is set
+ wrmsr
+.02:
+ mov ecx, MSR_EFER
+ rdmsr
+ or ax, MSR_EFER_XD ; enable NXE
+ wrmsr
+@StmXdDone2:
+ push r8
+
+ add rsp, -0x20
+ call ASM_PFX(SmmStmTeardown)
+ add rsp, 0x20
+
+ mov rax, ASM_PFX(gStmXdSupported)
+ mov al, [rax]
+ cmp al, 0
+ jz .12
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
+ test edx, BIT2
+ jz .12
+ mov ecx, MSR_IA32_MISC_ENABLE
+ rdmsr
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
+ wrmsr
+
+.12:
+ rsm
+
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
new file mode 100644
index 0000000..6681234
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
@@ -0,0 +1,95 @@
+/** @file
+ SMM STM support functions
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiSmm.h>
+#include <Library/DebugLib.h>
+
+#include "SmmStm.h"
+
+///
+/// Page Table Entry
+///
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_PS BIT7
+
+/**
+
+ Create 4G page table for STM.
+ 2M PAE page table in X64 version.
+
+ @param PageTableBase The page table base in MSEG
+
+**/
+VOID
+StmGen4GPageTable (
+ IN UINTN PageTableBase
+ )
+{
+ UINTN Index;
+ UINTN SubIndex;
+ UINT64 *Pde;
+ UINT64 *Pte;
+ UINT64 *Pml4;
+
+ Pml4 = (UINT64*)(UINTN)PageTableBase;
+ PageTableBase += SIZE_4KB;
+ *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
+
+ Pde = (UINT64*)(UINTN)PageTableBase;
+ PageTableBase += SIZE_4KB;
+ Pte = (UINT64 *)(UINTN)PageTableBase;
+
+ for (Index = 0; Index < 4; Index++) {
+ *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;
+ Pde++;
+ PageTableBase += SIZE_4KB;
+
+ for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) {
+ *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
+ Pte++;
+ }
+ }
+}
+
+/**
+ This is SMM exception handle.
+ Consumed by STM when exception happen.
+
+ @param Context STM protection exception stack frame
+
+ @return the EBX value for STM reference.
+ EBX = 0: resume SMM guest using register state found on exception stack.
+ EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the
+ TXT.ERRORCODE register and subsequently reset the system via
+ TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as
+ follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
+ EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
+
+**/
+UINT32
+EFIAPI
+SmmStmExceptionHandler (
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ )
+{
+ // TBD - SmmStmExceptionHandler, record information
+ DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));
+ //
+ // Skip this instruction and continue;
+ //
+ Context.X64StackFrame->Rip += Context.X64StackFrame->VmcsExitInstructionLength;
+
+ return 0;
+}
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 624641f..3922f2d 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -62,6 +62,7 @@
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
MicrocodeFlashAccessLib|UefiCpuPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
[LibraryClasses.common.SEC]
PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
@@ -127,10 +128,17 @@
UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+ UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
UefiCpuPkg/SecCore/SecCore.inf
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
+ <Defines>
+ FILE_GUID = D1D74FE9-7A4E-41D3-A0B3-67F13AD34D94
+ <LibraryClasses>
+ SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
+ }
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf
--
2.7.1.windows.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [patch 0/4] Add STM (Smi Tranfer Monitor) support
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
` (3 preceding siblings ...)
2016-12-16 1:48 ` [patch 4/4] UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance Feng Tian
@ 2016-12-19 1:00 ` Fan, Jeff
2016-12-19 1:24 ` Yao, Jiewen
5 siblings, 0 replies; 7+ messages in thread
From: Fan, Jeff @ 2016-12-19 1:00 UTC (permalink / raw)
To: Tian, Feng, edk2-devel@lists.01.org
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Feng Tian
Sent: Friday, December 16, 2016 9:48 AM
To: edk2-devel@lists.01.org
Subject: [edk2] [patch 0/4] Add STM (Smi Tranfer Monitor) support
This patch series is used to add STM support to UefiCpuPkg.
More details about STM are described in:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf
https://firmware.intel.com/sites/default/files/STM_User_Guide-001.pdf
https://firmware.intel.com/sites/default/files/A_Tour_Beyond_BIOS_Launching_STM_to_Monitor_SMM_in_EFI_Developer_Kit_II.pdf
Michael Kinney (4):
UefiCpuPkg/Include: Update MSEG structure comments
UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs
UefiCpuPkg/SmmCpuFeaturesLib: Split into two files
UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
UefiCpuPkg/Include/Guid/MsegSmram.h | 30 +
UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 141 +++
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 +-
UefiCpuPkg/Include/Register/StmApi.h | 954 ++++++++++++++
.../Include/Register/StmResourceDescriptor.h | 228 ++++
UefiCpuPkg/Include/Register/StmStatusCode.h | 78 ++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 278 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 285 +++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 271 ++++
.../Library/SmmCpuFeaturesLib/Ia32/SmiException.S | 174 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.asm | 170 +++
.../SmmCpuFeaturesLib/Ia32/SmiException.nasm | 176 +++
.../Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c | 83 ++
.../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 77 +-
.../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +-
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c | 89 ++
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 88 ++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1299 ++++++++++++++++++++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 176 +++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 282 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 281 +++++
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 263 ++++
.../Library/SmmCpuFeaturesLib/X64/SmiException.S | 178 +++
.../Library/SmmCpuFeaturesLib/X64/SmiException.asm | 178 +++
.../SmmCpuFeaturesLib/X64/SmiException.nasm | 179 +++
.../Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c | 95 ++
UefiCpuPkg/UefiCpuPkg.dec | 12 +
UefiCpuPkg/UefiCpuPkg.dsc | 8 +
28 files changed, 6036 insertions(+), 65 deletions(-)
create mode 100644 UefiCpuPkg/Include/Guid/MsegSmram.h
create mode 100644 UefiCpuPkg/Include/Protocol/SmMonitorInit.h
create mode 100644 UefiCpuPkg/Include/Register/StmApi.h
create mode 100644 UefiCpuPkg/Include/Register/StmResourceDescriptor.h
create mode 100644 UefiCpuPkg/Include/Register/StmStatusCode.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
--
2.7.1.windows.2
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [patch 0/4] Add STM (Smi Tranfer Monitor) support
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
` (4 preceding siblings ...)
2016-12-19 1:00 ` [patch 0/4] Add STM (Smi Tranfer Monitor) support Fan, Jeff
@ 2016-12-19 1:24 ` Yao, Jiewen
5 siblings, 0 replies; 7+ messages in thread
From: Yao, Jiewen @ 2016-12-19 1:24 UTC (permalink / raw)
To: Tian, Feng, edk2-devel@lists.01.org
Reviewed-by: jiewen.yao@intel.com
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Feng
> Tian
> Sent: Friday, December 16, 2016 9:48 AM
> To: edk2-devel@lists.01.org
> Subject: [edk2] [patch 0/4] Add STM (Smi Tranfer Monitor) support
>
> This patch series is used to add STM support to UefiCpuPkg.
>
> More details about STM are described in:
> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/6
> 4-ia-32-architectures-software-developer-manual-325462.pdf
> https://firmware.intel.com/sites/default/files/STM_User_Guide-001.pdf
> https://firmware.intel.com/sites/default/files/A_Tour_Beyond_BIOS_Launching
> _STM_to_Monitor_SMM_in_EFI_Developer_Kit_II.pdf
>
> Michael Kinney (4):
> UefiCpuPkg/Include: Update MSEG structure comments
> UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs
> UefiCpuPkg/SmmCpuFeaturesLib: Split into two files
> UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
>
> UefiCpuPkg/Include/Guid/MsegSmram.h | 30 +
> UefiCpuPkg/Include/Protocol/SmMonitorInit.h | 141 +++
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 +-
> UefiCpuPkg/Include/Register/StmApi.h | 954
> ++++++++++++++
> .../Include/Register/StmResourceDescriptor.h | 228 ++++
> UefiCpuPkg/Include/Register/StmStatusCode.h | 78 ++
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 278 +++++
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 285 +++++
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 271 ++++
> .../Library/SmmCpuFeaturesLib/Ia32/SmiException.S | 174 +++
> .../SmmCpuFeaturesLib/Ia32/SmiException.asm | 170 +++
> .../SmmCpuFeaturesLib/Ia32/SmiException.nasm | 176 +++
> .../Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c | 83 ++
> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 77 +-
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +-
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c | 89 ++
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 88 ++
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1299
> ++++++++++++++++++++
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 176 +++
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 282 +++++
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 281 +++++
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 263 ++++
> .../Library/SmmCpuFeaturesLib/X64/SmiException.S | 178 +++
> .../Library/SmmCpuFeaturesLib/X64/SmiException.asm | 178 +++
> .../SmmCpuFeaturesLib/X64/SmiException.nasm | 179 +++
> .../Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c | 95 ++
> UefiCpuPkg/UefiCpuPkg.dec | 12 +
> UefiCpuPkg/UefiCpuPkg.dsc | 8 +
> 28 files changed, 6036 insertions(+), 65 deletions(-)
> create mode 100644 UefiCpuPkg/Include/Guid/MsegSmram.h
> create mode 100644 UefiCpuPkg/Include/Protocol/SmMonitorInit.h
> create mode 100644 UefiCpuPkg/Include/Register/StmApi.h
> create mode 100644 UefiCpuPkg/Include/Register/StmResourceDescriptor.h
> create mode 100644 UefiCpuPkg/Include/Register/StmStatusCode.h
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.S
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
> create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
>
> --
> 2.7.1.windows.2
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-12-19 1:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-12-16 1:48 [patch 0/4] Add STM (Smi Tranfer Monitor) support Feng Tian
2016-12-16 1:48 ` [patch 1/4] UefiCpuPkg/Include: Update MSEG structure comments Feng Tian
2016-12-16 1:48 ` [patch 2/4] UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs Feng Tian
2016-12-16 1:48 ` [patch 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Split into two files Feng Tian
2016-12-16 1:48 ` [patch 4/4] UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance Feng Tian
2016-12-19 1:00 ` [patch 0/4] Add STM (Smi Tranfer Monitor) support Fan, Jeff
2016-12-19 1:24 ` Yao, Jiewen
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