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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AM5PR0801MB1778.eurprd08.prod.outlook.com (2603:10a6:203:3b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25; Mon, 10 May 2021 08:43:33 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688%7]) with mapi id 15.20.4108.031; Mon, 10 May 2021 08:43:33 +0000 Subject: Re: [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform To: Pranav Madhu , devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois References: <20210428121229.32674-1-pranav.madhu@arm.com> <20210428121229.32674-3-pranav.madhu@arm.com> From: "Sami Mujawar" Message-ID: <8ef1359e-b8be-76b5-82b6-4feded7bbcd5@arm.com> Date: Mon, 10 May 2021 09:43:32 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 08:43:47.7446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8202e7a-25ee-4541-341b-08d9138fba76 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6959 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-GB Hi Pranav, Please see my response inline marked [SAMI]. Regards, Sami Mujawar On 28/04/2021 01:12 PM, Pranav Madhu wrote: > From: Pranav Madhu > > The SGI-575 platform includes two clusters with four single-thread CPUs. > Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache > and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table > for SGI-575 platform with this information. > > Signed-off-by: Pranav Madhu > --- > Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +- > Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 +++++++++++++= +++++++ > 2 files changed, 163 insertions(+), 1 deletion(-) > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf > index 2121fd39f2f0..b1ee16e98ea3 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf > @@ -1,7 +1,7 @@ > ## @file > # ACPI table data and ASL sources required to boot the platform. > # > -# Copyright (c) 2018, ARM Ltd. All rights reserved. > +# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -22,6 +22,7 @@ > Mcfg.aslc > Sgi575/Dsdt.asl > Sgi575/Madt.aslc > + Sgi575/Pptt.aslc > Spcr.aslc > Ssdt.asl > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc > new file mode 100644 > index 000000000000..3388a012dd55 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc > @@ -0,0 +1,161 @@ > +/** @file > +* Processor Properties Topology Table (PPTT) for SGI-575 platform > +* > +* This file describes the topological structure of the processor block o= n the > +* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-57= 5 > +* platform includes two clusters with four single-thread CPUS. Each of t= he CPUs > +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cac= he. > +* Each cluster includes a 2MB L3 cache. > +* > +* Copyright (c) 2021, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +* @par Specification Reference: > +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table > +**/ > + > +#include > +#include > +#include > +#include > + > +#include "SgiPlatform.h" > +#include "SgiAcpiHeader.h" > + > +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ [SAMI] Can you add a doxygen style header describing the parameters. As it stands the meaning of the macro parameter is not intutive. I can see the difficulty if PPTT_CORE_INIT() were to be a generic macro, in which case it may be better to describe the parameters as affinity levels. However, in the current case this macro is local, so - the macro could be modified to suit parameters specific to this file OR - Describe the macro parameters as affinity levels and add a Doxygen function style comment header clarifying the parameter usage. [/SAMI] > + { = \ > + /* Parameters for CPU Core */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ > + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ > + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid]), /* Parent */ = \ > + ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ = \ > + 2 /* Num of private resource *= / \ > + ), = \ > + = \ > + /* Offsets of the private resources */ = \ > + { = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid].Core[cpuid].DCache), = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid].Core[cpuid].ICache) = \ > + }, = \ > + = \ > + /* L1 data cache parameters */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid].Core[cpuid].L2Cache), = \ > + /* Next level of cache */ = \ > + SIZE_64KB, /* Size */ = \ > + 64, /* Num of sets */ = \ > + 16, /* Associativity */ = \ > + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ > + 64 /* Line size */ = \ > + ), = \ > + = \ > + /* L1 instruction cache parameters */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid].Core[cpuid].L2Cache), = \ > + /* Next level of cache */ = \ > + SIZE_64KB, /* Size */ = \ > + 256, /* Num of sets */ = \ > + 4, /* Associativity */ = \ > + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ > + 64 /* Line size */ = \ > + ), = \ > + = \ > + /* L2 cache parameters */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + 0, /* Next level of cache */ = \ > + SIZE_512KB, /* Size */ = \ > + 1024, /* Num of sets */ = \ > + 8, /* Associativity */ = \ > + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ > + 64 /* Line size */ = \ > + ), = \ > + } > + > +#define PPTT_CLUSTER_INIT(pid, cid) = \ > + { = \ > + /* Parameters for Cluster */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ > + OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), = \ > + /* Length */ = \ > + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package), /* Parent */ = \ > + 0, /* ACPI Id */ = \ > + 1 /* Num of private resource *= / \ > + ), = \ > + = \ > + /* Offsets of the private resources */ = \ > + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[cid].L3Cache), = \ > + = \ > + /* L3 cache parameters */ = \ > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + 0, /* Next level of cache */ = \ > + SIZE_2MB, /* Size */ = \ > + 2048, /* Num of sets */ = \ > + 16, /* Associativity */ = \ > + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ > + 64 /* Line size */ = \ > + ), = \ > + = \ > + /* Initialize child cores */ = \ > + { = \ > + PPTT_CORE_INIT (pid, cid, 0), = \ > + PPTT_CORE_INIT (pid, cid, 1), = \ > + PPTT_CORE_INIT (pid, cid, 2), = \ > + PPTT_CORE_INIT (pid, cid, 3) = \ > + } = \ > + } > + > +#pragma pack(1) > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; > +} SGI575_PPTT_PACKAGE; > + > +/* > + * Processor Properties Topology Table > + */ > +typedef struct { > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > + SGI575_PPTT_PACKAGE Package; > +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > +#pragma pack () > + > +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { > + { > + ARM_ACPI_HEADER ( > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION > + ) > + }, > + > + { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( > + OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0 > + ), > + { > + PPTT_CLUSTER_INIT (0, 0), > + PPTT_CLUSTER_INIT (0, 1) > + } > + } > +}; > + > +/* > + * Reference the table being generated to prevent the optimizer from rem= oving > + * the data structure from the executable > + */ > +VOID* CONST ReferenceAcpiTable =3D &Pptt; IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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