From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3045C2118B661 for ; Wed, 14 Nov 2018 06:56:02 -0800 (PST) Received: by mail-pf1-x444.google.com with SMTP id s9-v6so8019358pfm.13 for ; Wed, 14 Nov 2018 06:56:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5HIPD8t3Q4G5rmAWQEOo4IQlJRci1Wzi/JPgbYCjOGc=; b=i/sWLSSo+uu1ztnz3vy8s7iLdhqb/g7aL+6EGnwt94kpXwaPtG80A/f26I7e8n6jDG LpnKR/hkoXh6w6UTfWbsDfYjMGlwROqpWdgHIUpPhb1X/h3na6WAwmhDCWqvXXWb7DcL hEqNl20lle0U+GiG81LtQ3UeaReawI9S/FfTg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5HIPD8t3Q4G5rmAWQEOo4IQlJRci1Wzi/JPgbYCjOGc=; b=TVSYljScKzm/UOgQNB+uSuuiDIjYw5fUuqVU/KMxuDLUNYMUKDH2QebXkLH2p7pSm8 PmCTk97OLg0wY9YsuayDK6czBPIN4VaH3SO8dkhqAKBWofwW2p3mo4zMpE0PXgJaK1RE tHVwKvCEvF42LPxlr70ii1+IhMcpsncZJcDqzAPaGqv/VW/yZrX9amFQQE68SyyfbL8w bJntXXOMXMjguy7BvLTFroSpBFSe7mLb3tsujwx2QvWnGYGARqokqFR2uh8CUrXdeQBt K9xLV9sE42D1V0jZterqRwfNJoH3hzuZJE8pifXrDX2oGcL8WcD7nxYo3AyGeMFHz+rW UCaw== X-Gm-Message-State: AGRZ1gLM7kmH4JTLVXyEtL21g2j1ZcV4qaaYN5o4hjkhaBcE/qyip8Jt 1WpHLGiqcdksxMb9+iPyWiISeQ== X-Google-Smtp-Source: AJdET5cmnbhF52/wE8G03Qi79FeFyRH28/6KBf3svGU5vpcoc+8KvtCSglzFg2svGzDfo3z+A6J7pQ== X-Received: by 2002:a62:be18:: with SMTP id l24-v6mr2235984pff.51.1542207361774; Wed, 14 Nov 2018 06:56:01 -0800 (PST) Received: from [10.39.0.150] ([64.64.108.117]) by smtp.gmail.com with ESMTPSA id v20-v6sm25226347pfm.114.2018.11.14.06.55.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 06:56:01 -0800 (PST) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com, Prasanth Pulla References: <20181029035111.53262-1-ming.huang@linaro.org> <20181029035111.53262-5-ming.huang@linaro.org> <20181114010543.vdrerefiijuec4y5@bivouac.eciton.net> From: Ming Huang Message-ID: <8ef876f0-1f14-cd2a-0ba3-80e8e3ec72da@linaro.org> Date: Wed, 14 Nov 2018 22:55:49 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20181114010543.vdrerefiijuec4y5@bivouac.eciton.net> Subject: Re: [PATCH edk2-non-osi v1 4/4] Hisilicon/D06: Fix SBSA PE-15 failed issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Nov 2018 14:56:02 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/14/2018 9:05 AM, Leif Lindholm wrote: > +Prasanth > > On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote: >> PE test case 15 flow: >> Primary core(cacheable shareable) and slave cores(non-cacheable) >> access the same memory area for communication. >> For each slave core{ >> 1 Turn on slave core; >> 2 run the payload function; >> 3 Write result in memory to notify primary core and follow >> clean and invalid instruction; > > clean and invalidate > >> 4 Slave core turn off itself; >> } >> The result in DDR may rewrite by cache data. The essence of >> this problem is that primary core and slave core access the >> same area with different cache attribute. >> Configure L3T register to fix this issue; > > Does this change have any performance implications? Feedback by chip engineer, performance may be reduced a bit. > > Prasanth: would PE test 15 not be _expected_ to fail if primary and > secondary cores access the buffers with different cachability > attributes? > >> Build commit informations: >> edk2:53caffc33b6 >> edk2-platforms:d4d7e39886a >> HwPgk:6e91ea20fda > > HwPkg. > > / > Leif > >> TrustedFirmware:5888a78d43c >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes >> 1 file changed, 0 insertions(+), 0 deletions(-) >> >> diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi >> index 8b6d740..b5aa0aa 100644 >> Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ >> -- >> 2.18.0 >>