From: "Lendacky, Thomas" <thomas.lendacky@amd.com>
To: Peter Gonda <pgonda@google.com>, devel@edk2.groups.io
Cc: James Bottomley <jejb@linux.ibm.com>, Min Xu <min.m.xu@intel.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Jordan Justen <jordan.l.justen@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Laszlo Ersek <lersek@redhat.com>,
Erdem Aktas <erdemaktas@google.com>,
Marc Orr <marcorr@google.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH] OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check
Date: Fri, 7 Jan 2022 16:54:16 -0600 [thread overview]
Message-ID: <8ff105d6-0bbe-35cd-22fb-151b6fb076c8@amd.com> (raw)
In-Reply-To: <f4e24379677e4468e65b57e398106b24d39b7d7d.1641574657.git.pgonda@google.com>
On 1/7/22 11:04 AM, Peter Gonda wrote:
> The SEV-ES bit of Fn800-001F[EAX] - Bit 3 is used for a host to
> determine support for running SEV-ES guests. It should not be checked by
> a guest to determine if it is running under SEV-ES. The guest should use
> the SEV_STATUS MSR Bit 1 to determine if SEV-ES is enabled.
Worth mentioning in the commit message that this check wasn't part of the
original SEV-ES support (Fixes: a91b700e385e7484ab7286b3ba7ea2efbd59480e
tag?), so this is really a compatibility thing, and that this makes the
check consistent with the Linux kernel.
Thanks,
Tom
>
> Cc: James Bottomley <jejb@linux.ibm.com>
> Cc: Min Xu <min.m.xu@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Tom Lendacky <thomas.lendacky@amd.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Erdem Aktas <erdemaktas@google.com>
> Cc: Marc Orr <marcorr@google.com>
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Cc: Jim Mattson <jmattson@google.com>
> Signed-off-by: Peter Gonda <pgonda@google.com>
> ---
> OvmfPkg/ResetVector/Ia32/AmdSev.asm | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
> index 1f827da3b9..77692db27e 100644
> --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
> +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
> @@ -265,14 +265,6 @@ CheckSevFeatures:
> ; Set the work area header to indicate that the SEV is enabled
> mov byte[WORK_AREA_GUEST_TYPE], 1
>
> - ; Check for SEV-ES memory encryption feature:
> - ; CPUID Fn8000_001F[EAX] - Bit 3
> - ; CPUID raises a #VC exception if running as an SEV-ES guest
> - mov eax, 0x8000001f
> - cpuid
> - bt eax, 3
> - jnc GetSevEncBit
> -
> ; Check if SEV-ES is enabled
> ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
> mov ecx, SEV_STATUS_MSR
>
next prev parent reply other threads:[~2022-01-07 22:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 17:04 [PATCH] OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check pgonda
2022-01-07 22:54 ` Lendacky, Thomas [this message]
2022-01-10 15:29 ` Peter Gonda
2022-01-10 18:18 ` Lendacky, Thomas
2022-01-13 16:31 ` Peter Gonda
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8ff105d6-0bbe-35cd-22fb-151b6fb076c8@amd.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox