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[83.11.2.232]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9ee0def87bsm749844566b.143.2024.11.12.09.10.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Nov 2024 09:10:58 -0800 (PST) Message-ID: <90513bfa-0888-44fe-8cd0-7b2e7518a41f@linaro.org> Date: Tue, 12 Nov 2024 18:10:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [edk2-devel] [RFC PATCH v2 1/1] hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW To: Jonathan Cameron , Yuquan Wang Cc: devel@edk2.groups.io, ardb+tianocore@kernel.org, quic_llindhol@quicinc.com, peter.maydell@linaro.org, chenbaozi@phytium.com.cn, linux-cxl@vger.kernel.org, asa-dev@op-lists.linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20241105104346.417102-1-wangyuquan1236@phytium.com.cn> <20241105104346.417102-2-wangyuquan1236@phytium.com.cn> <20241107120457.00006024@Huawei.com> From: "Marcin Juszkiewicz via groups.io" Organization: Linaro In-Reply-To: <20241107120457.00006024@Huawei.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 12 Nov 2024 09:11:01 -0800 Resent-From: marcin.juszkiewicz@linaro.org Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Language: pl-PL, en-GB Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b=Zkh+6zwa; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=pass (policy=none) header.from=groups.io W dniu 7.11.2024 o 13:04, Jonathan Cameron pisze: > On Tue, 5 Nov 2024 18:43:46 +0800 > "Yuquan Wang" wrote: > >> This creates a default pxb-cxl (bus_nr=0xc0) bridge with two >> cxl root ports on sbsa-ref. And the memory layout places 64K >> space for the cxl host bridge register regions(CHBCR) in the >> sbsa-ref memmap. >> >> In addition, this support indepentent mmio32(32M) & mmio64(1M) >> space for cxl components. > Those are too small. Might work today but not sustainable. > > I'm a bit surprised it was this simple to move the MMIO Space away > from what is normally done for PXBs. > I think it might work because the GPEX memory windows are effectively > unlimited in size but I'd like some more eyes on this from people > familiar with how all that works and whether there might be some > corner cases that you haven't seen yet. I see the same problem as with multiple PCIe buses (for NUMA systems): pci 0000:c0:00.0: bridge window [io size 0x1000]: can't assign; no space pci 0000:c0:00.0: bridge window [io size 0x1000]: failed to assign pci 0000:c0:01.0: bridge window [io size 0x1000]: can't assign; no space pci 0000:c0:01.0: bridge window [io size 0x1000]: failed to assign I do not know how it looks on real hardware (all my systems have one PCIe bus) but shouldn't each host bridge have own separate resource windows for config space, buses, mmio etc.? Now we squeeze all pcie buses as pcie-pxb devices and this patch adds cxl to the combo. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120777): https://edk2.groups.io/g/devel/message/120777 Mute This Topic: https://groups.io/mt/109403514/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-