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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB3449.namprd12.prod.outlook.com (2603:10b6:5:3b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2921.25; Wed, 22 Apr 2020 17:42:29 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::9ae:cb95:c925:d5bf]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::9ae:cb95:c925:d5bf%4]) with mapi id 15.20.2921.030; Wed, 22 Apr 2020 17:42:29 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v7 14/43] UefiCpuPkg/CpuExceptionHandler: Add support for CPUID NAE events Date: Wed, 22 Apr 2020 12:41:29 -0500 Message-Id: <92127d4ca1e6b9f205dbf094ceed4b434e124b3a.1587577317.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR04CA0060.namprd04.prod.outlook.com (2603:10b6:3:ef::22) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR04CA0060.namprd04.prod.outlook.com (2603:10b6:3:ef::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2937.13 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: BdscADGyWhrMmRzXN2I+tRggWuY3Yj6g7mBQWJQ3kqFm1BKLvXDgDXolOmuAev5Tm5b7gfWz/Bi+zeR/q+SumEnDfdRJ+lfkCJXDIJW29B5Cjzf6AWumtx2y29mNiisOznOX1YGHQP0GTlr5E5++lLolxnZsV7hwE7kzw367XVvpHMUMpLZU6vMYmoBLrMTnTLK9X7M1jQud/1J8P4u+UlIP2oXlP/cdf3ghHrnYxoTZHW/Kyg4zcw2kiBoHnYSR65EvarTJiwhvSbZzHmB0b0/gYKJ8Z7UUvomLMNhHjpwP83Gq6hUUEvcWn4vr3oqwwva26416sh6tFE11VoJQGKZY2/vZ7fWXhxU7vu/E7I4fhnMZeYRtrjyYYIEOkeh46KX5SGP2ERzuXeu63ZNMnDjX9EMyJWYFVrUeqU7Br6zaSXghJe5KpWkex+yapj0sDy0Gtk9Ovm7tMeY4+1XhaNHHcXxfIpvBqwsWouBaM3C+zc+CR+ZGWsgPtKbmT1by0IRVhGrQuI7S5cmTUqHfrgLNHk8Zw876958ALxuR4sX8/qoCsISpcNJeyEOZzg9ArSDF9TwK5mQ3ESX8QYQTiA== X-MS-Exchange-AntiSpam-MessageData: q80cwIG8fvb7sJlOJUrKo0nW8719smO/v4XQDPSwTiXRLH/KCOJe7OeW0t0qxJ/x5YAa8aDSHSx/+N2xWEOHXPUFv+dKYPpALSXKUK8o6DBJ6bhYQ9uHhxHk4zasjEeRyfuF54G+mhsP8T8pmpLi+A== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c649770f-ca51-4463-bd3d-08d7e6e48767 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2020 17:42:29.6718 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: l5RLrF722TYcWfBJaUCX0NV48mI7431hWz998+V/a4MLtfWhql2aSKDoF5eZJienmi961RimRaZDlBBy9w7VxA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3449 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 5fade675ad84..4324de152b82 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -11,6 +11,8 @@ #include #include "AMDSevVcCommon.h" +#define CR4_OSXSAVE (1 << 18) + // // Instruction execution mode definition // @@ -630,6 +632,58 @@ IoioExit ( return 0; } +/** + Handle a CPUID event. + + Use the VMGEXIT instruction to handle a CPUID event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @retval Others New exception value to propagate + +**/ +STATIC +UINT64 +CpuidExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rax = Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx = Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax == 0x0000000d) { + Ghcb->SaveArea.XCr0 = (AsmReadCr4 () & CR4_OSXSAVE) ? AsmXGetBv (0) : 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status = VmgExit (Ghcb, SvmExitCpuid, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rbx = Ghcb->SaveArea.Rbx; + Regs->Rcx = Ghcb->SaveArea.Rcx; + Regs->Rdx = Ghcb->SaveArea.Rdx; + + return 0; +} + /** Common #VC exception handling routine. @@ -660,6 +714,10 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitCpuid: + NaeExit = CpuidExit; + break; + case SvmExitIoioProt: NaeExit = IoioExit; break; -- 2.17.1