On 1/17/23 09:40, Ard Biesheuvel wrote:

On Tue, 17 Jan 2023 at 13:55, Rebecca Cran <rebecca@quicinc.com> wrote:

I was under the impression that this is becoming a more standard format?

If this is not defined in an ARM spec somewhere, we shouldn't add it
to ArmPkg at this point.

From what I've found, the ARM specs such as the Arm Architecture Reference Manual for A-profile architecture don't define the meaning of the affinity fields? That appears to be left up to the individual Arm core TRMs.

For example, the Cortex-X2 TRM says:

Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity
levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2,
Aff1, Aff0} or AArch64-MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the
system as a whole.
0b00000000
Only one thread.

Affinity level 1. See the description of Aff0 for more information.
Value read from the CPUID configuration pins. Identification number for each CPU in an cluster counting from
zero.

Affinity level 2. See the description of Aff0 for more information.
The value will be determined by the CLUSTERIDAFF2 configuration pins.

Affinity level 3. See the description of Aff0 for more information.
The value will be determined by the CLUSTERIDAFF3 configuration pins.

--
Rebecca Cran