From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B599C1A1E57 for ; Tue, 25 Oct 2016 08:33:00 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP; 25 Oct 2016 08:33:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,546,1473145200"; d="scan'208";a="23539704" Received: from gdong1-mobl4.ccr.corp.intel.com ([10.34.84.55]) by orsmga005.jf.intel.com with ESMTP; 25 Oct 2016 08:32:59 -0700 From: gdong1 To: edk2-devel@lists.01.org Cc: jiewen.yao@intel.com, giri.p.mudusuru@intel.com, maurice.ma@intel.com, guo.dong@intel.com Date: Tue, 25 Oct 2016 08:32:36 -0700 Message-Id: <930125c3fa4aa6ccfab08d27d6d7598de01da9fe.1477408715.git.guo.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 MIME-Version: 1.0 Subject: [PATCH v3] IntelFsp2WrapperPkg: Add a PCD to control if signaling PciEnumerationComplete. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Oct 2016 15:33:01 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PciEnumerationComplete might be signaled to FSP in Coreboot. So FSP wrapper driver don't need send it again. Add a PCD to control if a FSP API could be skipped from FspWrapperNotifyDxe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong Reviewed-by: Maurice Ma Reviewed-by: Jiewen Yao Reviewed-by: Giri P Mudusuru --- .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 22 ++++++++++++++-------- .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf | 1 + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 18 ++++++++++++++++++ 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c index 0797f44..d09e20e 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c @@ -26,6 +26,8 @@ #include #include +#define FSP_API_NOTIFY_PHASE_AFTER_PCI_ENUMERATION BIT16 + typedef EFI_STATUS (EFIAPI * ADD_PERFORMANCE_RECORDS)( @@ -237,6 +239,7 @@ FspWrapperNotifyDxeEntryPoint ( EFI_EVENT ReadyToBootEvent; VOID *Registration; EFI_EVENT ProtocolNotifyEvent; + UINT32 FspApiMask; // // Load this driver's image to memory @@ -246,14 +249,17 @@ FspWrapperNotifyDxeEntryPoint ( return EFI_SUCCESS; } - ProtocolNotifyEvent = EfiCreateProtocolNotifyEvent ( - &gEfiPciEnumerationCompleteProtocolGuid, - TPL_CALLBACK, - OnPciEnumerationComplete, - NULL, - &Registration - ); - ASSERT (ProtocolNotifyEvent != NULL); + FspApiMask = PcdGet32 (PcdSkipFspApi); + if ((FspApiMask & FSP_API_NOTIFY_PHASE_AFTER_PCI_ENUMERATION) == 0) { + ProtocolNotifyEvent = EfiCreateProtocolNotifyEvent ( + &gEfiPciEnumerationCompleteProtocolGuid, + TPL_CALLBACK, + OnPciEnumerationComplete, + NULL, + &Registration + ); + ASSERT (ProtocolNotifyEvent != NULL); + } Status = EfiCreateEventReadyToBootEx ( TPL_CALLBACK, diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf index f851f68..54c2cbf 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf @@ -62,6 +62,7 @@ [Pcd] gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi ## CONSUMES [Depex] TRUE diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec index d9d2d80..ea3bc70 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec @@ -75,6 +75,24 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301 + ## This PCD indicates if FSP APIs are skipped from FSP wrapper.

+ # If a bit is set, that means this FSP API is skipped.
+ # If a bit is clear, that means this FSP API is NOT skipped.
+ # NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.
+ # BIT[15:0] is for function:
+ # BIT0 – Skip TempRamInit
+ # BIT1 – Skip MemoryInit
+ # BIT2 – Skip TempRamExit
+ # BIT3 – Skip SiliconInit
+ # BIT4 – Skip NotifyPhase
+ # BIT[32:16] is for sub-function:
+ # BIT16 – Skip NotifyPhase (AfterPciEnumeration)
+ # BIT17 – Skip NotifyPhase (ReadyToBoot)
+ # BIT18 – Skip NotifyPhase (EndOfFirmware)
+ # Any undefined BITs are reserved for future use.
+ # @Prompt Skip FSP API from FSP wrapper. + gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009 + [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001 \ No newline at end of file -- 2.7.0.windows.1