From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=63.147.10.42; helo=atlmailgw2.ami.com; envelope-from=felixp@ami.com; receiver=edk2-devel@lists.01.org Received: from atlmailgw2.ami.com (atlmailgw2.ami.com [63.147.10.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8C7AC223C179D for ; Wed, 28 Feb 2018 06:50:44 -0800 (PST) X-AuditID: ac10606f-88bff700000006b6-47-5a96c333b6ed Received: from atlms2.us.megatrends.com (atlms2.us.megatrends.com [172.16.96.152]) (using TLS with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (Client did not present a certificate) by atlmailgw2.ami.com (Symantec Messaging Gateway) with SMTP id 0B.C9.01718.333C69A5; Wed, 28 Feb 2018 09:56:51 -0500 (EST) Received: from ATLMS1.us.megatrends.com ([fe80::8c55:daf0:ef05:5605]) by atlms2.us.megatrends.com ([fe80::29dc:a91e:ea0c:cdeb%12]) with mapi id 14.03.0361.001; Wed, 28 Feb 2018 09:56:50 -0500 From: Felix Polyudov To: 'Marvin H?user' , "edk2-devel@lists.01.org" CC: "michael.d.kinney@intel.com" , "Manickavasakam Karpagavinayagam" , "liming.gao@intel.com" Thread-Topic: [edk2] [Patch v2] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file Thread-Index: AQHTsA7hu++tXwdYSEq1yhTx4WIY46O4xVFwgAEiwNA= Date: Wed, 28 Feb 2018 14:56:50 +0000 Message-ID: <9333E191E0D52B4999CE63A99BA663A00302BA4AED@atlms1.us.megatrends.com> References: <20180227210640.7536-1-felixp@ami.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.16.99.93] content-transfer-encoding: quoted-printable MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBKsWRmVeSWpSXmKPExsWyRiBhhq7x4WlRBpt+qlnsOXSU2WLFvQ3s Fm//X2W36Oj4x+TA4rF4z0smj+7Z/1g8Nr9+wRzAHNXAaJOYl5dfkliSqpCSWpxsqxRQlFmW mFyppJCZYqtkqKRQkJOYnJqbmldiq5RYUJCal6Jkx6WAAWyAyjLzFFLzkvNTMvPSbZU8g/11 LSxMLXUNlexCMlIVMvPS8otyE0sy8/MUkvPzSoCqU1OAogoJXZwZXXNMC24bV+y+cpGxgfGF RhcjJ4eEgInEvbu7WLoYuTiEBHYxSfy8+48dwjnMKHF1TS87SBWbgKrE8dXNLCC2iEC6xLSZ e1lBipgF1jJKrJp8gxEkISyQKPF2ZhszRFGSRMf81UxdjBxAtpXEg5PGIGEWoDlLb+xlA7F5 BQIljvxZwAyxrJVR4tX3NlaQBKdArMTPp0vAljEKiEl8P7WGCcRmFhCXuPVkPhPE2QISS/ac Z4awRSVePv7HCmErSGx538kOUa8jsWD3JzYIW1ti2cLXzBCLBSVOznzCMoFRdBaSsbOQtMxC 0jILScsCRpZVjEKJJTm5iZk56eVGeom5mXrJ+bmbGCEJI38H48eP5ocYBTgYlXh4Z26ZFiXE mlhWXJl7iFGCg1lJhPf0dqAQb0piZVVqUX58UWlOavEhRidguExkluIGxRcwAcQbGxhIicI4 hiZmJuZG5oaWJubGxkrivAEnT0cKCaQDE1J2ampBahHMECYOTqkGxmUH1vQqcy1uUe71OP5G PrNMVNtv4av39WU628/atOeGSE4K6M1trpk06+TFJdHf9BuMXp27eKJHUd/VtCXjnH3sm/8m SnkfL97+65SUEuL32PT3ldma9aUTnuT3P1o8Sf/M3BqnzNaoCWeVji9WCJo64cDyItsFekvm TxRb/Xt32/7NMXtEHimxFGckGmoxFxUnAgDnmLBXOwMAAA== Subject: Re: [Patch v2] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 14:50:46 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" I think it should be governed by edk2 conventions. As far as I'm aware, currently there are no conventions related to packed da= ta structure decoration. -----Original Message----- From: Marvin H?user [mailto:Marvin.Haeuser@outlook.com] Sent: Tuesday, February 27, 2018 4:36 PM To: edk2-devel@lists.01.org Cc: Felix Polyudov; michael.d.kinney@intel.com; Manickavasakam Karpagavinaya= gam; liming.gao@intel.com Subject: RE: [edk2] [Patch v2] MdePkg/Include/IndustryStandard: Add PCI Expr= ess 4.0 header file Good day, Please consider for compatibility with some toolchains, byte-packed structs= and unions must be decorated with the define 'PACKED'. Thanks, Marvin. > -----Original Message----- > From: edk2-devel On Behalf Of Felix > Polyudov > Sent: Tuesday, February 27, 2018 10:07 PM > To: edk2-devel@lists.01.org > Cc: michael.d.kinney@intel.com; manickavasakamk@ami.com; > liming.gao@intel.com > Subject: [edk2] [Patch v2] MdePkg/Include/IndustryStandard: Add PCI > Express 4.0 header file > > v2: The structure is updated to include all the fields defined in the PCI-= E > specification. > > The header includes Physical Layer PCI Express Extended Capability > definitions described in section 7.7.5 of PCI Express Base Specification r= ev. > 4.0. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Felix Polyudov > --- > MdePkg/Include/IndustryStandard/PciExpress40.h | 89 > ++++++++++++++++++++++++++ > 1 file changed, 89 insertions(+) > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress40.h > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h > b/MdePkg/Include/IndustryStandard/PciExpress40.h > new file mode 100644 > index 0000000..a832259 > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h > @@ -0,0 +1,89 @@ > +/** @file > +Support for the PCI Express 4.0 standard. > + > +This header file may not define all structures. Please extend as require= d. > + > +Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
> +This program and the accompanying materials are licensed and made > +available under the terms and conditions of the BSD License which > +accompanies this distribution. The full text of the license may be > +found at http://opensource.org/licenses/bsd-license.php > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _PCIEXPRESS40_H_ > +#define _PCIEXPRESS40_H_ > + > +#include > + > +#pragma pack(1) > + > +/// The Physical Layer PCI Express Extended Capability definitions. > +/// > +/// Based on section 7.7.5 of PCI Express Base Specification 4.0. > +///@{ > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID > 0x0026 > +#define > PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1 > + > +// Register offsets from Physical Layer PCI-E Ext Cap Header > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET > 0x04 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET > 0x08 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET > 0x0C > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_ > OFFSET 0x10 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_ > STATUS_OFFSET 0x14 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARIT > Y_STATUS_OFFSET 0x18 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > _OFFSET 0x20 > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES; > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL; > + > +typedef union { > + struct { > + UINT32 EqualizationComplete : 1; // bit 0 > + UINT32 EqualizationPhase1Success : 1; // bit 1 > + UINT32 EqualizationPhase2Success : 1; // bit 2 > + UINT32 EqualizationPhase3Success : 1; // bit 3 > + UINT32 LinkEqualizationRequest : 1; // bit 4 > + UINT32 Reserved : 27; // Reserved bit 5:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS; > + > +typedef union { > + struct { > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > + } Bits; > + UINT8 Uint8; > +} > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > ; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES > Capablities; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status; > + UINT32 LocalData= ParityMismatchStatus; > + UINT32 FirstReti= merDataParityMismatchStatus; > + UINT32 > SecondRetimerDataParityMismatchStatus; > + UINT32 Reserved; > + > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > +LaneEqualizationControl; } > +PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; > +///@} > + > +#pragma pack() > + > +#endif > -- > 2.10.0.windows.1 > > > > Please consider the environment before printing this email. > > The information contained in this message may be confidential and > proprietary to American Megatrends, Inc. This communication is intended t= o > be read only by the individual or entity to whom it is addressed or by the= ir > designee. If the reader of this message is not the intended recipient, you= are > on notice that any distribution of this message, in any form, is strictly > prohibited. Please promptly notify the sender by reply e-mail or by > telephone at 770-246-8600, and then delete or destroy all copies of the > transmission. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel Please consider the environment before printing this email. The information contained in this message may be confidential and proprietar= y to American Megatrends, Inc. This communication is intended to be read on= ly by the individual or entity to whom it is addressed or by their designee.= If the reader of this message is not the intended recipient, you are on not= ice that any distribution of this message, in any form, is strictly prohibit= ed. Please promptly notify the sender by reply e-mail or by telephone at 77= 0-246-8600, and then delete or destroy all copies of the transmission.