From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from atlmailgw2.ami.com (atlmailgw2.ami.com [63.147.10.42]) by mx.groups.io with SMTP id smtpd.web10.11256.1581109097326270622 for ; Fri, 07 Feb 2020 12:58:17 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: ami.com, ip: 63.147.10.42, mailfrom: felixp@ami.com) X-AuditID: ac10606f-807ff70000000872-41-5e3dcf6b15d9 Received: from atlms2.us.megatrends.com (atlms2.us.megatrends.com [172.16.96.152]) (using TLS with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (Client did not present a certificate) by atlmailgw2.ami.com (Symantec Messaging Gateway) with SMTP id 92.A4.02162.B6FCD3E5; Fri, 7 Feb 2020 15:58:19 -0500 (EST) Received: from ATLMS1.us.megatrends.com ([fe80::8c55:daf0:ef05:5605]) by atlms2.us.megatrends.com ([fe80::29dc:a91e:ea0c:cdeb%12]) with mapi id 14.03.0468.000; Fri, 7 Feb 2020 15:57:35 -0500 From: "Felix Polyudov" To: "'Gao, Liming'" , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "Manickavasakam Karpagavinayagam" Subject: Re: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Topic: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Index: AQHV26JeasSAuP4Z6Eiyq9BnKLVYHKgPMgfwgAEI4qA= Date: Fri, 7 Feb 2020 20:57:34 +0000 Message-ID: <9333E191E0D52B4999CE63A99BA663A003FFBE5F12@atlms1.us.megatrends.com> References: <20200204213012.67268-1-felixp@ami.com> <066f801dfccd49e5942241c51496d482@intel.com> In-Reply-To: <066f801dfccd49e5942241c51496d482@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.16.99.93] MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnleLIzCtJLcpLzFFi42JZI5AwQzf7vG2cQcNEMYv2CbPZLFbc28Bu 0dHxj8mB2WP79wuMHov3vGQKYIpqYLRJzMvLL0ksSVVISS1OtlUKKMosS0yuVFLITLFVMlRS KMhJTE7NTc0rsVVKLChIzUtRsuNSwAA2QGWZeQqpecn5KZl56bZKnsH+uhYWppa6hkp2IRmp Cpl5aflFuYklmfl5Csn5eSVA1akpQFGFhG7OjI57F5gLfjtWrDjTyN7A2GjYxcjJISFgItH2 7ipTFyMXh5DALiaJv2+eskA4hxglnjzZwQRSxSagKnF8dTMLiC0iEC2xqncNYxcjBwezQLFE 60JFkLCwgI3Emxl/mCFKbCVurr/GBGFbSTz5vpIVxGYRUJG4Ofk4O4jNKxAosW/tC0YQW0gg SeLfk61gNZwClhLv/mwHizMKiEl8P7UGbA6zgLjErSfzmSCOFpBYsuc8M4QtKvHy8T9WCFtB Ysv7TnaIeh2JBbs/sUHY2hLLFr5mhtgrKHFy5hOWCYyis5CMnYWkZRaSlllIWhYwsqxiFEos yclNzMxJLzfSS8zN1EvOz93ECEkN+TsYP340P8TIxMEIDDsOZiUR3j5V2zgh3pTEyqrUovz4 otKc1OJDjE7AgJjILMUNiiBgjMcbGxhIicI4hiZmJuZG5oaWJubGxkrivKvWfIsREkgHppzs 1NSC1CKYIUwcnFINjMerWH4ybKo5bJJ/doYl69/MizXKvS987itw1N0K9lRrTTlbnj4hornR 2Ov24UX7r93m9Jk4e7eQz/frL65oK34XvXKi1kB5I9NDZqCDL2fIdG+Z2SLbc+TXHIX4z9xH Z/kFrn05V/f/vhjGGe+t97448+LpzT8XV3Nt+Hwn1YS5cuLHe7nLBZRYijMSDbWYi4oTAQP9 htEiAwAA Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Yes, we did build tests on Windows/VS and Linux/GCC. -----Original Message----- From: Gao, Liming [mailto:liming.gao@intel.com] Sent: Friday, February 07, 2020 12:10 AM To: Felix Polyudov; devel@edk2.groups.io Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File Felix: The patch is good. Is any test for the header file, such as build? Thanks Liming > -----Original Message----- > From: Felix Polyudov > Sent: Wednesday, February 5, 2020 5:30 AM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming ; manickavasakamk@ami.com > Subject: [PATCH] MdePkg: Add PCI Express 5.0 Header File > > The header includes Physical Layer PCI Express Extended Capability > definitions based on section 7.7.6 of PCI Express Base Specification 5.0. > > Signed-off-by: Felix Polyudov > --- > MdePkg/Include/IndustryStandard/PciExpress50.h | 136 ++++++++++++++++++++= +++++ > 1 file changed, 136 insertions(+) > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Inclu= de/IndustryStandard/PciExpress50.h > new file mode 100644 > index 0000000..26eae0b > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/PciExpress50.h > @@ -0,0 +1,136 @@ > +/** @file > +Support for the PCI Express 5.0 standard. > + > +This header file may not define all structures. Please extend as require= d. > + > +Copyright (c) 2020, American Megatrends International LLC. All rights res= erved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PCIEXPRESS50_H_ > +#define _PCIEXPRESS50_H_ > + > +#include > + > +#pragma pack(1) > + > +/// The Physical Layer PCI Express Extended Capability definitions. > +/// > +/// Based on section 7.7.6 of PCI Express Base Specification 5.0. > +///@{ > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1 > + > +// Register offsets from Physical Layer PCI-E Ext Cap Header > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET = 0x04 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET = 0x08 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET = 0x0C > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET= 0x10 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET= 0x14 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSE= T 0x18 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSE= T 0x1C > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFF= SET 0x20 > + > +typedef union { > + struct { > + UINT32 EqualizationByPassToHighestRateSupport : 1; /= / bit 0 > + UINT32 NoEqualizationNeededSupport : 1; /= / bit 1 > + UINT32 Reserved1 : 6; /= / Reserved bit 2:7 > + UINT32 ModifiedTSUsageMode0Support : 1; /= / bit 8 > + UINT32 ModifiedTSUsageMode1Support : 1; /= / bit 9 > + UINT32 ModifiedTSUsageMode2Support : 1; /= / bit 10 > + UINT32 ModifiedTSReservedUsageModes : 5; /= / bit 11:15 > + UINT32 Reserved2 : 16;= // Reserved bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES; > + > +typedef union { > + struct { > + UINT32 EqualizationByPassToHighestRateDisable : 1; /= / bit 0 > + UINT32 NoEqualizationNeededDisable : 1; /= / bit 1 > + UINT32 Reserved1 : 6; /= / Reserved bit 2:7 > + UINT32 ModifiedTSUsageModeSelected : 3; /= / bit 8:10 > + UINT32 Reserved2 : 21;= // Reserved bit 11:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL; > + > +typedef union { > + struct { > + UINT32 EqualizationComplete : 1; // bit 0 > + UINT32 EqualizationPhase1Success : 1; // bit 1 > + UINT32 EqualizationPhase2Success : 1; // bit 2 > + UINT32 EqualizationPhase3Success : 1; // bit 3 > + UINT32 LinkEqualizationRequest : 1; // bit 4 > + UINT32 ModifiedTSRcvd : 1; // bit 5 > + UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7 > + UINT32 TransmitterPrecodingOn : 1; // bit 8 > + UINT32 TransmitterPrecodeRequest : 1; // bit 9 > + UINT32 NoEqualizationNeededRcvd : 1; // bit 10 > + UINT32 Reserved : 21; // Reserved bit 11:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS; > + > +typedef union { > + struct { > + UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2 > + UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15 > + UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1; > + > +typedef union { > + struct { > + UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23 > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > + UINT32 Reserved : 6; // Reserved bit 26:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2; > + > +typedef union { > + struct { > + UINT32 TransModifiedTSUsageMode : 3; // bit 0:2 > + UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15 > + UINT32 TransModifiedTSVendorId : 16; // bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1; > + > +typedef union { > + struct { > + UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23 > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > + UINT32 Reserved : 6; // Reserved bit 26:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2; > + > +typedef union { > + struct { > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > + } Bits; > + UINT8 Uint8; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capabliti= es; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModif= iedTs1Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModif= iedTs2Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModi= fiedTs1Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModi= fiedTs2Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqual= izationControl[1]; > +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0; > +///@} > + > +#pragma pack() > + > +#endif > -- > 2.10.0.windows.1 > > > Please consider the environment before printing this email. > > The information contained in this message may be confidential and propriet= ary to American Megatrends (AMI). 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