* [PATCH edk2-platforms 1/3] WIP: SbsaQemu: make PCIe variables dynamic (part 1)
2023-06-13 19:28 [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
@ 2023-06-13 19:28 ` Marcin Juszkiewicz
2023-06-13 19:28 ` [PATCH edk2-platforms 2/3] WIP: SbsaQemu: make PCIe variables dynamic (part 2) Marcin Juszkiewicz
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Marcin Juszkiewicz @ 2023-06-13 19:28 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Graeme Gregory, Marcin Juszkiewicz
DSDT and PciHostBridge gets hardcoded values directly instead of using
FixedPcd* functions.
---
.../SbsaQemuPciHostBridgeLib.c | 16 ++++----
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 38 +++++++++----------
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
index 9739c7500def..08e9b23c5b33 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
@@ -83,31 +83,31 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = {
{
/* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the
* root bridge. */
- FixedPcdGet32 (PcdPciBusMin),
- FixedPcdGet32 (PcdPciBusMax)
+ 0, //PcdGet32 (PcdPciBusMin),
+ 255 //PcdGet32 (PcdPciBusMax)
},
/* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root
bridge */
{
- FixedPcdGet64 (PcdPciIoBase),
- FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ 0, //PcdGet64 (PcdPciIoBase),
+ 0XFFFF //PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1
},
/* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by
the root bridge
(gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */
{
- FixedPcdGet32 (PcdPciMmio32Base),
- FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1,
+ 0x80000000, //PcdGet32 (PcdPciMmio32Base),
+ 0xEFFFFFFF //PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1,
},
/* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be
used by the root bridge.
(gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */
{
- FixedPcdGet64 (PcdPciMmio64Base),
- FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ 0x0100000000, //PcdGet64 (PcdPciMmio64Base),
+ 0xFFFFFFFFFF //PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1
},
/* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index e50772fcf76d..7193c87cdcf2 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -198,7 +198,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
}
Method (_CBA, 0, NotSerialized) {
- return (FixedPcdGet32 (PcdPciExpressBaseAddress))
+ return (0xF0000000) // return (PcdGet32 (PcdPciExpressBaseAddress))
}
LINK_DEVICE(0, GSI0, 0x23)
@@ -376,8 +376,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
ResourceProducer,
MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
- FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
- FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // PcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
+ 255, // PcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
256 // RangeLength - Number of Busses
)
@@ -387,10 +387,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
- FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address
- FixedPcdGet32 (PcdPciMmio32Limit), // Max Base Address
- FixedPcdGet32 (PcdPciMmio32Translation), // Translate
- FixedPcdGet32 (PcdPciMmio32Size) // Length
+ 0x80000000, // PcdGet32 (PcdPciMmio32Base), // Min Base Address
+ 0xEFFFFFFF, // PcdGet32 (PcdPciMmio32Limit), // Max Base Address
+ 0, // PcdGet32 (PcdPciMmio32Translation), // Translate
+ 0x70000000, // PcdGet32 (PcdPciMmio32Size) // Length
)
QWordMemory ( // 64-bit BAR Windows
@@ -398,10 +398,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
- FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address
- FixedPcdGet64 (PcdPciMmio64Limit), // Max Base Address
- FixedPcdGet64 (PcdPciMmio64Translation), // Translate
- FixedPcdGet64 (PcdPciMmio64Size) // Length
+ 0x100000000, // PcdGet64 (PcdPciMmio64Base), // Min Base Address
+ 0xFFFFFFFFFF, // PcdGet64 (PcdPciMmio64Limit), // Max Base Address
+ 0, // PcdGet64 (PcdPciMmio64Translation), // Translate
+ 0xFF00000000, // PcdGet64 (PcdPciMmio64Size) // Length
)
DWordIo ( // IO window
@@ -411,10 +411,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
PosDecode,
EntireRange,
0x00000000, // Granularity
- FixedPcdGet32 (PcdPciIoBase), // Min Base Address
- FixedPcdGet32 (PcdPciIoLimit), // Max Base Address
- FixedPcdGet32 (PcdPciIoTranslation), // Translate
- FixedPcdGet32 (PcdPciIoSize), // Length
+ 0, // PcdGet32 (PcdPciIoBase), // Min Base Address
+ 0x0000ffff, // PcdGet32 (PcdPciIoLimit), // Max Base Address
+ 0x7fff0000, // PcdGet32 (PcdPciIoTranslation), // Translate
+ 0x00010000, // PcdGet32 (PcdPciIoSize), // Length
,,,TypeTranslation
)
}) // Name(RBUF)
@@ -429,10 +429,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- FixedPcdGet64 (PcdPciExpressBaseAddress), // Range Minimum
- FixedPcdGet64 (PcdPciExpressBarLimit), // Range Maximum
- 0x0000000000000000, // Translation Offset
- FixedPcdGet64 (PcdPciExpressBarSize), // Length
+ 0xf0000000, // PcdGet64 (PcdPciExpressBaseAddress), // Range Minimum
+ 0xFFFFFFFF, // PcdGet64 (PcdPciExpressBarLimit), // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x10000000, // PcdGet64 (PcdPciExpressBarSize), // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_STA) {
--
2.40.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms 2/3] WIP: SbsaQemu: make PCIe variables dynamic (part 2)
2023-06-13 19:28 [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
2023-06-13 19:28 ` [PATCH edk2-platforms 1/3] WIP: SbsaQemu: make PCIe variables dynamic (part 1) Marcin Juszkiewicz
@ 2023-06-13 19:28 ` Marcin Juszkiewicz
2023-06-13 19:29 ` [PATCH edk2-platforms 3/3] WIP: SbsaQemu: make PCIe variables dynamic (part 3) Marcin Juszkiewicz
2023-06-21 12:15 ` [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
3 siblings, 0 replies; 5+ messages in thread
From: Marcin Juszkiewicz @ 2023-06-13 19:28 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Graeme Gregory, Marcin Juszkiewicz
Create MCFG table directly from C code instead of ASLC as we cannot use
FixedPcd* for PCIe data.
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 9 +++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 74 +++++++++++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 -----------
4 files changed, 83 insertions(+), 44 deletions(-)
delete mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 0501c670d565..5607878c2040 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -20,7 +20,6 @@ [Sources]
Dsdt.asl
Fadt.aslc
Gtdt.aslc
- Mcfg.aslc
Spcr.aslc
[Packages]
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index c1c33788567d..aad4c8086c40 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -43,11 +43,20 @@ [LibraryClasses]
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
[Depex]
gEfiAcpiTableProtocolGuid ## CONSUMES
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index ae5397bab768..af95f7e14672 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -8,6 +8,7 @@
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/AcpiAml.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <Library/AcpiLib.h>
#include <Library/BaseMemoryLib.h>
@@ -306,6 +307,74 @@ AddSsdtTable (
return Status;
}
+/*
+ * A function that adds the MCFG ACPI table.
+ */
+EFI_STATUS
+AddMcfgTable (
+ IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN TableHandle;
+ UINT32 TableSize;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+
+ EFI_ACPI_DESCRIPTION_HEADER Header =
+ SBSAQEMU_ACPI_HEADER (
+ EFI_ACPI_6_5_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION);
+
+ TableSize = sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+ sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiACPIReclaimMemory,
+ EFI_SIZE_TO_PAGES (TableSize),
+ &PageAddress
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MCFG table\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ New = (UINT8 *)(UINTN) PageAddress;
+ ZeroMem (New, TableSize);
+
+ Header.Length = TableSize;
+
+ // Add the ACPI Description table header
+ CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+ New += sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER);
+
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *CfgPtr;
+
+ CfgPtr = (VOID *)New;
+
+ CfgPtr->BaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
+ CfgPtr->StartBusNumber = PcdGet32 (PcdPciBusMin);
+ CfgPtr->EndBusNumber = PcdGet32 (PcdPciBusMax);
+ CfgPtr->PciSegmentGroupNumber = 0;
+
+ // Perform Checksum
+ AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ (EFI_ACPI_COMMON_HEADER *)PageAddress,
+ TableSize,
+ &TableHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to install MCFG table\n"));
+ }
+
+ return Status;
+}
+
/*
* A function that adds the SSDT ACPI table.
*/
@@ -443,6 +512,11 @@ InitializeSbsaQemuAcpiDxe (
DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n"));
}
+ Status = AddMcfgTable (AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to add MCFG table\n"));
+ }
+
Status = AddSsdtTable (AcpiTable);
if (EFI_ERROR(Status)) {
DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n"));
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
deleted file mode 100644
index 289f4ad4ea3a..000000000000
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @file
-* ACPI Memory mapped configuration space base address Description Table (MCFG).
-*
-* Copyright (c) 2020, Linaro Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
-#include <IndustryStandard/SbsaQemuAcpi.h>
-
-#pragma pack(push, 1)
-
-typedef struct {
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
- EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[1];
-} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
-
-EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
- {
- SBSAQEMU_ACPI_HEADER (
- EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
- EFI_ACPI_RESERVED_QWORD
- },
- {
- {
- FixedPcdGet32 (PcdPciExpressBaseAddress),
- 0,
- FixedPcdGet32 (PcdPciBusMin),
- FixedPcdGet32 (PcdPciBusMax),
- EFI_ACPI_RESERVED_DWORD
- }
- }
-};
-
-#pragma pack(pop)
-
-// Reference the table being generated to prevent the optimizer
-// from removing the data structure from the executable
-VOID* CONST ReferenceAcpiTable = &Mcfg;
--
2.40.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms 3/3] WIP: SbsaQemu: make PCIe variables dynamic (part 3)
2023-06-13 19:28 [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
2023-06-13 19:28 ` [PATCH edk2-platforms 1/3] WIP: SbsaQemu: make PCIe variables dynamic (part 1) Marcin Juszkiewicz
2023-06-13 19:28 ` [PATCH edk2-platforms 2/3] WIP: SbsaQemu: make PCIe variables dynamic (part 2) Marcin Juszkiewicz
@ 2023-06-13 19:29 ` Marcin Juszkiewicz
2023-06-21 12:15 ` [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
3 siblings, 0 replies; 5+ messages in thread
From: Marcin Juszkiewicz @ 2023-06-13 19:29 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Graeme Gregory, Marcin Juszkiewicz
Make those PCIe variables dynamic. But this breaks things:
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 100FB866190
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 100FB866178
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 100FB866160
[Bds] Entry...
[BdsDxe] Locate Variable Policy protocol - Success
Variable Driver Auto Update PlatformLang, PlatformLang:en, Lang:eng Status: Success
[Variable]END_OF_DXE is signaled
Initialize variable error flag (FF)
PCI Bus First Scanning
PciBus: Discovered PCI @ [00|00|00] [VID = 0x1B36, DID = 0x8]
FATAL ERROR - RaiseTpl with OldTpl(0x1F) > NewTpl(0x10)
ASSERT [DxeCore] /home/marcin/devel/linaro/sbsa-qemu/code/edk2/MdeModulePkg/Core/Dxe/Event/Tpl.c(66): ((BOOLEAN)(0==1))
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 +-
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 53 ++++++++++---------
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 22 ++++----
.../SbsaQemuPciHostBridgeLib.inf | 2 +-
4 files changed, 40 insertions(+), 39 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 9448852967b6..3fdf23b77a08 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -36,6 +36,7 @@ [PcdsFixedAtBuild.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005
+[PcdsDynamic.common]
# PCDs complementing PCIe layout pulled into ACPI tables
# Limit = Base + Size - 1
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0x00000006
@@ -47,7 +48,6 @@ [PcdsFixedAtBuild.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010
-[PcdsDynamic.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000101
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 0bd0df4f0239..3cc0f2a270ba 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -459,32 +459,6 @@ [PcdsFixedAtBuild.common]
# point only, for entry point versions >= 3.0.
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
- #
- # PLDA PCI Root Complex
- #
- # ECAM size == 0x10000000
- gArmTokenSpaceGuid.PcdPciBusMin|0
- gArmTokenSpaceGuid.PcdPciBusMax|255
- gArmTokenSpaceGuid.PcdPciIoBase|0x0
- gArmTokenSpaceGuid.PcdPciIoSize|0x00010000
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff
- gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000
- gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF
- gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
- gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF
-
- # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this
- # PCD and PcdPciDisableBusEnumeration have not been assigned yet
- # TODO: PcdPciExpressBaseAddress set to max_uint64
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF
-
- gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000
- gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0
- gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation|0x0
## If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI
# enumeration to complete before installing ACPI tables.
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
@@ -523,6 +497,33 @@ [PcdsDynamicDefault.common]
gArmTokenSpaceGuid.PcdGicDistributorBase|0x40060000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x40080000
+ #
+ # PLDA PCI Root Complex
+ #
+ # ECAM size == 0x10000000
+ gArmTokenSpaceGuid.PcdPciBusMin|0
+ gArmTokenSpaceGuid.PcdPciBusMax|255
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0
+ gArmTokenSpaceGuid.PcdPciIoSize|0x00010000
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF
+
+ # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this
+ # PCD and PcdPciDisableBusEnumeration have not been assigned yet
+ # TODO: PcdPciExpressBaseAddress set to max_uint64
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000
+ gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
#
# Set video resolution for boot options
# PlatformDxe can set the former at runtime.
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 5607878c2040..a8300fd355fd 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -42,6 +42,17 @@ [FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
@@ -63,14 +74,3 @@ [FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize
-
-[Pcd]
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicRedistributorsBase
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
index 9d6791ff7dc2..6bc78ac108f0 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf
@@ -33,7 +33,7 @@ [Packages]
[LibraryClasses]
DebugLib
-[FixedPcd]
+[Pcd]
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
gArmTokenSpaceGuid.PcdPciIoBase
--
2.40.1
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