From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: ashraf.javeed@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Thu, 25 Jul 2019 08:29:46 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 08:29:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,307,1559545200"; d="scan'208";a="193842492" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga004.fm.intel.com with ESMTP; 25 Jul 2019 08:29:46 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 08:29:46 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 25 Jul 2019 08:29:43 -0700 Received: from bgsmsx152.gar.corp.intel.com (10.224.48.50) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 25 Jul 2019 08:29:43 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.176]) by BGSMSX152.gar.corp.intel.com ([169.254.6.179]) with mapi id 14.03.0439.000; Thu, 25 Jul 2019 20:59:41 +0530 From: "Javeed, Ashraf" To: "Gao, Liming" , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "Ni, Ray" , "Wu, Hao A" Subject: Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Topic: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Index: AQHVQFZ3lxBHivQTJkmq0JjMFqXL76bbXjEQgAAJudCAAAM9gIAADnrQ Date: Thu, 25 Jul 2019 15:29:40 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824578BEA6E@BGSMSX101.gar.corp.intel.com> References: <20190722062627.12276-1-ashraf.javeed@intel.com> <4A89E2EF3DFEDB4C8BFDE51014F606A14E4BE088@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E9824578BE96A@BGSMSX101.gar.corp.intel.com> <4A89E2EF3DFEDB4C8BFDE51014F606A14E4BF0DF@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4BF0DF@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTBiYmQ4MGQtZmYxMC00YTllLWFiYjctZjFjZjI1YjFlMGZiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiT0tMY3JycW03YVhSVnY4UXRGeFdmVTNMYjdFUnF1cnZQOHpWbTlRaXF0TkVEbFoyWkdwQXh1SHVWZHQyTlFRQSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable These new macros definitions define PCI attributes which exist in the PCI E= xpress Base Specification Revision 2.1; hence placing this in the PciExpres= s21.h align with the specification revision. Thanks Ashraf > -----Original Message----- > From: Gao, Liming > Sent: Thursday, July 25, 2019 8:05 PM > To: Javeed, Ashraf ; devel@edk2.groups.io > Cc: Kinney, Michael D ; Ni, Ray > ; Wu, Hao A > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standar= d > registers >=20 > I agree the structure update in PciExpress21.h. I also see some new macro > definitions. Can they be added to PciExpress40.h, for example: >=20 > #define PCIE_MAX_PAYLOAD_SIZE_128B 0 > #define PCIE_MAX_PAYLOAD_SIZE_256B 1 > #define PCIE_MAX_PAYLOAD_SIZE_512B 2 > #define PCIE_MAX_PAYLOAD_SIZE_1024B 3 > #define PCIE_MAX_PAYLOAD_SIZE_2048B 4 > #define PCIE_MAX_PAYLOAD_SIZE_4096B 5 > #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 > #define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 >=20 > #define PCIE_MAX_READ_REQ_SIZE_128B 0 > #define PCIE_MAX_READ_REQ_SIZE_256B 1 > #define PCIE_MAX_READ_REQ_SIZE_512B 2 > #define PCIE_MAX_READ_REQ_SIZE_1024B 3 > #define PCIE_MAX_READ_REQ_SIZE_2048B 4 > #define PCIE_MAX_READ_REQ_SIZE_4096B 5 > #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 > #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 >=20 > Thanks > Liming > > -----Original Message----- > > From: Javeed, Ashraf > > Sent: Thursday, July 25, 2019 10:24 PM > > To: Gao, Liming ; devel@edk2.groups.io > > Cc: Kinney, Michael D ; Ni, Ray > > ; Wu, Hao A > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry > > standard registers > > > > Liming, > > The existing structure are extended in PCI Express Base Specification R= evision > 4; hence I have made the change in PciExpress21.h. > > > > Thanks > > Ashraf > > > > > -----Original Message----- > > > From: Gao, Liming > > > Sent: Thursday, July 25, 2019 7:35 PM > > > To: Javeed, Ashraf ; devel@edk2.groups.io > > > Cc: Kinney, Michael D ; Ni, Ray > > > ; Wu, Hao A > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry > > > standard registers > > > > > > Ashraf: > > > So, those update base on PCI Express Base Specification Revision > > > 4.0. If new definitions are in version 4.0, they can be added into > > > PciExpress40.h. If the existing structure is extended, they can be ke= pt in > PciExpress21.h. > > > > > > Thanks > > > Liming > > > > -----Original Message----- > > > > From: Javeed, Ashraf > > > > Sent: Monday, July 22, 2019 2:26 PM > > > > To: devel@edk2.groups.io > > > > Cc: Kinney, Michael D ; Gao, Liming > > > > ; Ni, Ray ; Wu, Hao A > > > > > > > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry > > > > standard registers > > > > > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 > > > > The PCIe Device capability register #2 > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the > > > > PCI features like - LN system CLS, 10b Tag completer/requester > > > > register fields, emergency power reduction support and > > > > initialization requirement, and > > > FRS support. > > > > > > > > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) > > > > needs to be upgraded for the - emergency power reduction request > > > > enabling and also the 10b Extended Tag enabling. > > > > > > > > Needs macro definitions for all the ranges of Maximum Payload > > > > Sizes and Maximum Read Request Sizes defined > > > > > > > > Needs macro definitions for all the ranges of Completion Timeout > > > > range needs to be defined. > > > > > > > > Signed-off-by: Ashraf Javeed > > > > Cc: Michael D Kinney > > > > Cc: Liming Gao > > > > Cc: Ray Ni > > > > Cc: Hao A Wu > > > > --- > > > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39 > > > > ++++++++++++++++++++++++++++++++++++--- > > > > 1 file changed, 36 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h > > > > b/MdePkg/Include/IndustryStandard/PciExpress21.h > > > > index d4003de74c..e652e77a1e 100644 > > > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h > > > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h > > > > @@ -91,6 +91,24 @@ typedef union { > > > > UINT16 Uint16; > > > > } PCI_REG_PCIE_DEVICE_CONTROL; > > > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 > > > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 > > > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 > > > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define > > > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define > > > PCIE_MAX_PAYLOAD_SIZE_4096B 5 > > > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define > > > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 > > > > + > > > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0 > > > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1 > > > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2 > > > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 > > > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 > > > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 > > > > + > > > > typedef union { > > > > struct { > > > > UINT16 CorrectableError : 1; > > > > @@ -250,16 +268,30 @@ typedef union { > > > > UINT32 NoRoEnabledPrPrPassing : 1; > > > > UINT32 LtrMechanism : 1; > > > > UINT32 TphCompleter : 2; > > > > - UINT32 Reserved : 4; > > > > + UINT32 LnSystemCLS : 2; > > > > + UINT32 TenBitTagCompleterSupported : 1; > > > > + UINT32 TenBitTagRequesterSupported : 1; > > > > UINT32 Obff : 2; > > > > UINT32 ExtendedFmtField : 1; > > > > UINT32 EndEndTlpPrefix : 1; > > > > UINT32 MaxEndEndTlpPrefixes : 2; > > > > - UINT32 Reserved2 : 8; > > > > + UINT32 EmergencyPowerReductionSupported : 2; > > > > + UINT32 EmergencyPowerReductionInitializationRequired : 1; > > > > + UINT32 Reserved : 4; > > > > + UINT32 FrsSupported : 1; > > > > } Bits; > > > > UINT32 Uint32; > > > > } PCI_REG_PCIE_DEVICE_CAPABILITY2; > > > > > > > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 > > > > + > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 > > > > > > > > @@ -273,7 +305,8 @@ typedef union { > > > > UINT16 IdoRequest : 1; > > > > UINT16 IdoCompletion : 1; > > > > UINT16 LtrMechanism : 2; > > > > - UINT16 Reserved : 2; > > > > + UINT16 EmergencyPowerReductionRequest : 1; > > > > + UINT16 TenBitTagRequesterEnable : 1; > > > > UINT16 Obff : 2; > > > > UINT16 EndEndTlpPrefixBlocking : 1; > > > > } Bits; > > > > -- > > > > 2.21.0.windows.1