From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ashraf.javeed@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Thu, 25 Jul 2019 11:14:48 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 11:14:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,307,1559545200"; d="scan'208";a="170320990" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga008.fm.intel.com with ESMTP; 25 Jul 2019 11:14:47 -0700 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 11:14:47 -0700 Received: from bgsmsx103.gar.corp.intel.com (10.223.4.130) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 11:14:46 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.176]) by BGSMSX103.gar.corp.intel.com ([169.254.4.187]) with mapi id 14.03.0439.000; Thu, 25 Jul 2019 23:44:44 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Kinney, Michael D" , "Gao, Liming" , "Ni, Ray" , "Wu, Hao A" Subject: Re: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Topic: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Index: AQHVQxKHVULim5kxeEaa5HIOou6GrKbbo1IQ Date: Thu, 25 Jul 2019 18:14:43 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824578BEB52@BGSMSX101.gar.corp.intel.com> References: <15B4B82F76F0FE72.24444@groups.io> In-Reply-To: <15B4B82F76F0FE72.24444@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzgwMjhkZTctZTQzZi00MTM2LTg0ZTctZGUzOGVlZjIwMDExIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRjZmcWs0aGpRRE9CQ0VSQThlU3dRdWgrczFzS0pjMmNUVlk4QVwvWEdLeHNCVjMxM041YTRMVHZKQ1NDMGM1RVkifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please ignore this! I shall amend the commit message, reformat and send the patch again. Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Thursday, July 25, 2019 11:28 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Ni, Ray ; Wu, Hao A > > Subject: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe indust= ry > standard registers >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 > The following two PCI Capability Structure registers are updated as per = the PCI > Base Specification Revision 4:- > (1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2= ) > needs to be upgraded for the PCI features like - > LN system CLS (LnSystemCLS), > 10b Tag completer/requester register fields > (TenBitTagCompleterSupported, TenBitTagRequesterSupported), > Emergency power reduction support and initialization requirement > (EmergencyPowerReductionSupported, > EmergencyPowerReductionInitializationRequired), > and FRS support (FrsSupported ). >=20 > (2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) need= s > to be upgraded for the - > Emergency power reduction request enabling > (EmergencyPowerReductionRequest), and also the 10b Extended Tag > enabling (TenBitTagRequesterEnable). >=20 > The following two are defined as per the PCI Express Base Specification = Revision > 2.1:- > (1) Defined macro definitions for all the ranges of Maximum Payload Size= s > and Maximum Read Request Sizes defined >=20 > (2) Defined macro definitions for all the ranges of Completion Timeout > value. >=20 > Signed-off-by: Ashraf Javeed > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Ray Ni > Cc: Hao A Wu > --- > MdePkg/Include/IndustryStandard/PciExpress21.h | 39 > ++++++++++++++++++++++++++++++++++++--- > 1 file changed, 36 insertions(+), 3 deletions(-) >=20 > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h > b/MdePkg/Include/IndustryStandard/PciExpress21.h > index d4003de74c..e652e77a1e 100644 > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h > @@ -91,6 +91,24 @@ typedef union { > UINT16 Uint16; > } PCI_REG_PCIE_DEVICE_CONTROL; >=20 > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 > +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 > +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 > + > +#define PCIE_MAX_READ_REQ_SIZE_128B 0 > +#define PCIE_MAX_READ_REQ_SIZE_256B 1 > +#define PCIE_MAX_READ_REQ_SIZE_512B 2 > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 > + > typedef union { > struct { > UINT16 CorrectableError : 1; > @@ -250,16 +268,30 @@ typedef union { > UINT32 NoRoEnabledPrPrPassing : 1; > UINT32 LtrMechanism : 1; > UINT32 TphCompleter : 2; > - UINT32 Reserved : 4; > + UINT32 LnSystemCLS : 2; > + UINT32 TenBitTagCompleterSupported : 1; > + UINT32 TenBitTagRequesterSupported : 1; > UINT32 Obff : 2; > UINT32 ExtendedFmtField : 1; > UINT32 EndEndTlpPrefix : 1; > UINT32 MaxEndEndTlpPrefixes : 2; > - UINT32 Reserved2 : 8; > + UINT32 EmergencyPowerReductionSupported : 2; > + UINT32 EmergencyPowerReductionInitializationRequired : 1; > + UINT32 Reserved : 4; > + UINT32 FrsSupported : 1; > } Bits; > UINT32 Uint32; > } PCI_REG_PCIE_DEVICE_CAPABILITY2; >=20 > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 > + > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 >=20 > @@ -273,7 +305,8 @@ typedef union { > UINT16 IdoRequest : 1; > UINT16 IdoCompletion : 1; > UINT16 LtrMechanism : 2; > - UINT16 Reserved : 2; > + UINT16 EmergencyPowerReductionRequest : 1; > + UINT16 TenBitTagRequesterEnable : 1; > UINT16 Obff : 2; > UINT16 EndEndTlpPrefixBlocking : 1; > } Bits; > -- > 2.21.0.windows.1 >=20 >=20 >=20