From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Javeed, Ashraf" <ashraf.javeed@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>,
"Gao, Liming" <liming.gao@intel.com>,
"Ni, Ray" <ray.ni@intel.com>, "Wu, Hao A" <hao.a.wu@intel.com>
Subject: Re: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
Date: Thu, 25 Jul 2019 18:22:40 +0000 [thread overview]
Message-ID: <95C5C2B113DE604FB208120C742E9824578BEB6F@BGSMSX101.gar.corp.intel.com> (raw)
In-Reply-To: <15B4B93608B7CE6F.24444@groups.io>
Please ignore this!
Sent the patch with wrong commit message details.
Regards
Ashraf
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed,
> Ashraf
> Sent: Thursday, July 25, 2019 11:47 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> <hao.a.wu@intel.com>
> Subject: [edk2-devel] [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> standard registers
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
> needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
> completer/requester register fields, emergency power reduction support and
> initialization requirement, and FRS support.
>
> The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs
> to be upgraded for the - emergency power reduction request enabling and also
> the 10b Extended Tag enabling.
>
> Needs macro definitions for all the ranges of Maximum Payload Sizes and
> Maximum Read Request Sizes defined
>
> Needs macro definitions for all the ranges of Completion Timeout range needs
> to be defined.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> ---
> MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> b/MdePkg/Include/IndustryStandard/PciExpress21.h
> index d4003de74c..e652e77a1e 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> @@ -91,6 +91,24 @@ typedef union {
> UINT16 Uint16;
> } PCI_REG_PCIE_DEVICE_CONTROL;
>
> +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
> +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
> +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
> +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
> +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> +
> +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> +
> typedef union {
> struct {
> UINT16 CorrectableError : 1;
> @@ -250,16 +268,30 @@ typedef union {
> UINT32 NoRoEnabledPrPrPassing : 1;
> UINT32 LtrMechanism : 1;
> UINT32 TphCompleter : 2;
> - UINT32 Reserved : 4;
> + UINT32 LnSystemCLS : 2;
> + UINT32 TenBitTagCompleterSupported : 1;
> + UINT32 TenBitTagRequesterSupported : 1;
> UINT32 Obff : 2;
> UINT32 ExtendedFmtField : 1;
> UINT32 EndEndTlpPrefix : 1;
> UINT32 MaxEndEndTlpPrefixes : 2;
> - UINT32 Reserved2 : 8;
> + UINT32 EmergencyPowerReductionSupported : 2;
> + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> + UINT32 Reserved : 4;
> + UINT32 FrsSupported : 1;
> } Bits;
> UINT32 Uint32;
> } PCI_REG_PCIE_DEVICE_CAPABILITY2;
>
> +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> +
> #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
>
> @@ -273,7 +305,8 @@ typedef union {
> UINT16 IdoRequest : 1;
> UINT16 IdoCompletion : 1;
> UINT16 LtrMechanism : 2;
> - UINT16 Reserved : 2;
> + UINT16 EmergencyPowerReductionRequest : 1;
> + UINT16 TenBitTagRequesterEnable : 1;
> UINT16 Obff : 2;
> UINT16 EndEndTlpPrefixBlocking : 1;
> } Bits;
> --
> 2.21.0.windows.1
>
>
>
next parent reply other threads:[~2019-07-25 18:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <15B4B93608B7CE6F.24444@groups.io>
2019-07-25 18:22 ` Javeed, Ashraf [this message]
2019-07-25 18:23 [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Javeed, Ashraf
2019-07-25 21:20 ` [edk2-devel] " Laszlo Ersek
2019-07-25 21:52 ` Laszlo Ersek
2019-07-26 1:40 ` Javeed, Ashraf
2019-07-26 1:47 ` Javeed, Ashraf
2019-07-26 2:32 ` Wu, Hao A
[not found] <15B4B82F76F0FE72.24444@groups.io>
2019-07-25 18:14 ` Javeed, Ashraf
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