From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ashraf.javeed@intel.com) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Mon, 29 Jul 2019 01:00:14 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jul 2019 00:59:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,322,1559545200"; d="scan'208";a="173791926" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 29 Jul 2019 00:59:21 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 29 Jul 2019 00:59:20 -0700 Received: from BGSMSX108.gar.corp.intel.com (10.223.4.192) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 29 Jul 2019 00:59:20 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.176]) by BGSMSX108.gar.corp.intel.com ([169.254.8.155]) with mapi id 14.03.0439.000; Mon, 29 Jul 2019 13:29:17 +0530 From: "Javeed, Ashraf" To: "Gao, Liming" , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "Ni, Ray" , "Wu, Hao A" Subject: Re: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard register defines Thread-Topic: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard register defines Thread-Index: AQHVRcDp9rZrVlrpOUq2VptQYFWa0qbhOhUwgAABZFA= Date: Mon, 29 Jul 2019 07:59:16 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824578BF994@BGSMSX101.gar.corp.intel.com> References: <20190729035123.12444-1-ashraf.javeed@intel.com> <4A89E2EF3DFEDB4C8BFDE51014F606A14E4C44D9@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4C44D9@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjQwZWVkMjItMzRmMS00NjQwLWIwZjYtZmJkYzNiZWI1ZjUyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieXlEMm1UODdNb3ZnclJZZEpWTjBOZktvd3hxS2x0Tjk4OWdOd1M5dkNnbGZwNmxKbDltNWN6YTdubzRQSVwvUDkifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Liming! > -----Original Message----- > From: Gao, Liming > Sent: Monday, July 29, 2019 1:24 PM > To: Javeed, Ashraf ; devel@edk2.groups.io > Cc: Kinney, Michael D ; Ni, Ray > ; Wu, Hao A > Subject: RE: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry stand= ard > register defines >=20 > The patch is good. Reviewed-by: Liming Gao >=20 > >-----Original Message----- > >From: Javeed, Ashraf > >Sent: Monday, July 29, 2019 11:51 AM > >To: devel@edk2.groups.io > >Cc: Kinney, Michael D ; Gao, Liming > >; Ni, Ray ; Wu, Hao A > > > >Subject: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry > >standard register defines > > > >BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 > >The following two PCI Capability Structure registers are updated as per > >the PCI Base Specification Revision 4:- > >(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2= ) > > needs to be upgraded for the PCI features like - > > LN system CLS (LnSystemCLS), > > 10b Tag completer/requester register fields > > (TenBitTagCompleterSupported, TenBitTagRequesterSupported), > > Emergency power reduction support and initialization requirement > > (EmergencyPowerReductionSupported, > > EmergencyPowerReductionInitializationRequired), > > and FRS support (FrsSupported ). > > > >(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) > >needs > > to be upgraded for the - > > Emergency power reduction request enabling > > (EmergencyPowerReductionRequest), and also the 10b Extended Tag > > enabling (TenBitTagRequesterEnable). > > > >The following two are defined as per the PCI Express Base Specification > >Revision 2.1:- > >(1) Defined macro definitions for all the ranges of Maximum Payload Size= s > > and Maximum Read Request Sizes register fields > > > >(2) Defined macro definitions for all the ranges of Completion Timeout > > value. > > > > > >Signed-off-by: Ashraf Javeed > >Cc: Michael D Kinney > >Cc: Liming Gao > >Cc: Ray Ni > >Cc: Hao A Wu > >--- > > > >In V2: Reserved field name change in PCI_REG_PCIE_DEVICE_CAPABILITY2 > >--- > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39 > >++++++++++++++++++++++++++++++++++++--- > > 1 file changed, 36 insertions(+), 3 deletions(-) > > > >diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h > >b/MdePkg/Include/IndustryStandard/PciExpress21.h > >index d4003de74c..f17f570775 100644 > >--- a/MdePkg/Include/IndustryStandard/PciExpress21.h > >+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h > >@@ -91,6 +91,24 @@ typedef union { > > UINT16 Uint16; > > } PCI_REG_PCIE_DEVICE_CONTROL; > > > >+#define PCIE_MAX_PAYLOAD_SIZE_128B 0 > >+#define PCIE_MAX_PAYLOAD_SIZE_256B 1 > >+#define PCIE_MAX_PAYLOAD_SIZE_512B 2 > >+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define > >+PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define > PCIE_MAX_PAYLOAD_SIZE_4096B 5 > >+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define > >+PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 > >+ > >+#define PCIE_MAX_READ_REQ_SIZE_128B 0 > >+#define PCIE_MAX_READ_REQ_SIZE_256B 1 > >+#define PCIE_MAX_READ_REQ_SIZE_512B 2 > >+#define PCIE_MAX_READ_REQ_SIZE_1024B 3 > >+#define PCIE_MAX_READ_REQ_SIZE_2048B 4 > >+#define PCIE_MAX_READ_REQ_SIZE_4096B 5 > >+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 > >+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 > >+ > > typedef union { > > struct { > > UINT16 CorrectableError : 1; > >@@ -250,16 +268,30 @@ typedef union { > > UINT32 NoRoEnabledPrPrPassing : 1; > > UINT32 LtrMechanism : 1; > > UINT32 TphCompleter : 2; > >- UINT32 Reserved : 4; > >+ UINT32 LnSystemCLS : 2; > >+ UINT32 TenBitTagCompleterSupported : 1; > >+ UINT32 TenBitTagRequesterSupported : 1; > > UINT32 Obff : 2; > > UINT32 ExtendedFmtField : 1; > > UINT32 EndEndTlpPrefix : 1; > > UINT32 MaxEndEndTlpPrefixes : 2; > >- UINT32 Reserved2 : 8; > >+ UINT32 EmergencyPowerReductionSupported : 2; > >+ UINT32 EmergencyPowerReductionInitializationRequired : 1; > >+ UINT32 Reserved3 : 4; > >+ UINT32 FrsSupported : 1; > > } Bits; > > UINT32 Uint32; > > } PCI_REG_PCIE_DEVICE_CAPABILITY2; > > > >+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 > >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 > >+ > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 > > > >@@ -273,7 +305,8 @@ typedef union { > > UINT16 IdoRequest : 1; > > UINT16 IdoCompletion : 1; > > UINT16 LtrMechanism : 2; > >- UINT16 Reserved : 2; > >+ UINT16 EmergencyPowerReductionRequest : 1; > >+ UINT16 TenBitTagRequesterEnable : 1; > > UINT16 Obff : 2; > > UINT16 EndEndTlpPrefixBlocking : 1; > > } Bits; > >-- > >2.21.0.windows.1