From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.1333.1571129405586430146 for ; Tue, 15 Oct 2019 01:50:05 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Oct 2019 01:50:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,298,1566889200"; d="scan'208";a="279125209" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 15 Oct 2019 01:50:03 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 15 Oct 2019 01:50:03 -0700 Received: from bgsmsx104.gar.corp.intel.com (10.223.4.190) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 15 Oct 2019 01:50:02 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.199]) by BGSMSX104.gar.corp.intel.com ([169.254.5.180]) with mapi id 14.03.0439.000; Tue, 15 Oct 2019 14:19:58 +0530 From: "Javeed, Ashraf" To: "Ni, Ray" , "'devel@edk2.groups.io'" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH] PciBusDxe: New PCI features Max_Payload_Size, Max_Read_Req_Size Thread-Topic: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH] PciBusDxe: New PCI features Max_Payload_Size, Max_Read_Req_Size Thread-Index: AQHVcho7l4BFAB45b0GVT+j70Hksa6dZkjEAgABqo4CAASu7UIAAKxHwgAAqq2A= Date: Tue, 15 Oct 2019 08:49:57 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824578FF85C@BGSMSX101.gar.corp.intel.com> References: <20190923142051.10832-1-ashraf.javeed@intel.com> <734D49CCEBEEF84792F5B80ED585239D5C322169@SHSMSX104.ccr.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C322525@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E9824578FF7B4@BGSMSX101.gar.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C32333C@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C32333C@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTQ3NTQzMzMtYzgzOS00ZGI5LWE1ZDItYTgxZGIzZDRjYWU5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidVd6bnZsOWdVamlDZlRQZzhrTXJGTXh0MytsTkVncGc3TE1ZOU56UnJEOVAwdTBYKzJ0QnIxK2s2RnROTEtNUyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Ni, Ray > Sent: Tuesday, October 15, 2019 1:18 PM > To: Javeed, Ashraf ; 'devel@edk2.groups.io' > > Cc: Wang, Jian J ; Wu, Hao A > Subject: RE: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH] PciBusDxe: New PCI > features Max_Payload_Size, Max_Read_Req_Size >=20 > > > More comments: > > > 1. IsPciRootPortEmpty(): can you just check whether PciDevice->ChildL= ist is > > > empty by using IsListEmpty (&PciDevice->ChildList)? > > OK, will do the additional check. >=20 > Can that be the only check? It cannot be the only check when I am parsing the list as it is going to lo= op over; or may be where exactly you want to have this check? I understand = it can be the first check before traversing the list. >=20 > > > > > 2. Can you point to me which spec requires the MPS to be 128 for empt= y > > root > > > ports? > > Refer the PCI Express Base Specification Revision 5, chapter 7.5.3.4 > > Implementation Notes section. > Can you please paste the specific wording that supports the logic to prog= ram > MPS to 128B for empty root ports? > Below wording seems to require 128B only for special OSes that don't supp= ort > PCIE. > " For example, if the operating system environment does not comprehend PC= I > Express, firmware probably should > not program a non-default Max_Payload_Size for a hierarchy that supports = Hot- > Plug operations" Yes; since the PCI Bus driver does not know what OS it is going to boot to,= it has to assume for the worst and set it to default, or leave it to defau= lt as the HW default is set to 128B. Besides, the Max_Payload_Size is for t= he Data Packet size, since the PCI RP is empty there is no point changing = to any other value as there won't be any PCI transactions. >=20 > > > > > 3. GetPciRootPortBusAssigned() is dangerous because it assumes the in= put > > > PciDevice points to the bridge. > > Good catch! Will make the right change. >=20 > As we discussed over phone, using device path can eliminate the needs of > comparing bus number. Then this function is not needed. Yes, I am looking towards that direction. >=20 > > > > > 4. RecordPciRootPortBridges() could be simplified to just collect all > > PciDevice > > > instances who: > > > a. belongs to the linked list of the root bridge > > > b. is a bridge > > I can see if I can optimize further, but do note that I need to align t= he PCI > > feature Max_Payload_Size and Max_Read_Request_Size among all the child > > PCI devices of the Root Port (RP) in the Root Complex (RC) and since a = single > > RC is known to have multiple RP I need to maintain the list of all the = primary > > RP in the Root Bridge handle so that each primary RP can have its PCI > > configuration table to track the Max_Payload_Size and > > Max_Read_Request_Size that needs to be assigned to all its child PCI de= vices > > in the tree. >=20 > I am not suggesting to stop collecting all root ports. > Can you simplify the logic of RecordPciRootPortBridges() as below? > for each node in PciRootBridge.ChildList: > if (!IsListEmpty (node.ChildList)) { > RootPortList.add (node) OK, will do. >=20 > > > > 2. GetPciPlatformProtocol(): better to rename to InitializePciPlatf= orm (). > > To me, the word "Initialize" would mean also installing the PCI Platfor= m > > Protocol which is not the case with the PCI Bus driver; since it only f= etches > > the existing protocol already installed by the platform... > I agree with your concern : ) > But "Get" means to return the PciPlatform protocol back through function = return > result. > How about "Locate"? Ok, will use this key word. >=20 > > > > > > 3. Why the type cast is needed in below code? If it is because > > PciPlatform2 > > > > protocol reuses the prototype of GetPciRom defined for PciPlatform > > protocol, > > > > I suggest you define GetPciRom for PciPlatform2. Type redefinition > > seems a > > > > duplication. But below type-cast is more annoyed. > > > > > > > > Status =3D mPciPlatformProtocol2->GetPciRom ( > > > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciPlatformProtocol2, > > > > PciIoDevice->Handle, > > > > &PlatformOpRomBuffer, > > > > &PlatformOpRomSize > > > > ); > > > > > > Yes, the PciPlatform2.h which I had submitted to the edk2-staging branc= h > > previously; includes the PciPlatform.h during compilation. Even I was t= hinking > > the same and since the new definition of the PCI Platform Protocol has = to > > used in future; I can port the legacy definitions into the new definiti= on source > > file itself to avoid further change in future. >=20 > Thanks. >=20 > > > > > > 4. Please run ECC tool and fix all coding style issue > > I thought the ECC tool is used once the changes are submitted into the > > Gerritt by the maintainer; it is good if I can use it offline; please l= et me know > > where to get this tool. >=20 > The tool is inside BaseTools\BinWrappers\WindowsLike\Ecc.bat. Thanks! Will use this. By the way; I did make the code changes by referring= the "EDK-II C Coding Style Standards Specification". >=20 > > > > > > 5. I don't quite understand what *primary* PCI root port is. So I d= on't > > quite > > > > understand what RecordPciRootPortBridges() does. > > I used the word primary for the PCI Root port to indicate the first lev= el Root > > port in the RC of the host; there can be multiple first level PCI RP in= the Root > > Bridge handle and each RP can have its downstream hierarchy which in tu= rn > > can be the PCIe-PCIe/PCI/PCI-X bridge devices and its endpoint devices. > > Since the RP and its downstream PCI bridges both have the same PCI Type= 1 > > PCI Configuration header, I have to maintain the list of first level RP= of the > > Root Bridge handle. > > > > > > > > > > Thanks, > > > > Ray > > > > > > > > > -----Original Message----- > > > > > From: Javeed, Ashraf > > > > > Sent: Monday, September 23, 2019 10:21 PM > > > > > To: devel@edk2.groups.io > > > > > Cc: Wang, Jian J ; Wu, Hao A > > > > ; > > > > > Ni, Ray > > > > > Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH] PciBusDxe: New > > PCI > > > > > features Max_Payload_Size, Max_Read_Req_Size > > > > > > > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > > > > > > > > > > The EDK2 Kernel PciBusDxe driver is enhanced to enable the > > configuration > > > > > of PCI features like Max_Payload_Size and Max_Read_Req_Size. > > > > > > > > > > Max_Payload_Size:- The PCI Device Control register provides this > > feature > > > > > register field which controls the maximum data packet (TLP) size = that a > > > > > PCI device should maintain as a requester. The PCI Bus driver is > > required > > > > > to maintain a highest common value supported by all the PCI devic= es in > > a > > > > > PCIe hierarchy, especially in case of isochronous applications. > > > > > > > > > > Max_Read_Req_Size:- The PCI Device Control register provides this > > > > feature > > > > > register field which controls the maximum memory read request siz= e > > that a > > > > > PCI device should maintain as a requester. The PCI Bus driver is > > required > > > > > to maintain a common value, same as Max_Payload_Size, in case of > > > > > isochronous applications only; or else, it should maintain the us= er > > > > > requested value uniformly in a PCIe hierarchy (PCI root port and = its > > > > > downstream devices). > > > > > > > > > > The PCI Base Specification 4 Revision 1 contains detailed informa= tion > > > > > about these features. The EDK2 PCI Bus driver needs to enable the > > > > > configuration of these features as per the PCI Base specification= . > > > > > > > > > > The EDK2 PCI Bus driver also needs to take the PCI device-specifi= c > > > > > platform policy into the consideration while programming these > > features; > > > > > thus the code changes to support these, is explicitly dependent o= n the > > > > > new PCI Platform Protocol interface definition defined in the bel= ow > > > > > record:- > > > > > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > > > > > > > > > > Signed-off-by: Ashraf Javeed > > > > > Cc: Jian J Wang > > > > > Cc: Hao A Wu > > > > > Cc: Ray Ni > > > > > --- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 ++-= ----------- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 14 +++= +++++- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 9 +++= ++- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 229 > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > ++++++++++++++++++++++++++++-------------------------------------= ----- > > ----- > > > > - > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 > > > > > ++++++++++++++++++++---------------------------------------------= ---------- > > ---- > > > > --- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 > > > > > ++++++++++++-------- > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 1601 > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > +++++++++ > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 201 > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > ++ > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 565 > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > +++++++++++++++++++++++++++++++++++++++++ > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 193 > > > > > > > > > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +--= --- > > --- > > > > > MdeModulePkg/MdeModulePkg.dec | 10 +++= +++ > > > > > 12 files changed, 2797 insertions(+), 236 deletions(-) > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > > > > > index b020ce50ce..2503b298f4 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > > > > > @@ -8,7 +8,7 @@ > > > > > PCI Root Bridges. So it means platform needs install PCI Root = Bridge IO > > > > > protocol for each > > > > > > > > > > PCI Root Bus and install PCI Host Bridge Resource Allocation P= rotocol. > > > > > > > > > > > > > > > > > > > > -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserve= d.
> > > > > > > > > > +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserve= d.
> > > > > > > > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > > > > > > > > > > > **/ > > > > > > > > > > @@ -34,8 +34,6 @@ BOOLEAN g= FullEnumeration > =3D > > > > TRUE; > > > > > UINT64 gAllOne = =3D 0xFFFFFFFFFFFFFFFFULL; > > > > > > > > > > UINT64 gAllZero = =3D 0; > > > > > > > > > > > > > > > > > > > > -EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProto= col; > > > > > > > > > > -EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProto= col; > > > > > > > > > > EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > @@ -266,24 +264,7 @@ PciBusDriverBindingStart ( > > > > > // If PCI Platform protocol is available, get it now. > > > > > > > > > > // If the platform implements this, it must be installed befor= e BDS > > phase > > > > > > > > > > // > > > > > > > > > > - gPciPlatformProtocol =3D NULL; > > > > > > > > > > - gBS->LocateProtocol ( > > > > > > > > > > - &gEfiPciPlatformProtocolGuid, > > > > > > > > > > - NULL, > > > > > > > > > > - (VOID **) &gPciPlatformProtocol > > > > > > > > > > - ); > > > > > > > > > > - > > > > > > > > > > - // > > > > > > > > > > - // If PCI Platform protocol doesn't exist, try to Pci Override= Protocol. > > > > > > > > > > - // > > > > > > > > > > - if (gPciPlatformProtocol =3D=3D NULL) { > > > > > > > > > > - gPciOverrideProtocol =3D NULL; > > > > > > > > > > - gBS->LocateProtocol ( > > > > > > > > > > - &gEfiPciOverrideProtocolGuid, > > > > > > > > > > - NULL, > > > > > > > > > > - (VOID **) &gPciOverrideProtocol > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > + GetPciPlatformProtocol (); > > > > > > > > > > > > > > > > > > > > if (mIoMmuProtocol =3D=3D NULL) { > > > > > > > > > > gBS->LocateProtocol ( > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > > > > index 504a1b1c12..7955bf8a26 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > > > > @@ -27,6 +27,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > #include > > > > > > > > > > #include > > > > > > > > > > #include > > > > > > > > > > +#include > > > > > > > > > > +#include > > > > > > > > > > > > > > > > > > > > #include > > > > > > > > > > #include > > > > > > > > > > @@ -79,6 +81,7 @@ typedef enum { > > > > > #include "PciPowerManagement.h" > > > > > > > > > > #include "PciHotPlugSupport.h" > > > > > > > > > > #include "PciLib.h" > > > > > > > > > > +#include "PciFeatureSupport.h" > > > > > > > > > > > > > > > > > > > > #define VGABASE1 0x3B0 > > > > > > > > > > #define VGALIMIT1 0x3BB > > > > > > > > > > @@ -263,9 +266,13 @@ struct _PCI_IO_DEVICE { > > > > > > > > > > > > > > > BOOLEAN IsPciExp; > > > > > > > > > > // > > > > > > > > > > - // For SR-IOV > > > > > > > > > > + // For PCI Express Capability List Structure > > > > > > > > > > // > > > > > > > > > > UINT8 PciExpressCapability= Offset; > > > > > > > > > > + PCI_CAPABILITY_PCIEXP PciExpStruct; > > > > > > > > > > + // > > > > > > > > > > + // For SR-IOV > > > > > > > > > > + // > > > > > > > > > > UINT32 AriCapabilityOffset; > > > > > > > > > > UINT32 SrIovCapabilityOffse= t; > > > > > > > > > > UINT32 MrIovCapabilityOffse= t; > > > > > > > > > > @@ -279,6 +286,11 @@ struct _PCI_IO_DEVICE { > > > > > // This field is used to support this case. > > > > > > > > > > // > > > > > > > > > > UINT16 BridgeIoAlignment; > > > > > > > > > > + // > > > > > > > > > > + // Other PCI features setup flags > > > > > > > > > > + // > > > > > > > > > > + UINT8 SetupMPS; > > > > > > > > > > + UINT8 SetupMRRS; > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > > > > index 05c22025b8..13768d7ded 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > > > > @@ -2,7 +2,7 @@ > > > > > # The PCI bus driver will probe all PCI devices and allocate MM= IO and > > IO > > > > > space for these devices. > > > > > > > > > > # Please use PCD feature flag PcdPciBusHotplugDeviceSupport to > > enable > > > > > hot plug supporting. > > > > > > > > > > # > > > > > > > > > > -# Copyright (c) 2006 - 2018, Intel Corporation. All rights rese= rved.
> > > > > > > > > > +# Copyright (c) 2006 - 2019, Intel Corporation. All rights rese= rved.
> > > > > > > > > > # > > > > > > > > > > # SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > # > > > > > > > > > > @@ -57,6 +57,10 @@ > > > > > PciCommand.h > > > > > > > > > > PciIo.h > > > > > > > > > > PciBus.h > > > > > > > > > > + PciFeatureSupport.c > > > > > > > > > > + PciFeatureSupport.h > > > > > > > > > > + PciPlatformSupport.c > > > > > > > > > > + PciPlatformSupport.h > > > > > > > > > > > > > > > > > > > > [Packages] > > > > > > > > > > MdePkg/MdePkg.dec > > > > > > > > > > @@ -91,6 +95,8 @@ > > > > > gEfiLoadFile2ProtocolGuid ## SOMETIMES_P= RODUCES > > > > > > > > > > gEdkiiIoMmuProtocolGuid ## SOMETIMES_C= ONSUMES > > > > > > > > > > gEfiLoadedImageDevicePathProtocolGuid ## CONSUMES > > > > > > > > > > + gEfiPciPlatformProtocol2Guid ## SOMETIMES_= CONSUMES > > > > > > > > > > + gEfiPciOverrideProtocol2Guid ## SOMETIMES_= CONSUMES > > > > > > > > > > > > > > > > > > > > [FeaturePcd] > > > > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport > > > > ## > > > > > CONSUMES > > > > > > > > > > @@ -104,6 +110,7 @@ > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport = ## > > > > CONSUMES > > > > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport = ## > > > > > CONSUMES > > > > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration > > ## > > > > > SOMETIMES_CONSUMES > > > > > > > > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdOtherPciFeatures > > ## > > > > > CONSUMES > > > > > > > > > > > > > > > > > > > > [UserExtensions.TianoCore."ExtraFiles"] > > > > > > > > > > PciBusDxeExtra.uni > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > > > > > index b7832c6970..0f76ab1cd5 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > > > > > @@ -170,6 +170,8 @@ DestroyRootBridgeByHandle ( > > > > > > > > > > > > > > > if (Temp->Handle =3D=3D Controller) { > > > > > > > > > > > > > > > > > > > > + DestroyRootBridgePciFeaturesConfigCompletionList ( Temp); > > > > > > > > > > + > > > > > > > > > > RemoveEntryList (CurrentLink); > > > > > > > > > > > > > > > > > > > > DestroyPciDeviceTree (Temp); > > > > > > > > > > @@ -208,8 +210,6 @@ RegisterPciDevice ( > > > > > ) > > > > > > > > > > { > > > > > > > > > > EFI_STATUS Status; > > > > > > > > > > - VOID *PlatformOpRomBuffer; > > > > > > > > > > - UINTN PlatformOpRomSize; > > > > > > > > > > EFI_PCI_IO_PROTOCOL *PciIo; > > > > > > > > > > UINT8 Data8; > > > > > > > > > > BOOLEAN HasEfiImage; > > > > > > > > > > @@ -244,49 +244,13 @@ RegisterPciDevice ( > > > > > // > > > > > > > > > > // Get the OpRom provided by platform > > > > > > > > > > // > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > - Status =3D gPciPlatformProtocol->GetPciRom ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - PciIoDevice->Handle, > > > > > > > > > > - &PlatformOpRomBuffer, > > > > > > > > > > - &PlatformOpRomSize > > > > > > > > > > - ); > > > > > > > > > > - if (!EFI_ERROR (Status)) { > > > > > > > > > > - PciIoDevice->EmbeddedRom =3D FALSE; > > > > > > > > > > - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSi= ze; > > > > > > > > > > - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > > > > > > > > > > - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > > > > > > > > > > - // > > > > > > > > > > - // For OpROM read from gPciPlatformProtocol: > > > > > > > > > > - // Add the Rom Image to internal database for later PCI = light > > > > > enumeration > > > > > > > > > > - // > > > > > > > > > > - PciRomAddImageMapping ( > > > > > > > > > > - NULL, > > > > > > > > > > - PciIoDevice->PciRootBridgeIo->SegmentNumber, > > > > > > > > > > - PciIoDevice->BusNumber, > > > > > > > > > > - PciIoDevice->DeviceNumber, > > > > > > > > > > - PciIoDevice->FunctionNumber, > > > > > > > > > > - PciIoDevice->PciIo.RomImage, > > > > > > > > > > - PciIoDevice->PciIo.RomSize > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > - } else if (gPciOverrideProtocol !=3D NULL) { > > > > > > > > > > - Status =3D gPciOverrideProtocol->GetPciRom ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - PciIoDevice->Handle, > > > > > > > > > > - &PlatformOpRomBuffer, > > > > > > > > > > - &PlatformOpRomSize > > > > > > > > > > - ); > > > > > > > > > > - if (!EFI_ERROR (Status)) { > > > > > > > > > > - PciIoDevice->EmbeddedRom =3D FALSE; > > > > > > > > > > - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSi= ze; > > > > > > > > > > - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > > > > > > > > > > - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > > > > > > > > > > - // > > > > > > > > > > - // For OpROM read from gPciOverrideProtocol: > > > > > > > > > > - // Add the Rom Image to internal database for later PCI = light > > > > > enumeration > > > > > > > > > > - // > > > > > > > > > > - PciRomAddImageMapping ( > > > > > > > > > > + Status =3D GetPlatformPciOptionRom ( Controller, PciIoDevice= ); > > > > > > > > > > + if (!EFI_ERROR (Status)) { > > > > > > > > > > + // > > > > > > > > > > + // For OpROM read from the PCI Platform Protocol: > > > > > > > > > > + // Add the Rom Image to internal database for later PCI li= ght > > > > > enumeration > > > > > > > > > > + // > > > > > > > > > > + PciRomAddImageMapping ( > > > > > > > > > > NULL, > > > > > > > > > > PciIoDevice->PciRootBridgeIo->SegmentNumber, > > > > > > > > > > PciIoDevice->BusNumber, > > > > > > > > > > @@ -294,8 +258,7 @@ RegisterPciDevice ( > > > > > PciIoDevice->FunctionNumber, > > > > > > > > > > PciIoDevice->PciIo.RomImage, > > > > > > > > > > PciIoDevice->PciIo.RomSize > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > + ); > > > > > > > > > > } > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > @@ -597,7 +560,7 @@ DeRegisterPciDevice ( > > > > > } > > > > > > > > > > > > > > > > > > > > /** > > > > > > > > > > - Start to manage the PCI device on the specified root bridge or= PCI-PCI > > > > > Bridge. > > > > > > > > > > + Start the PCI root Ports or PCI-PCI Bridge only. > > > > > > > > > > > > > > > > > > > > @param Controller The root bridge handle. > > > > > > > > > > @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > @@ -612,7 +575,82 @@ DeRegisterPciDevice ( > > > > > > > > > > > > > > > **/ > > > > > > > > > > EFI_STATUS > > > > > > > > > > -StartPciDevicesOnBridge ( > > > > > > > > > > +StartPciRootPortsOnBridge ( > > > > > > > > > > + IN EFI_HANDLE Controller, > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > + > > > > > > > > > > +{ > > > > > > > > > > + PCI_IO_DEVICE *PciIoDevice; > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + LIST_ENTRY *CurrentLink; > > > > > > > > > > + UINT64 Supports; > > > > > > > > > > + > > > > > > > > > > + PciIoDevice =3D NULL; > > > > > > > > > > + CurrentLink =3D RootBridge->ChildList.ForwardLink; > > > > > > > > > > + > > > > > > > > > > + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridge->= ChildList) > > { > > > > > > > > > > + > > > > > > > > > > + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // check if the device has been assigned with required resou= rce > > > > > > > > > > + // and registered > > > > > > > > > > + // > > > > > > > > > > + if (!PciIoDevice->Registered && !PciIoDevice->Allocated) { > > > > > > > > > > + return EFI_NOT_READY; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > > > > > > > > > > + Status =3D StartPciRootPortsOnBridge ( > > > > > > > > > > + Controller, > > > > > > > > > > + PciIoDevice > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + PciIoDevice->PciIo.Attributes ( > > > > > > > > > > + &(PciIoDevice->PciIo), > > > > > > > > > > + EfiPciIoAttributeOperationSupported, > > > > > > > > > > + 0, > > > > > > > > > > + &Supports > > > > > > > > > > + ); > > > > > > > > > > + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > > > > > > > > > > + PciIoDevice->PciIo.Attributes ( > > > > > > > > > > + &(PciIoDevice->PciIo), > > > > > > > > > > + EfiPciIoAttributeOperationEnable, > > > > > > > > > > + Supports, > > > > > > > > > > + NULL > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + CurrentLink =3D CurrentLink->ForwardLink; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (PciIoDevice =3D=3D NULL) { > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } else { > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Register to manage the PCI device on the specified root bridge= or > > PCI-PCI > > > > > Bridge. > > > > > > > > > > + > > > > > > > > > > + @param Controller The root bridge handle. > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + @param RemainingDevicePath A pointer to the > > > > > EFI_DEVICE_PATH_PROTOCOL. > > > > > > > > > > + @param NumberOfChildren Children number. > > > > > > > > > > + @param ChildHandleBuffer A pointer to the child handle buffe= r. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_NOT_READY Device is not allocated. > > > > > > > > > > + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. > > > > > > > > > > + @retval EFI_NOT_FOUND Can not find the specific device. > > > > > > > > > > + @retval EFI_SUCCESS Success to start Pci devices on bridge= . > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +RegisterPciDevicesOnBridge ( > > > > > > > > > > IN EFI_HANDLE Controller, > > > > > > > > > > IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, > > > > > > > > > > @@ -626,7 +664,6 @@ StartPciDevicesOnBridge ( > > > > > EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath; > > > > > > > > > > EFI_STATUS Status; > > > > > > > > > > LIST_ENTRY *CurrentLink; > > > > > > > > > > - UINT64 Supports; > > > > > > > > > > > > > > > > > > > > PciIoDevice =3D NULL; > > > > > > > > > > CurrentLink =3D RootBridge->ChildList.ForwardLink; > > > > > > > > > > @@ -681,7 +718,7 @@ StartPciDevicesOnBridge ( > > > > > // If it is a PPB > > > > > > > > > > // > > > > > > > > > > if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > > > > > > > > > > - Status =3D StartPciDevicesOnBridge ( > > > > > > > > > > + Status =3D RegisterPciDevicesOnBridge ( > > > > > > > > > > Controller, > > > > > > > > > > PciIoDevice, > > > > > > > > > > CurrentDevicePath, > > > > > > > > > > @@ -689,20 +726,6 @@ StartPciDevicesOnBridge ( > > > > > ChildHandleBuffer > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > - PciIoDevice->PciIo.Attributes ( > > > > > > > > > > - &(PciIoDevice->PciIo), > > > > > > > > > > - EfiPciIoAttributeOperationSupported= , > > > > > > > > > > - 0, > > > > > > > > > > - &Supports > > > > > > > > > > - ); > > > > > > > > > > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > > > > > > > > > > - PciIoDevice->PciIo.Attributes ( > > > > > > > > > > - &(PciIoDevice->PciIo), > > > > > > > > > > - EfiPciIoAttributeOperationEnable, > > > > > > > > > > - Supports, > > > > > > > > > > - NULL > > > > > > > > > > - ); > > > > > > > > > > - > > > > > > > > > > return Status; > > > > > > > > > > } else { > > > > > > > > > > > > > > > > > > > > @@ -733,28 +756,13 @@ StartPciDevicesOnBridge ( > > > > > } > > > > > > > > > > > > > > > > > > > > if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > > > > > > > > > > - Status =3D StartPciDevicesOnBridge ( > > > > > > > > > > + Status =3D RegisterPciDevicesOnBridge ( > > > > > > > > > > Controller, > > > > > > > > > > PciIoDevice, > > > > > > > > > > RemainingDevicePath, > > > > > > > > > > NumberOfChildren, > > > > > > > > > > ChildHandleBuffer > > > > > > > > > > ); > > > > > > > > > > - > > > > > > > > > > - PciIoDevice->PciIo.Attributes ( > > > > > > > > > > - &(PciIoDevice->PciIo), > > > > > > > > > > - EfiPciIoAttributeOperationSupported= , > > > > > > > > > > - 0, > > > > > > > > > > - &Supports > > > > > > > > > > - ); > > > > > > > > > > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > > > > > > > > > > - PciIoDevice->PciIo.Attributes ( > > > > > > > > > > - &(PciIoDevice->PciIo), > > > > > > > > > > - EfiPciIoAttributeOperationEnable, > > > > > > > > > > - Supports, > > > > > > > > > > - NULL > > > > > > > > > > - ); > > > > > > > > > > - > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > CurrentLink =3D CurrentLink->ForwardLink; > > > > > > > > > > @@ -768,6 +776,65 @@ StartPciDevicesOnBridge ( > > > > > } > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > +/** > > > > > > > > > > + Start to manage the PCI device on the specified root bridge or= PCI-PCI > > > > > Bridge. > > > > > > > > > > + > > > > > > > > > > + @param Controller The root bridge handle. > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + @param RemainingDevicePath A pointer to the > > > > > EFI_DEVICE_PATH_PROTOCOL. > > > > > > > > > > + @param NumberOfChildren Children number. > > > > > > > > > > + @param ChildHandleBuffer A pointer to the child handle buffe= r. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_NOT_READY Device is not allocated. > > > > > > > > > > + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. > > > > > > > > > > + @retval EFI_NOT_FOUND Can not find the specific device. > > > > > > > > > > + @retval EFI_SUCCESS Success to start Pci devices on bridge= . > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +StartPciDevicesOnBridge ( > > > > > > > > > > + IN EFI_HANDLE Controller, > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, > > > > > > > > > > + IN OUT UINT8 *NumberOfChildren, > > > > > > > > > > + IN OUT EFI_HANDLE *ChildHandleBuffer > > > > > > > > > > + ) > > > > > > > > > > + > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // first register all the PCI devices > > > > > > > > > > + // > > > > > > > > > > + Status =3D RegisterPciDevicesOnBridge ( > > > > > > > > > > + Controller, > > > > > > > > > > + RootBridge, > > > > > > > > > > + RemainingDevicePath, > > > > > > > > > > + NumberOfChildren, > > > > > > > > > > + ChildHandleBuffer > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + if (EFI_ERROR (Status) =3D=3D EFI_NOT_FOUND) { > > > > > > > > > > + return Status; > > > > > > > > > > + } else { > > > > > > > > > > + if ( CheckOtherPciFeaturesPcd ()) { > > > > > > > > > > + // > > > > > > > > > > + // the late configuration of PCI features > > > > > > > > > > + // > > > > > > > > > > + Status =3D EnumerateOtherPciFeatures ( > > > > > > > > > > + RootBridge > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // finally start those PCI bridge port devices only > > > > > > > > > > + // > > > > > > > > > > + return StartPciRootPortsOnBridge ( > > > > > > > > > > + Controller, > > > > > > > > > > + RootBridge > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > /** > > > > > > > > > > Start to manage all the PCI devices it found previously under > > > > > > > > > > the entire host bridge. > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > > > > > index 8db1ebf8ec..0a56668380 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > > > > > @@ -1003,7 +1003,7 @@ PciHostBridgeAdjustAllocation ( > > > > > Status =3D RejectPciDevice (PciResNode->PciDev); > > > > > > > > > > if (Status =3D=3D EFI_SUCCESS) { > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_ERROR, > > > > > > > > > > + DEBUG_ERROR, > > > > > > > > > > "PciBus: [%02x|%02x|%02x] was rejected due to resource > > > > > confliction.\n", > > > > > > > > > > PciResNode->PciDev->BusNumber, PciResNode->PciDev- > > > > > >DeviceNumber, PciResNode->PciDev->FunctionNumber > > > > > > > > > > )); > > > > > > > > > > @@ -1746,7 +1746,7 @@ NotifyPhase ( > > > > > > > > > > > > > > > HostBridgeHandle =3D NULL; > > > > > > > > > > RootBridgeHandle =3D NULL; > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + if ( CheckPciPlatformProtocolInstall()) { > > > > > > > > > > // > > > > > > > > > > // Get Host Bridge Handle. > > > > > > > > > > // > > > > > > > > > > @@ -1770,42 +1770,11 @@ NotifyPhase ( > > > > > // > > > > > > > > > > // Call PlatformPci::PlatformNotify() if the protocol is pre= sent. > > > > > > > > > > // > > > > > > > > > > - gPciPlatformProtocol->PlatformNotify ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetEntry > > > > > > > > > > - ); > > > > > > > > > > - } else if (gPciOverrideProtocol !=3D NULL){ > > > > > > > > > > - // > > > > > > > > > > - // Get Host Bridge Handle. > > > > > > > > > > - // > > > > > > > > > > - PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHand= le); > > > > > > > > > > - > > > > > > > > > > - // > > > > > > > > > > - // Get the rootbridge Io protocol to find the host bridge ha= ndle > > > > > > > > > > - // > > > > > > > > > > - Status =3D gBS->HandleProtocol ( > > > > > > > > > > - RootBridgeHandle, > > > > > > > > > > - &gEfiPciRootBridgeIoProtocolGuid, > > > > > > > > > > - (VOID **) &PciRootBridgeIo > > > > > > > > > > - ); > > > > > > > > > > - > > > > > > > > > > - if (EFI_ERROR (Status)) { > > > > > > > > > > - return EFI_NOT_FOUND; > > > > > > > > > > - } > > > > > > > > > > - > > > > > > > > > > - HostBridgeHandle =3D PciRootBridgeIo->ParentHandle; > > > > > > > > > > - > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PhaseNotify() if the protocol is presen= t. > > > > > > > > > > - // > > > > > > > > > > - gPciOverrideProtocol->PlatformNotify ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetEntry > > > > > > > > > > - ); > > > > > > > > > > + PciPlatformNotifyPhase ( > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ChipsetEntry > > > > > > > > > > + ); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > Status =3D PciResAlloc->NotifyPhase ( > > > > > > > > > > @@ -1813,27 +1782,15 @@ NotifyPhase ( > > > > > Phase > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + if ( CheckPciPlatformProtocolInstall()) { > > > > > > > > > > // > > > > > > > > > > // Call PlatformPci::PlatformNotify() if the protocol is pre= sent. > > > > > > > > > > // > > > > > > > > > > - gPciPlatformProtocol->PlatformNotify ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetExit > > > > > > > > > > - ); > > > > > > > > > > - > > > > > > > > > > - } else if (gPciOverrideProtocol !=3D NULL) { > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PhaseNotify() if the protocol is presen= t. > > > > > > > > > > - // > > > > > > > > > > - gPciOverrideProtocol->PlatformNotify ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetExit > > > > > > > > > > - ); > > > > > > > > > > + PciPlatformNotifyPhase ( > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ChipsetExit > > > > > > > > > > + ); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > return Status; > > > > > > > > > > @@ -1914,31 +1871,16 @@ PreprocessController ( > > > > > RootBridgePciAddress.Bus =3D Bus; > > > > > > > > > > RootBridgePciAddress.ExtendedRegister =3D 0; > > > > > > > > > > > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > - // > > > > > > > > > > - gPciPlatformProtocol->PlatformPrepController ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - RootBridgeHandle, > > > > > > > > > > - RootBridgePciAddress, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetEntry > > > > > > > > > > - ); > > > > > > > > > > - } else if (gPciOverrideProtocol !=3D NULL) { > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > - // > > > > > > > > > > - gPciOverrideProtocol->PlatformPrepController ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - RootBridgeHandle, > > > > > > > > > > - RootBridgePciAddress, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetEntry > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is prese= nt. > > > > > > > > > > + // > > > > > > > > > > + PciPlatformPreprocessController ( > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ChipsetEntry > > > > > > > > > > + ); > > > > > > > > > > > > > > > > > > > > Status =3D PciResAlloc->PreprocessController ( > > > > > > > > > > PciResAlloc, > > > > > > > > > > @@ -1947,31 +1889,16 @@ PreprocessController ( > > > > > Phase > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > - // > > > > > > > > > > - gPciPlatformProtocol->PlatformPrepController ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - RootBridgeHandle, > > > > > > > > > > - RootBridgePciAddress, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetExit > > > > > > > > > > - ); > > > > > > > > > > - } else if (gPciOverrideProtocol !=3D NULL) { > > > > > > > > > > - // > > > > > > > > > > - // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > - // > > > > > > > > > > - gPciOverrideProtocol->PlatformPrepController ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - HostBridgeHandle, > > > > > > > > > > - RootBridgeHandle, > > > > > > > > > > - RootBridgePciAddress, > > > > > > > > > > - Phase, > > > > > > > > > > - ChipsetExit > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is prese= nt. > > > > > > > > > > + // > > > > > > > > > > + PciPlatformPreprocessController ( > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ChipsetExit > > > > > > > > > > + ); > > > > > > > > > > > > > > > > > > > > return EFI_SUCCESS; > > > > > > > > > > } > > > > > > > > > > diff --git > > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > > > > index c7eafff593..2343702154 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > > > > @@ -230,7 +230,7 @@ PciSearchDevice ( > > > > > PciIoDevice =3D NULL; > > > > > > > > > > > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > "PciBus: Discovered %s @ [%02x|%02x|%02x]\n", > > > > > > > > > > IS_PCI_BRIDGE (Pci) ? L"PPB" : > > > > > > > > > > IS_CARDBUS_BRIDGE (Pci) ? L"P2C" : > > > > > > > > > > @@ -397,7 +397,7 @@ DumpPpbPaddingResource ( > > > > > > > > > > > > > > > if ((Type !=3D PciBarTypeUnknown) && ((ResourceType =3D=3D > > > > > PciBarTypeUnknown) || (ResourceType =3D=3D Type))) { > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " Padding: Type =3D %s; Alignment =3D 0x%lx;\tLength = =3D 0x%lx\n", > > > > > > > > > > mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor- > > >AddrLen > > > > > > > > > > )); > > > > > > > > > > @@ -424,7 +424,7 @@ DumpPciBars ( > > > > > } > > > > > > > > > > > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " BAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D= 0x%lx;\tOffset > > =3D > > > > > 0x%02x\n", > > > > > > > > > > Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType= , > > > > > PciBarTypeMaxType)], > > > > > > > > > > PciIoDevice->PciBar[Index].Alignment, PciIoDevice- > > > > > >PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset > > > > > > > > > > @@ -437,13 +437,13 @@ DumpPciBars ( > > > > > } > > > > > > > > > > > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " VFBAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D > > 0x%lx;\tOffset =3D > > > > > 0x%02x\n", > > > > > > > > > > Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarTy= pe, > > > > > PciBarTypeMaxType)], > > > > > > > > > > PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice- > > > > > >VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset > > > > > > > > > > )); > > > > > > > > > > } > > > > > > > > > > - DEBUG ((EFI_D_INFO, "\n")); > > > > > > > > > > + DEBUG ((DEBUG_INFO, "\n")); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > /** > > > > > > > > > > @@ -1903,7 +1903,7 @@ PciParseBar ( > > > > > // Fix the length to support some special 64 bit BAR > > > > > > > > > > // > > > > > > > > > > if (Value =3D=3D 0) { > > > > > > > > > > - DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit= of > > MEM64 > > > > > BAR returns 0, change to 0xFFFFFFFF.\n")); > > > > > > > > > > + DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit= of > > > > MEM64 > > > > > BAR returns 0, change to 0xFFFFFFFF.\n")); > > > > > > > > > > Value =3D (UINT32) -1; > > > > > > > > > > } else { > > > > > > > > > > Value |=3D ((UINT32)(-1) << HighBitSet32 (Value)); > > > > > > > > > > @@ -2153,7 +2153,17 @@ CreatePciIoDevice ( > > > > > NULL > > > > > > > > > > ); > > > > > > > > > > if (!EFI_ERROR (Status)) { > > > > > > > > > > - PciIoDevice->IsPciExp =3D TRUE; > > > > > > > > > > + PciIoDevice->IsPciExp =3D TRUE; > > > > > > > > > > + // > > > > > > > > > > + // read the PCI device's entire PCI Express Capability struc= ture > > > > > > > > > > + // > > > > > > > > > > + PciIo->Pci.Read ( > > > > > > > > > > + PciIo, > > > > > > > > > > + EfiPciIoWidthUint8, > > > > > > > > > > + PciIoDevice->PciExpressCapabilityOffset, > > > > > > > > > > + sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8= ), > > > > > > > > > > + &PciIoDevice->PciExpStruct > > > > > > > > > > + ); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > if (PcdGetBool (PcdAriSupport)) { > > > > > > > > > > @@ -2206,7 +2216,7 @@ CreatePciIoDevice ( > > > > > &Data32 > > > > > > > > > > ); > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n"= , > > > > > > > > > > Bridge->BusNumber, > > > > > > > > > > Bridge->DeviceNumber, > > > > > > > > > > @@ -2215,7 +2225,7 @@ CreatePciIoDevice ( > > > > > } > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > - DEBUG ((EFI_D_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDev= ice- > > > > > >AriCapabilityOffset)); > > > > > > > > > > + DEBUG ((DEBUG_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDev= ice- > > > > > >AriCapabilityOffset)); > > > > > > > > > > } > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > @@ -2325,12 +2335,12 @@ CreatePciIoDevice ( > > > > > PciIoDevice->ReservedBusNum =3D (UINT16)(EFI_PCI_BUS_OF_RI= D > > > > (LastVF) > > > > > - Bus + 1); > > > > > > > > > > > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " SR-IOV: SupportedPageSize =3D 0x%x; SystemPageSize =3D= 0x%x; > > > > > FirstVFOffset =3D 0x%x;\n", > > > > > > > > > > SupportedPageSize, PciIoDevice->SystemPageSize >> 12, > > FirstVFOffset > > > > > > > > > > )); > > > > > > > > > > DEBUG (( > > > > > > > > > > - EFI_D_INFO, > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > " InitialVFs =3D 0x%x; ReservedBusNum =3D 0x%x; = CapOffset =3D > > 0x%x\n", > > > > > > > > > > PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, > > PciIoDevice- > > > > > >SrIovCapabilityOffset > > > > > > > > > > )); > > > > > > > > > > @@ -2345,7 +2355,7 @@ CreatePciIoDevice ( > > > > > NULL > > > > > > > > > > ); > > > > > > > > > > if (!EFI_ERROR (Status)) { > > > > > > > > > > - DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIo= Device- > > > > > >MrIovCapabilityOffset)); > > > > > > > > > > + DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset =3D 0x%x\n", > > PciIoDevice- > > > > > >MrIovCapabilityOffset)); > > > > > > > > > > } > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > > > > > new file mode 100644 > > > > > index 0000000000..0819da6536 > > > > > --- /dev/null > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > > > > > @@ -0,0 +1,1601 @@ > > > > > +/** @file > > > > > > > > > > + PCI standard feature support functions implementation for PCI = Bus > > > > > module.. > > > > > > > > > > + > > > > > > > > > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > > > > > > > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > + > > > > > > > > > > +#include "PciFeatureSupport.h" > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + A gobal pointer to PRIMARY_ROOT_PORT_NODE buffer to track all > > the > > > > > primary physical > > > > > > > > > > + PCI Root Ports (PCI Controllers) for a given PCI Root Bridge i= nstance > > while > > > > > > > > > > + enumerating to configure the PCI features > > > > > > > > > > +**/ > > > > > > > > > > +PRIMARY_ROOT_PORT_NODE *mPrimaryRootPortLis= t; > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + A gobal pointer to OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > buffer > > > > > all the PCI > > > > > > > > > > + Feature configuration Table nodes to pair against each of the > > > > > PRIMARY_ROOT_PORT_NODE > > > > > > > > > > + buffer nodes. Each node of these is used to align all the PCI = devices > > > > > originating > > > > > > > > > > + from the PCI Root Port devices of a PCI Root Bridge instance > > > > > > > > > > +**/ > > > > > > > > > > +OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *mPciFeaturesConfigurationTableInstances; > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + A global pointer to > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST, > > > > > which stores all > > > > > > > > > > + the PCI Root Bridge instances that are enumerated for the othe= r PCI > > > > > features, > > > > > > > > > > + like MaxPayloadSize & MaxReadReqSize; during the the Start() > > interface > > > > of > > > > > the > > > > > > > > > > + driver binding protocol. The records pointed by this pointer w= ould be > > > > > destroyed > > > > > > > > > > + when the DXE core invokes the Stop() interface. > > > > > > > > > > +**/ > > > > > > > > > > +PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > > > > > *mPciFeaturesConfigurationCompletionList =3D NULL; > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Main routine to indicate platform selection of any of the othe= r PCI > > > > features > > > > > > > > > > + to be configured by this driver > > > > > > > > > > + > > > > > > > > > > + @retval TRUE platform has selected the other PCI features t= o be > > > > > configured > > > > > > > > > > + FALSE platform has not selected any of the other PCI= features > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckOtherPciFeaturesPcd ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + return PcdGet32 ( PcdOtherPciFeatures) ? TRUE : FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Main routine to indicate whether the platform has selected the > > > > > Max_Payload_Size > > > > > > > > > > + PCI feature to be configured by this driver > > > > > > > > > > + > > > > > > > > > > + @retval TRUE platform has selected the Max_Payload_Size to = be > > > > > configured > > > > > > > > > > + FALSE platform has not selected this feature > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMaxPayloadSize ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + return (PcdGet32 ( PcdOtherPciFeatures) & > > > > > PCI_FEATURE_SUPPORT_FLAG_MPS) ? TRUE : FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Main routine to indicate whether the platform has selected the > > > > > Max_Read_Req_Size > > > > > > > > > > + PCI feature to be configured by this driver > > > > > > > > > > + > > > > > > > > > > + @retval TRUE platform has selected the Max_Read_Req_Size to= be > > > > > configured > > > > > > > > > > + FALSE platform has not selected this feature > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMaxReadReqSize ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + return (PcdGet32 ( PcdOtherPciFeatures) & > > > > > PCI_FEATURE_SUPPORT_FLAG_MRRS) ? TRUE : FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine which determines whether the given PCI Root Bri= dge > > > > > instance > > > > > > > > > > + record already exist. This routine shall help avoid duplicate = record > > > > creation > > > > > > > > > > + in case of re-enumeration of PCI configuation features. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE= for the > > Root > > > > > Bridge > > > > > > > > > > + @param PciFeatureConfigRecord A pointer to a pointer for typ= e > > > > > > > > > > + PCI_FEATURE_CONFIGURATION_COMP= LETION_LIST > > > > > > > > > > + record, Use to return the spec= ific record. > > > > > > > > > > + > > > > > > > > > > + @retval TRUE Record already exist > > > > > > > > > > + FALSE Record does not exist for the = given PCI Root > > Bridge > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckPciFeatureConfigurationRecordExist ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > + OUT PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > > > > > **PciFeatureConfigRecord > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( mPciFeaturesConfigurationCompletionList) { > > > > > > > > > > + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink; > > > > > > > > > > + > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK > > (Link); > > > > > > > > > > + if ( Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { > > > > > > > > > > + *PciFeatureConfigRecord =3D Temp; > > > > > > > > > > + return TRUE; > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while (Link !=3D &mPciFeaturesConfigurationCompletionList- > > > > > >RootBridgeLink); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // not found on the PCI feature configuration completion list > > > > > > > > > > + // > > > > > > > > > > + *PciFeatureConfigRecord =3D NULL; > > > > > > > > > > + return FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine is primarily to avoid multiple configuration of P= CI features > > > > > > > > > > + to the same PCI Root Bridge due to EDK2 core's ConnectControll= er > > calls > > > > on > > > > > > > > > > + all the EFI handles. This routine also provide re-enumeration = of the > > PCI > > > > > > > > > > + features on the same PCI Root Bridge based on the policy of > > > > > ReEnumeratePciFeatureConfiguration > > > > > > > > > > + of the PCI_FEATURE_CONFIGURATION_COMPLETION_LIST. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE= for the > > Root > > > > > Bridge > > > > > > > > > > + > > > > > > > > > > + @retval TRUE PCI Feature configuration requ= ired for the PCI > > > > > > > > > > + Root Bridge > > > > > > > > > > + FALSE PCI Feature configuration is n= ot required to be > > > > > > > > > > + re-enumerated for the PCI Root= Bridge > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckPciFeaturesConfigurationRequired ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( mPciFeaturesConfigurationCompletionList) { > > > > > > > > > > + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink; > > > > > > > > > > + > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK > > (Link); > > > > > > > > > > + if ( Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { > > > > > > > > > > + return Temp->ReEnumeratePciFeatureConfiguration; > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while (Link !=3D &mPciFeaturesConfigurationCompletionList- > > > > > >RootBridgeLink); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // not found on the PCI feature configuration completion list,= return > > as > > > > > required > > > > > > > > > > + // > > > > > > > > > > + return TRUE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine finds the duplicate record if exist and assigns t= he re- > > > > > enumeration > > > > > > > > > > + requirement flag, as passed as input. It creates new record fo= r the > > PCI > > > > > Root > > > > > > > > > > + Bridge and appends the list after updating its re-enumeration = flag. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to PCI_IO_DEVICE of th= e Root > > > > Bridge > > > > > > > > > > + @param ReEnumerationRequired A BOOLEAN for recording the re- > > > > > enumeration requirement > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS new record inserted into the lis= t or > > updated > > > > the > > > > > > > > > > + existing record > > > > > > > > > > + EFI_INVALID_PARAMETER Unexpected error as > > > > > CheckPciFeatureConfigurationRecordExist > > > > > > > > > > + reports as record exist but does= not return its pointer > > > > > > > > > > + EFI_OUT_OF_RESOURCES Not able to create PCI features > > > > configuratin > > > > > complete > > > > > > > > > > + record for the RootBridge > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +AddRootBridgeInPciFeaturesConfigCompletionList ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > + IN BOOLEAN ReEnumerationRequired > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( CheckPciFeatureConfigurationRecordExist ( RootBridge, &Te= mp)) > > { > > > > > > > > > > + // > > > > > > > > > > + // this PCI Root Bridge record already exist; it may have be= en re- > > > > > enumerated > > > > > > > > > > + // hence just update its enumeration required flag again to = exit > > > > > > > > > > + // > > > > > > > > > > + if ( Temp) { > > > > > > > > > > + Temp->ReEnumeratePciFeatureConfiguration =3D > > > > > ReEnumerationRequired; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // PCI feature configuration complete record reported as e= xist and > > no > > > > > > > > > > + // record pointer returned > > > > > > > > > > + // > > > > > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + } else { > > > > > > > > > > + > > > > > > > > > > + Temp =3D AllocateZeroPool ( sizeof > > > > > ( PCI_FEATURE_CONFIGURATION_COMPLETION_LIST)); > > > > > > > > > > + if ( !Temp) { > > > > > > > > > > + return EFI_OUT_OF_RESOURCES; > > > > > > > > > > + } > > > > > > > > > > + Temp->Signature =3D > > > > > PCI_FEATURE_CONFIGURATION_SIGNATURE; > > > > > > > > > > + Temp->RootBridgeHandle =3D RootBridge->Ha= ndle; > > > > > > > > > > + Temp->ReEnumeratePciFeatureConfiguration =3D > > > > ReEnumerationRequired; > > > > > > > > > > + if ( mPciFeaturesConfigurationCompletionList) { > > > > > > > > > > + InsertTailList ( &mPciFeaturesConfigurationCompletionList- > > > > > >RootBridgeLink, > > > > > > > > > > + &Temp->RootBridgeLink); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // init the very first node of the Root Bridge > > > > > > > > > > + // > > > > > > > > > > + mPciFeaturesConfigurationCompletionList =3D Temp; > > > > > > > > > > + InitializeListHead ( &mPciFeaturesConfigurationCompletionL= ist- > > > > > >RootBridgeLink); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Free up memory alloted for the primary physical PCI Root ports= of the > > > > PCI > > > > > Root > > > > > > > > > > + Bridge instance. Free up all the nodes of type > > > > > PRIMARY_ROOT_PORT_NODE. > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +DestroyPrimaryRootPortNodes () > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( mPrimaryRootPortList) { > > > > > > > > > > + Link =3D &mPrimaryRootPortList->NeighborRootPort; > > > > > > > > > > + > > > > > > > > > > + if ( IsListEmpty ( Link)) { > > > > > > > > > > + FreePool ( mPrimaryRootPortList); > > > > > > > > > > + } else { > > > > > > > > > > + do { > > > > > > > > > > + if ( Link->ForwardLink !=3D &mPrimaryRootPortList- > > >NeighborRootPort) > > > > { > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } > > > > > > > > > > + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK ( Link); > > > > > > > > > > + Link =3D RemoveEntryList ( Link); > > > > > > > > > > + FreePool ( Temp); > > > > > > > > > > + } while ( !IsListEmpty ( Link)); > > > > > > > > > > + FreePool ( mPrimaryRootPortList); > > > > > > > > > > + } > > > > > > > > > > + mPrimaryRootPortList =3D NULL; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Free up the memory allocated for temporarily maintaining the P= CI > > > > feature > > > > > > > > > > + configuration table for all the nodes of the primary PCI Root = port. > > > > > > > > > > + Free up memory alloted for > > > > > OTHER_PCI_FEATURES_CONFIGURATION_TABLE. > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +ErasePciFeaturesConfigurationTable ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + if ( mPciFeaturesConfigurationTableInstances) { > > > > > > > > > > + FreePool ( mPciFeaturesConfigurationTableInstances); > > > > > > > > > > + } > > > > > > > > > > + mPciFeaturesConfigurationTableInstances =3D NULL; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Routine meant for initializing any global variables used. It p= rimarily > > cleans > > > > > > > > > > + up the internal data structure memory allocated for the previo= us PCI > > > > Root > > > > > Bridge > > > > > > > > > > + instance. This should be the first routine to call for any vir= tual PCI > > Root > > > > > > > > > > + Bridge instance. > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +SetupPciFeaturesConfigurationDefaults () > > > > > > > > > > +{ > > > > > > > > > > + // > > > > > > > > > > + // delete the primary root port list > > > > > > > > > > + // > > > > > > > > > > + if (mPrimaryRootPortList) { > > > > > > > > > > + DestroyPrimaryRootPortNodes (); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( mPciFeaturesConfigurationTableInstances) { > > > > > > > > > > + ErasePciFeaturesConfigurationTable (); > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine to determine whether the PCI device is a physic= al root > > > > port > > > > > > > > > > + recorded in the list. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_I= O_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval TRUE The PCI device instanc= e is a primary > > > > > > > > > > + primary physical PCI R= oot Port > > > > > > > > > > + FALSE Not a primary physical= PCI Root port > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckRootBridgePrimaryPort ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( !mPrimaryRootPortList) { > > > > > > > > > > + return FALSE; > > > > > > > > > > + } > > > > > > > > > > + Link =3D &mPrimaryRootPortList->NeighborRootPort; > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK ( Link); > > > > > > > > > > + if ( Temp->RootBridgeHandle =3D=3D PciDevice->Parent->Handle > > > > > > > > > > + && Temp->RootPortHandle =3D=3D PciDevice->Handle) { > > > > > > > > > > + // > > > > > > > > > > + // the given PCI device is the primary root port of the Ro= ot Bridge > > > > > controller > > > > > > > > > > + // > > > > > > > > > > + return TRUE; > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while ( Link !=3D &mPrimaryRootPortList->NeighborRootPort); > > > > > > > > > > + // > > > > > > > > > > + // the given PCI device is not the primary root port of the Br= idge > > > > controller > > > > > > > > > > + // > > > > > > > > > > + return FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Main routine to determine the child PCI devices of a physical = PCI > > bridge > > > > > device > > > > > > > > > > + and group them under a common internal PCI features Configurat= ion > > > > table. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_I= O_DEVICE. > > > > > > > > > > + @param PciFeaturesConfigTable A pointer to a pointer= to the > > > > > > > > > > + > OTHER_PCI_FEATURES_CONFIGURATION_TABLE. > > > > > > > > > > + Returns NULL in case o= f RCiEP or the PCI > > > > > > > > > > + device does match with= any of the physical > > > > > > > > > > + Root ports, or it does= not belong to any > > > > > > > > > > + Root port's PCU bus ra= nge (not a child) > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS able to determine the = PCI feature > > > > > > > > > > + configuration table. F= or RCiEP since > > > > > > > > > > + since it is not prepar= ed. > > > > > > > > > > + EFI_NOT_FOUND the PCI feature config= uration table > > does > > > > > > > > > > + not exist as the PCI p= hysical Bridge device > > > > > > > > > > + is not found for this = device's parent > > > > > > > > > > + Root Bridge instance > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPciFeaturesConfigurationTable ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice, > > > > > > > > > > + OUT OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > **PciFeaturesConfigTable > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( !mPrimaryRootPortList) { > > > > > > > > > > + *PciFeaturesConfigTable =3D NULL; > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // The PCI features configuration table is not built for RCiEP= , return > > NULL > > > > > > > > > > + // > > > > > > > > > > + if ( PciDevice->PciExpStruct.Capability.Bits.DevicePortType = =3D=3D \ > > > > > > > > > > + > > PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) > > > > > { > > > > > > > > > > + *PciFeaturesConfigTable =3D NULL; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + Link =3D &mPrimaryRootPortList->NeighborRootPort; > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK ( Link); > > > > > > > > > > + if ( Temp->RootBridgeHandle =3D=3D PciDevice->Parent->Handle > > > > > > > > > > + && Temp->RootPortHandle =3D=3D PciDevice->Handle) { > > > > > > > > > > + // > > > > > > > > > > + // the given PCI device is the primary root port of the Ro= ot Bridge > > > > > controller > > > > > > > > > > + // > > > > > > > > > > + *PciFeaturesConfigTable =3D Temp- > > > > >OtherPciFeaturesConfigurationTable; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // check this PCI device belongs to the primary root port = of the root > > > > > bridge > > > > > > > > > > + // > > > > > > > > > > + if ( PciDevice->BusNumber >=3D Temp->SecondaryBusStart > > > > > > > > > > + && PciDevice->BusNumber <=3D Temp->SecondaryBusEnd) { > > > > > > > > > > + *PciFeaturesConfigTable =3D Temp- > > > > >OtherPciFeaturesConfigurationTable; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while ( Link !=3D &mPrimaryRootPortList->NeighborRootPort); > > > > > > > > > > + // > > > > > > > > > > + // the PCI device must be RCiEP, does not belong to any primar= y root > > > > port > > > > > > > > > > + // > > > > > > > > > > + *PciFeaturesConfigTable =3D NULL; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + The helper routine to retrieve the PCI bus numbers from the PC= I > > Bridge > > > > or > > > > > Root > > > > > > > > > > + port device. Assumes the input PCI device has the PCI Type 1 > > > > configuration > > > > > header. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_I= O_DEVICE. > > > > > > > > > > + @param PrimaryBusNumber A pointer to return th= e PCI > > Priamry > > > > > > > > > > + Bus number. > > > > > > > > > > + @param SecondaryBusNumber A pointer to return th= e PCI > > > > > Secondary > > > > > > > > > > + Bus number. > > > > > > > > > > + @param SubordinateBusNumber A pointer to return th= e PCI > > > > > Subordinate > > > > > > > > > > + Bus number. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The data was read from the PCI d= evice. > > > > > > > > > > + @retval EFI_UNSUPPORTED The address range specified by O= ffset, > > > > > Width, and Count is not > > > > > > > > > > + valid for the PCI configuration = header of the PCI > device. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER input parameters provided to the > > > > read > > > > > operation were invalid. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPciRootPortBusAssigned ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice, > > > > > > > > > > + OUT UINT8 *PrimaryBusNumber, > > > > > > > > > > + OUT UINT8 *SecondaryBusNumbe= r, > > > > > > > > > > + OUT UINT8 *SubordinateBusNum= ber > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + UINT32 RootPortBusAssigne= d; > > > > > > > > > > + > > > > > > > > > > + Status =3D PciDevice->PciIo.Pci.Read ( > > > > > > > > > > + &PciDevice->PciIo, > > > > > > > > > > + EfiPciIoWidthUint32, > > > > > > > > > > + PCI_BRIDGE_PRIMARY_BUS_REGISTE= R_OFFSET, > > > > > > > > > > + 1, > > > > > > > > > > + &RootPortBusAssigned > > > > > > > > > > + ); > > > > > > > > > > + if ( !EFI_ERROR(Status)) { > > > > > > > > > > + if ( PrimaryBusNumber) { > > > > > > > > > > + *PrimaryBusNumber =3D (UINT8) (0xFF & RootPortBusAssigned)= ; > > > > > > > > > > + } > > > > > > > > > > + if ( SecondaryBusNumber) { > > > > > > > > > > + *SecondaryBusNumber =3D (UINT8)(0xFF & (RootPortBusAssigne= d >> > > 8)); > > > > > > > > > > + } > > > > > > > > > > + if ( SubordinateBusNumber) { > > > > > > > > > > + *SubordinateBusNumber =3D (UINT8)(0xFF & > > (RootPortBusAssigned >> > > > > > 16)); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine determines the existance of the child PCI device = for the > > > > given > > > > > > > > > > + PCI Root / Bridge Port device. Always assumes the input PCI de= vice is > > the > > > > > bridge > > > > > > > > > > + or PCI-PCI Bridge device. This routine should not be used with= PCI > > > > > endpoint device. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_I= O_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval TRUE child device exist > > > > > > > > > > + FALSE no child device > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +IsPciRootPortEmpty ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + UINT8 SecBus, > > > > > > > > > > + SubBus; > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_IO_DEVICE *NextPciDevice; > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // check secondary & suboridinate bus numbers for its endpoint > > device > > > > > > > > > > + // existance > > > > > > > > > > + // > > > > > > > > > > + Status =3D GetPciRootPortBusAssigned ( PciDevice, NULL, &SecBu= s, > > > > > &SubBus); > > > > > > > > > > + if ( !EFI_ERROR( Status)) { > > > > > > > > > > + Link =3D PciDevice->ChildList.ForwardLink; > > > > > > > > > > + if ( IsListEmpty ( Link)) { > > > > > > > > > > + // > > > > > > > > > > + // return as PCI Root port empty > > > > > > > > > > + // > > > > > > > > > > + DEBUG (( DEBUG_INFO, "RP empty,")); > > > > > > > > > > + return TRUE; > > > > > > > > > > + } > > > > > > > > > > + do { > > > > > > > > > > + NextPciDevice =3D PCI_IO_DEVICE_FROM_LINK ( Link); > > > > > > > > > > + DEBUG (( DEBUG_INFO, "dev@%x", NextPciDevice->BusNumber)); > > > > > > > > > > + > > > > > > > > > > + if ( NextPciDevice->BusNumber >=3D SecBus > > > > > > > > > > + && NextPciDevice->BusNumber <=3D SubBus) { > > > > > > > > > > + > > > > > > > > > > + return FALSE; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while ( Link !=3D &PciDevice->ChildList); > > > > > > > > > > + } else { > > > > > > > > > > + SecBus =3D SubBus =3D 0; > > > > > > > > > > + DEBUG (( DEBUG_ERROR, "unable to retrieve root port's bus ra= nge > > > > > assigned!!!")); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // return as PCI Root port empty > > > > > > > > > > + // > > > > > > > > > > + return TRUE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + The main routine which process the PCI feature Max_Payload_Siz= e as > > > > per > > > > > the > > > > > > > > > > + device-specific platform policy, as well as in complaince with= the PCI > > Base > > > > > > > > > > + specification Revision 4, that aligns the value for the entire= PCI > > heirarchy > > > > > > > > > > + starting from its physical PCI Root port / Bridge device. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_IO_= DEVICE. > > > > > > > > > > + @param PciConfigPhase for the PCI feature conf= iguration > > phases: > > > > > > > > > > + PciFeatureGetDevicePolic= y & > > PciFeatureSetupPhase > > > > > > > > > > + @param PciFeaturesConfigurationTable pointer to > > > > > OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS processing of PCI featur= e > > > > > Max_Payload_Size > > > > > > > > > > + is successful. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +ProcessMaxPayloadSize ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice, > > > > > > > > > > + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase, > > > > > > > > > > + IN OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *PciFeaturesConfigurationTable > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; > > > > > > > > > > + UINT8 MpsValue; > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > + PciDeviceCap.Uint32 =3D PciDevice- > > >PciExpStruct.DeviceCapability.Uint32; > > > > > > > > > > + > > > > > > > > > > + if ( PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { > > > > > > > > > > + if ( SetupMpsAsPerDeviceCapability ( PciDevice->SetupMPS)) > > > > > > > > > > + { > > > > > > > > > > + MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; > > > > > > > > > > + // > > > > > > > > > > + // no change to PCI Root ports without any endpoint device > > > > > > > > > > + // > > > > > > > > > > + if ( IS_PCI_BRIDGE ( &PciDevice->Pci) && > > > > > PciDeviceCap.Bits.MaxPayloadSize) { > > > > > > > > > > + if ( IsPciRootPortEmpty ( PciDevice)) { > > > > > > > > > > + MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > > > > > > + DEBUG (( DEBUG_INFO, "(reset RP MPS to min.)")); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } else { > > > > > > > > > > + MpsValue =3D TranslateMpsSetupValueToPci ( PciDevice- > > >SetupMPS); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // discard device policy override request if greater than PC= I device > > > > > capability > > > > > > > > > > + // > > > > > > > > > > + PciDevice->SetupMPS =3D > > > > MIN( (UINT8)PciDeviceCap.Bits.MaxPayloadSize, > > > > > MpsValue); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // align the MPS of the tree to the HCF with this device > > > > > > > > > > + // > > > > > > > > > > + if ( PciFeaturesConfigurationTable) { > > > > > > > > > > + MpsValue =3D PciFeaturesConfigurationTable->Max_Payload_Size= ; > > > > > > > > > > + > > > > > > > > > > + MpsValue =3D MIN ( PciDevice->SetupMPS, MpsValue); > > > > > > > > > > + PciDevice->SetupMPS =3D MIN ( PciDevice->SetupMPS, MpsValue)= ; > > > > > > > > > > + > > > > > > > > > > + if ( MpsValue !=3D PciFeaturesConfigurationTable->Max_Payloa= d_Size) > > { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "reset MPS of the tree to %d,", > > MpsValue)); > > > > > > > > > > + PciFeaturesConfigurationTable->Max_Payload_Size =3D MpsVal= ue; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + DEBUG (( DEBUG_INFO, > > > > > > > > > > + "Max_Payload_Size: %d [DevCap:%d],", > > > > > > > > > > + PciDevice->SetupMPS, PciDeviceCap.Bits.MaxPayloadSize > > > > > > > > > > + )); > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + The main routine which process the PCI feature Max_Read_Req_Si= ze > > as > > > > > per the > > > > > > > > > > + device-specific platform policy, as well as in complaince with= the PCI > > Base > > > > > > > > > > + specification Revision 4, that aligns the value for the entire= PCI > > heirarchy > > > > > > > > > > + starting from its physical PCI Root port / Bridge device. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_IO_= DEVICE. > > > > > > > > > > + @param PciConfigPhase for the PCI feature conf= iguration > > phases: > > > > > > > > > > + PciFeatureGetDevicePolic= y & > > PciFeatureSetupPhase > > > > > > > > > > + @param PciFeaturesConfigurationTable pointer to > > > > > OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS processing of PCI featur= e > > > > > Max_Read_Req_Size > > > > > > > > > > + is successful. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +ProcessMaxReadReqSize ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice, > > > > > > > > > > + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase, > > > > > > > > > > + IN OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *PciFeaturesConfigurationTable > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; > > > > > > > > > > + UINT8 MrrsValue; > > > > > > > > > > + > > > > > > > > > > + PciDeviceCap.Uint32 =3D PciDevice- > > >PciExpStruct.DeviceCapability.Uint32; > > > > > > > > > > + > > > > > > > > > > + if ( PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { > > > > > > > > > > + if ( SetupMrrsAsPerDeviceCapability ( PciDevice->SetupMRRS)) > > > > > > > > > > + { > > > > > > > > > > + // > > > > > > > > > > + // The maximum read request size is not the data packet si= ze of the > > > > TLP, > > > > > > > > > > + // but the memory read request size, and set to the functi= on as a > > > > > requestor > > > > > > > > > > + // to not exceed this limit. > > > > > > > > > > + // However, for the PCI device capable of isochronous traf= fic; this > > > > > memory read > > > > > > > > > > + // request size should not extend beyond the Max_Payload_S= ize. > > Thus, > > > > > in case if > > > > > > > > > > + // device policy return by platform indicates to set as pe= r device > > > > > capability > > > > > > > > > > + // than set as per Max_Payload_Size configuration value > > > > > > > > > > + // > > > > > > > > > > + if ( SetupMaxPayloadSize()) { > > > > > > > > > > + MrrsValue =3D PciDevice->SetupMPS; > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // in case this driver is not required to configure the > > > > Max_Payload_Size > > > > > > > > > > + // than consider programming HCF of the device capabilit= y's > > > > > Max_Payload_Size > > > > > > > > > > + // in this PCI hierarchy; thus making this an implementa= tion > > specific > > > > > feature > > > > > > > > > > + // which the platform should avoid. For better results, = the > > platform > > > > > should > > > > > > > > > > + // make both the Max_Payload_Size & Max_Read_Request_Siz= e > > to > > > > be > > > > > configured > > > > > > > > > > + // by this driver > > > > > > > > > > + // > > > > > > > > > > + MrrsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; > > > > > > > > > > + } > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // override as per platform based device policy > > > > > > > > > > + // > > > > > > > > > > + MrrsValue =3D TranslateMrrsSetupValueToPci ( PciDevice- > > >SetupMRRS); > > > > > > > > > > + // > > > > > > > > > > + // align this device's Max_Read_Request_Size value to the = entire > > PCI > > > > > tree > > > > > > > > > > + // > > > > > > > > > > + if ( PciFeaturesConfigurationTable) { > > > > > > > > > > + if ( !PciFeaturesConfigurationTable- > > >Lock_Max_Read_Request_Size) > > > > { > > > > > > > > > > + PciFeaturesConfigurationTable->Lock_Max_Read_Request_S= ize > > =3D > > > > > TRUE; > > > > > > > > > > + PciFeaturesConfigurationTable->Max_Read_Request_Size = =3D > > > > > MrrsValue; > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // in case of another user enforced value of MRRS with= in the > > same > > > > > tree, > > > > > > > > > > + // pick the smallest between the locked value and this= value; to > > set > > > > > > > > > > + // across entire PCI tree nodes > > > > > > > > > > + // > > > > > > > > > > + MrrsValue =3D MIN ( > > > > > > > > > > + MrrsValue, > > > > > > > > > > + PciFeaturesConfigurationTable->Max_Read_= Request_Size > > > > > > > > > > + ); > > > > > > > > > > + PciFeaturesConfigurationTable->Max_Read_Request_Size = =3D > > > > > MrrsValue; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // align this device's Max_Read_Request_Size to derived > > configuration > > > > > value > > > > > > > > > > + // > > > > > > > > > > + PciDevice->SetupMRRS =3D MrrsValue; > > > > > > > > > > + > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // align the Max_Read_Request_Size of the PCI tree based on 3 > > > > conditions: > > > > > > > > > > + // first, if user defines MRRS for any one PCI device in the t= ree than > > align > > > > > > > > > > + // all the devices in the PCI tree. > > > > > > > > > > + // second, if user override is not define for this PCI tree th= an setup > > the > > > > > MRRS > > > > > > > > > > + // based on MPS value of the tree to meet the criteria for the > > > > isochronous > > > > > > > > > > + // traffic. > > > > > > > > > > + // third, if no user override, or platform firmware policy has= not > > selected > > > > > > > > > > + // this PCI bus driver to configure the MPS; than configure th= e MRRS > > to a > > > > > > > > > > + // highest common value of PCI device capability for the MPS f= ound > > > > among > > > > > all > > > > > > > > > > + // the PCI devices in this tree > > > > > > > > > > + // > > > > > > > > > > + if ( PciFeaturesConfigurationTable) { > > > > > > > > > > + if ( PciFeaturesConfigurationTable->Lock_Max_Read_Request_Si= ze) > > { > > > > > > > > > > + PciDevice->SetupMRRS =3D PciFeaturesConfigurationTable- > > > > > >Max_Read_Request_Size; > > > > > > > > > > + } else { > > > > > > > > > > + if ( SetupMaxPayloadSize()) { > > > > > > > > > > + PciDevice->SetupMRRS =3D PciDevice->SetupMPS; > > > > > > > > > > + } else { > > > > > > > > > > + PciDevice->SetupMRRS =3D MIN ( > > > > > > > > > > + PciDevice->SetupMRRS, > > > > > > > > > > + PciFeaturesConfigurationTable- > > > > >Max_Read_Request_Size > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + PciFeaturesConfigurationTable->Max_Read_Request_Size =3D > > > > PciDevice- > > > > > >SetupMRRS; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + DEBUG (( DEBUG_INFO, "Max_Read_Request_Size: %d\n", > > PciDevice- > > > > > >SetupMRRS)); > > > > > > > > > > + > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Overrides the PCI Device Control register MaxPayloadSize regis= ter > > field; > > > > if > > > > > > > > > > + the hardware value is different than the intended value. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_IO_DEVICE i= nstance. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The data was read from or writte= n to the > > PCI > > > > > device. > > > > > > > > > > + @retval EFI_UNSUPPORTED The address range specified by O= ffset, > > > > > Width, and Count is not > > > > > > > > > > + valid for the PCI configuration = header of the PCI > > > controller. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is inval= id. > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +OverrideMaxPayloadSize ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > > > > > > > > > > + UINT32 Offset; > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + PcieDev.Uint16 =3D 0; > > > > > > > > > > + Offset =3D PciDevice->PciExpressCapabilityOffset + > > > > > > > > > > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > > > > > > > > > > + Status =3D PciDevice->PciIo.Pci.Read ( > > > > > > > > > > + &PciDevice->PciIo, > > > > > > > > > > + EfiPciIoWidthUint16, > > > > > > > > > > + Offset, > > > > > > > > > > + 1, > > > > > > > > > > + &PcieDev.Uint16 > > > > > > > > > > + ); > > > > > > > > > > + if ( EFI_ERROR(Status)){ > > > > > > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > (0x%x) > > > > > read error!", > > > > > > > > > > + Offset > > > > > > > > > > + )); > > > > > > > > > > + return Status; > > > > > > > > > > + } > > > > > > > > > > + if ( PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) { > > > > > > > > > > + PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS; > > > > > > > > > > + DEBUG (( DEBUG_INFO, "Max_Payload_Size=3D%d,", PciDevice- > > > > > >SetupMPS)); > > > > > > > > > > + > > > > > > > > > > + Status =3D PciDevice->PciIo.Pci.Write ( > > > > > > > > > > + &PciDevice->PciIo, > > > > > > > > > > + EfiPciIoWidthUint16, > > > > > > > > > > + Offset, > > > > > > > > > > + 1, > > > > > > > > > > + &PcieDev.Uint16 > > > > > > > > > > + ); > > > > > > > > > > + if ( !EFI_ERROR(Status)) { > > > > > > > > > > + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.U= int16; > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > (0x%x) > > > > > write error!", > > > > > > > > > > + Offset > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "No write of Max_Payload_Size=3D%d,", > > > > PciDevice- > > > > > >SetupMPS)); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Overrides the PCI Device Control register MaxPayloadSize regis= ter > > field; > > > > if > > > > > > > > > > + the hardware value is different than the intended value. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to the PCI_IO_DEVICE i= nstance. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The data was read from or writte= n to the > > PCI > > > > > controller. > > > > > > > > > > + @retval EFI_UNSUPPORTED The address range specified by O= ffset, > > > > > Width, and Count is not > > > > > > > > > > + valid for the PCI configuration = header of the PCI > > > controller. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is inval= id. > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +OverrideMaxReadReqSize ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > > > > > > > > > > + UINT32 Offset; > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + PcieDev.Uint16 =3D 0; > > > > > > > > > > + Offset =3D PciDevice->PciExpressCapabilityOffset + > > > > > > > > > > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > > > > > > > > > > + Status =3D PciDevice->PciIo.Pci.Read ( > > > > > > > > > > + &PciDevice->PciIo, > > > > > > > > > > + EfiPciIoWidthUint16, > > > > > > > > > > + Offset, > > > > > > > > > > + 1, > > > > > > > > > > + &PcieDev.Uint16 > > > > > > > > > > + ); > > > > > > > > > > + if ( EFI_ERROR(Status)){ > > > > > > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > (0x%x) > > > > > read error!", > > > > > > > > > > + Offset > > > > > > > > > > + )); > > > > > > > > > > + return Status; > > > > > > > > > > + } > > > > > > > > > > + if ( PcieDev.Bits.MaxReadRequestSize !=3D PciDevice->SetupMRRS= ) { > > > > > > > > > > + PcieDev.Bits.MaxReadRequestSize =3D PciDevice->SetupMRRS; > > > > > > > > > > + DEBUG (( DEBUG_INFO, "Max_Read_Request_Size: %d\n", > > PciDevice- > > > > > >SetupMRRS)); > > > > > > > > > > + > > > > > > > > > > + Status =3D PciDevice->PciIo.Pci.Write ( > > > > > > > > > > + &PciDevice->PciIo, > > > > > > > > > > + EfiPciIoWidthUint16, > > > > > > > > > > + Offset, > > > > > > > > > > + 1, > > > > > > > > > > + &PcieDev.Uint16 > > > > > > > > > > + ); > > > > > > > > > > + if ( !EFI_ERROR(Status)) { > > > > > > > > > > + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.U= int16; > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > (0x%x) > > > > > write error!", > > > > > > > > > > + Offset > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "No write of > > Max_Read_Request_Size=3D%d\n", > > > > > PciDevice->SetupMRRS)); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + helper routine to dump the PCIe Device Port Type > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +DumpDevicePortType ( > > > > > > > > > > + IN UINT8 DevicePortType > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + switch ( DevicePortType){ > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCIe endpoint found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_ROOT_PORT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCIe Root Port found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n")= ); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case > > > > > PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "RCiEP found\n")); > > > > > > > > > > + break; > > > > > > > > > > + case > > PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR: > > > > > > > > > > + DEBUG (( DEBUG_INFO, "RC Event Collector found\n")); > > > > > > > > > > + break; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Process each PCI device as per the pltaform and device-specif= ic > > policy. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS processing each PCI feature as p= er policy > > > > > defined > > > > > > > > > > + was successful. > > > > > > > > > > + **/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +SetupDevicePciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice, > > > > > > > > > > + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + PCI_REG_PCIE_CAPABILITY PcieCap; > > > > > > > > > > + OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *OtherPciFeaturesConfigTable; > > > > > > > > > > + > > > > > > > > > > + PcieCap.Uint16 =3D PciDevice->PciExpStruct.Capability.Uint16; > > > > > > > > > > + DumpDevicePortType ( (UINT8)PcieCap.Bits.DevicePortType); > > > > > > > > > > + > > > > > > > > > > + OtherPciFeaturesConfigTable =3D NULL; > > > > > > > > > > + Status =3D GetPciFeaturesConfigurationTable ( PciDevice, > > > > > &OtherPciFeaturesConfigTable); > > > > > > > > > > + if ( EFI_ERROR( Status)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + EFI_D_WARN, "No primary root port found in these root br= idge > > > > > nodes!\n" > > > > > > > > > > + )); > > > > > > > > > > + } else if ( !OtherPciFeaturesConfigTable) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "No PCI features config. table for this devi= ce!\n" > > > > > > > > > > + )); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "using PCI features config. table ID: %d\n", > > > > > > > > > > + OtherPciFeaturesConfigTable->ID > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { > > > > > > > > > > + Status =3D GetPciDevicePlatformPolicy ( PciDevice); > > > > > > > > > > + if ( EFI_ERROR(Status)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, "Error in obtaining PCI device policy!!!\= n" > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( SetupMaxPayloadSize ()) { > > > > > > > > > > + Status =3D ProcessMaxPayloadSize ( > > > > > > > > > > + PciDevice, > > > > > > > > > > + PciConfigPhase, > > > > > > > > > > + OtherPciFeaturesConfigTable > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // implementation specific rule:- the MRRS of any PCI device s= hould > > be > > > > > processed > > > > > > > > > > + // only after the MPS is processed for that device > > > > > > > > > > + // > > > > > > > > > > + if ( SetupMaxReadReqSize ()) { > > > > > > > > > > + Status =3D ProcessMaxReadReqSize ( > > > > > > > > > > + PciDevice, > > > > > > > > > > + PciConfigPhase, > > > > > > > > > > + OtherPciFeaturesConfigTable > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Traverse all the nodes from the root bridge or PCI-PCI bridge = instance, > > to > > > > > > > > > > + configure the PCI features as per the device-specific platform= policy, > > and > > > > > > > > > > + as per the device capability, as applicable. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS Traversing all the nodes of the = root bridge > > > > > > > > > > + instances were successfull. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +SetupPciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_IO_DEVICE *Device; > > > > > > > > > > + > > > > > > > > > > + for ( Link =3D RootBridge->ChildList.ForwardLink > > > > > > > > > > + ; Link !=3D &RootBridge->ChildList > > > > > > > > > > + ; Link =3D Link->ForwardLink > > > > > > > > > > + ) { > > > > > > > > > > + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); > > > > > > > > > > + if (IS_PCI_BRIDGE (&Device->Pci)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "::Bridge [%02x|%02x|%02x] -", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + if (Device->IsPciExp) { > > > > > > > > > > + Status =3D SetupDevicePciFeatures ( Device, PciConfigPha= se); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "Not a PCIe capable device!\n")); > > > > > > > > > > + // > > > > > > > > > > + // PCI Bridge which does not have PCI Express Capability= structure > > > > > > > > > > + // cannot process this kind of PCI Bridge device > > > > > > > > > > + // > > > > > > > > > > + > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + SetupPciFeatures ( Device, PciConfigPhase); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "::Device [%02x|%02x|%02x] -", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + if (Device->IsPciExp) { > > > > > > > > > > + > > > > > > > > > > + Status =3D SetupDevicePciFeatures ( Device, PciConfigPha= se); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "Not a PCIe capable device!\n")); > > > > > > > > > > + // > > > > > > > > > > + // PCI Device which does not have PCI Express Capability= structure > > > > > > > > > > + // cannot process this kind of PCI device > > > > > > > > > > + // > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Program the PCI device, to override the PCI features as per th= e policy, > > > > > > > > > > + resolved from previous traverse. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The other PCI features configura= tion > > during > > > > > enumeration > > > > > > > > > > + of all the nodes of the PCI root= bridge instance were > > > > > > > > > > + programmed in PCI-compliance pat= tern along with the > > > > > > > > > > + device-specific policy, as appli= cable. > > > > > > > > > > + @retval EFI_UNSUPPORTED One of the override operation ma= ong > > the > > > > > nodes of > > > > > > > > > > + the PCI hierarchy resulted in a = incompatible address > > > > > > > > > > + range. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER The override operation is > > performed > > > > > with invalid input > > > > > > > > > > + parameters. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +ProgramDevicePciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + if ( SetupMaxPayloadSize ()) { > > > > > > > > > > + Status =3D OverrideMaxPayloadSize (PciDevice); > > > > > > > > > > + } > > > > > > > > > > + if ( SetupMaxReadReqSize ()) { > > > > > > > > > > + Status =3D OverrideMaxReadReqSize (PciDevice); > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Program all the nodes of the specified root bridge or PCI-PCI = Bridge, > > to > > > > > > > > > > + override the PCI features. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The other PCI features configura= tion > > during > > > > > enumeration > > > > > > > > > > + of all the nodes of the PCI root= bridge instance were > > > > > > > > > > + programmed in PCI-compliance pat= tern along with the > > > > > > > > > > + device-specific policy, as appli= cable. > > > > > > > > > > + @retval EFI_UNSUPPORTED One of the override operation ma= ong > > the > > > > > nodes of > > > > > > > > > > + the PCI hierarchy resulted in a = incompatible address > > > > > > > > > > + range. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER The override operation is > > performed > > > > > with invalid input > > > > > > > > > > + parameters. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +ProgramPciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_IO_DEVICE *Device; > > > > > > > > > > + > > > > > > > > > > + for ( Link =3D RootBridge->ChildList.ForwardLink > > > > > > > > > > + ; Link !=3D &RootBridge->ChildList > > > > > > > > > > + ; Link =3D Link->ForwardLink > > > > > > > > > > + ) { > > > > > > > > > > + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); > > > > > > > > > > + if (IS_PCI_BRIDGE (&Device->Pci)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "::Bridge [%02x|%02x|%02x] -", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + if (Device->IsPciExp) { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "ready to override!\n")); > > > > > > > > > > + > > > > > > > > > > + Status =3D ProgramDevicePciFeatures ( Device); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "skipped!\n")); > > > > > > > > > > + // > > > > > > > > > > + // PCI Bridge which does not have PCI Express Capability= structure > > > > > > > > > > + // cannot process this kind of PCI Bridge device > > > > > > > > > > + // > > > > > > > > > > + > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + Status =3D ProgramPciFeatures ( Device); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "::Device [%02x|%02x|%02x] -", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + if (Device->IsPciExp) { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "ready to override!\n")); > > > > > > > > > > + > > > > > > > > > > + Status =3D ProgramDevicePciFeatures ( Device); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( DEBUG_INFO, "skipped!\n")); > > > > > > > > > > + // > > > > > > > > > > + // PCI Device which does not have PCI Express Capability= structure > > > > > > > > > > + // cannot process this kind of PCI device > > > > > > > > > > + // > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Create a node of type PRIMARY_ROOT_PORT_NODE for the given > > PCI > > > > > device, and > > > > > > > > > > + assigns EFI handles of its Root Bridge and its own, along with= its PCI > > Bus > > > > > > > > > > + range for the secondary and subordinate bus range. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE for= its PCI > > Root > > > > > Bridge > > > > > > > > > > + @param Device A pointer to the PCI_IO_DEVICE for= the PCI > > > > > controller > > > > > > > > > > + @param RootPortSecBus PCI controller's Secondary Bus num= ber > > > > > > > > > > + @param RootPortSubBus PCI controller's Subordinate Bus n= umber > > > > > > > > > > + @param PrimaryRootPortNode A pointer to the > > > > > PRIMARY_ROOT_PORT_NODE to return > > > > > > > > > > + the newly created node for the PCI= controller. In > > > > > > > > > > + case of error nothing is return in= this. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS new node of > > PRIMARY_ROOT_PORT_NODE is > > > > > returned for > > > > > > > > > > + the PCI controller > > > > > > > > > > + EFI_OUT_OF_RESOURCES unable to create the node for th= e PCI > > > > > controller > > > > > > > > > > + EFI_INVALID_PARAMETER unable to store the node as the = input > > > > > buffer is > > > > > > > > > > + not empty (*PrimaryRootPortNode) > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +CreatePrimaryPciRootPortNode ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > > > > > + IN PCI_IO_DEVICE *Device, > > > > > > > > > > + IN UINT8 RootPortSecBus, > > > > > > > > > > + IN UINT8 RootPortSubBus, > > > > > > > > > > + OUT PRIMARY_ROOT_PORT_NODE **PrimaryRootPortNode > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *RootPortNode =3D NULL; > > > > > > > > > > + > > > > > > > > > > + if ( !*PrimaryRootPortNode) { > > > > > > > > > > + RootPortNode =3D AllocateZeroPool ( sizeo= f > > > > > (PRIMARY_ROOT_PORT_NODE)); > > > > > > > > > > + if ( RootPortNode =3D=3D NULL) { > > > > > > > > > > + return EFI_OUT_OF_RESOURCES; > > > > > > > > > > + } > > > > > > > > > > + RootPortNode->Signature =3D PCI_ROOT_PORT_SIGNATURE; > > > > > > > > > > + RootPortNode->RootBridgeHandle =3D RootBridge->Handle; > > > > > > > > > > + RootPortNode->RootPortHandle =3D Device->Handle; > > > > > > > > > > + RootPortNode->SecondaryBusStart =3D RootPortSecBus; > > > > > > > > > > + RootPortNode->SecondaryBusEnd =3D RootPortSubBus; > > > > > > > > > > + InitializeListHead ( &RootPortNode->NeighborRootPort); > > > > > > > > > > + *PrimaryRootPortNode =3D RootPortNode; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } else { > > > > > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Checks to report whether the input PCI controller's secondary = / > > > > > subordinate > > > > > > > > > > + bus numbers are within the recorded list of other PCI controll= ers > > (root > > > > > ports). > > > > > > > > > > + > > > > > > > > > > + @param RootPortNode A pointer to the first node of > > > > > PRIMARY_ROOT_PORT_NODE > > > > > > > > > > + @param RootPortSecBus PCI secondary bus number of the PCI > > > > controller > > > > > found > > > > > > > > > > + @param RootPortSubBus PCI subordinate bus number of the PC= I > > Root > > > > > Port found > > > > > > > > > > + > > > > > > > > > > + @retval TRUE A child PCI Root port found > > > > > > > > > > + FALSE A new PCI controller found > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckChildRootPort ( > > > > > > > > > > + IN PRIMARY_ROOT_PORT_NODE *RootPortNode, > > > > > > > > > > + IN UINT8 RootPortSecBus, > > > > > > > > > > + IN UINT8 RootPortSubBus > > > > > > > > > > +) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( !RootPortNode) { > > > > > > > > > > + return FALSE; > > > > > > > > > > + } > > > > > > > > > > + Link =3D &RootPortNode->NeighborRootPort; > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK ( Link); > > > > > > > > > > + if ( RootPortSecBus >=3D Temp->SecondaryBusStart > > > > > > > > > > + && RootPortSubBus <=3D Temp->SecondaryBusEnd) { > > > > > > > > > > + // > > > > > > > > > > + // given root port's secondary & subordinate within its pr= imary > > ports > > > > > > > > > > + // hence return as child port > > > > > > > > > > + // > > > > > > > > > > + return TRUE; > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while (Link !=3D &RootPortNode->NeighborRootPort); > > > > > > > > > > + // > > > > > > > > > > + // the given root port's secondary / subordinate bus numbers d= o not > > > > > belong to > > > > > > > > > > + // any existing primary root port's bus range hence consider a= nother > > > > > primary > > > > > > > > > > + // root port of the root bridge controller > > > > > > > > > > + // > > > > > > > > > > + return FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Create the vector of PCI Feature configuration table as per th= e > > number > > > > of > > > > > > > > > > + the PCI Root Ports given, assigns default value to the PCI fea= tures > > > > > supported > > > > > > > > > > + and assign its address to the global variable > > > > > "mPciFeaturesConfigurationTableInstances". > > > > > > > > > > + > > > > > > > > > > + @param NumberOfRootPorts An input arguement of UINTN to > > indicate > > > > > number of > > > > > > > > > > + primary PCI physical Root Bridge d= evices found > > > > > > > > > > + > > > > > > > > > > + @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to sto= re > > PCI > > > > > feature > > > > > > > > > > + configuration table for all the = physical PCI root > > > > > > > > > > + ports given > > > > > > > > > > + EFI_SUCCESS PCI Feature COnfiguration table = created for all > > > > > > > > > > + the PCI Rooot ports reported > > > > > > > > > > + */ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +CreatePciFeaturesConfigurationTableInstances ( > > > > > > > > > > + IN UINTN NumberOfRootPorts > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *PciRootBridgePortFeatures =3D NULL; > > > > > > > > > > + UINTN Instances; > > > > > > > > > > + > > > > > > > > > > + PciRootBridgePortFeatures =3D AllocateZeroPool ( > > > > > > > > > > + sizeof > > ( OTHER_PCI_FEATURES_CONFIGURATION_TABLE) > > > > * > > > > > NumberOfRootPorts > > > > > > > > > > + ); > > > > > > > > > > + if ( !PciRootBridgePortFeatures) { > > > > > > > > > > + return EFI_OUT_OF_RESOURCES; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + for ( Instances =3D 0; Instances < NumberOfRootPorts; Instance= s++) { > > > > > > > > > > + PciRootBridgePortFeatures [Instances].ID = =3D Instances + 1; > > > > > > > > > > + PciRootBridgePortFeatures [Instances].Max_Payload_Size = =3D > > > > > PCIE_MAX_PAYLOAD_SIZE_4096B; > > > > > > > > > > + PciRootBridgePortFeatures [Instances].Max_Read_Request_Size = =3D > > > > > PCIE_MAX_READ_REQ_SIZE_4096B; > > > > > > > > > > + PciRootBridgePortFeatures > > [Instances].Lock_Max_Read_Request_Size > > > > =3D > > > > > FALSE; > > > > > > > > > > + } > > > > > > > > > > + mPciFeaturesConfigurationTableInstances =3D > > PciRootBridgePortFeatures; > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine pairs the each PCI Root Port node with one of the= PCI > > > > Feature > > > > > > > > > > + Configuration Table node. Each physical PCI Root Port has its = own PCI > > > > > feature > > > > > > > > > > + configuration table which will used for aligning all its downs= tream > > > > > components. > > > > > > > > > > + > > > > > > > > > > + @param NumberOfRootPorts inputs the number of physical PC= I > > root > > > > > ports > > > > > > > > > > + found on the Root bridge instanc= e > > > > > > > > > > + > > > > > > > > > > + @retval EFI_INVALID_PARAMETER if the primary PCI root ports li= st is > > > > > vacant when > > > > > > > > > > + there is one or more PCI Root po= rt indicated as per > > > > > > > > > > + input parameter > > > > > > > > > > + EFI_UNSUPPORTED The PCI Root Port nodes not pair= ed > > equally > > > > with > > > > > > > > > > + the PCI Configuration Table node= s > > > > > > > > > > + EFI_SUCCESS each PCI feature configuration n= ode is paired > > > > > equally > > > > > > > > > > + with each PCI Root port in the l= ist > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +AssignPciFeaturesConfigurationTable ( > > > > > > > > > > + IN UINTN NumberOfRootPorts > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + UINTN Instances; > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( !mPrimaryRootPortList > > > > > > > > > > + && NumberOfRootPorts) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, > > > > > > > > > > + "Critical error! no internal table setup for %d PCI Root= ports \n", > > > > > > > > > > + NumberOfRootPorts > > > > > > > > > > + )); > > > > > > > > > > + return EFI_INVALID_PARAMETER; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( NumberOfRootPorts) { > > > > > > > > > > + Link =3D &mPrimaryRootPortList->NeighborRootPort; > > > > > > > > > > + for ( Instances =3D 0 > > > > > > > > > > + ; (Instances < NumberOfRootPorts) > > > > > > > > > > + ; Instances++ > > > > > > > > > > + ) { > > > > > > > > > > + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK ( Link); > > > > > > > > > > + Temp->OtherPciFeaturesConfigurationTable =3D > > > > > &mPciFeaturesConfigurationTableInstances [Instances]; > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, > > > > > > > > > > + "Assigned to %dth primary root port\n", > > > > > > > > > > + Instances > > > > > > > > > > + )); > > > > > > > > > > + > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } > > > > > > > > > > + if ( Link !=3D &mPrimaryRootPortList->NeighborRootPort) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, > > > > > > > > > > + "Error!! PCI Root Port list is not properly matched wi= th Config., > > Table > > > > > list \n" > > > > > > > > > > + )); > > > > > > > > > > + return EFI_UNSUPPORTED; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Prepare each PCI Controller (Root Port) with its own PCI Featu= re > > > > > configuration > > > > > > > > > > + table node that can be used for tracking to align all PCI node= s in its > > > > > hierarchy. > > > > > > > > > > + > > > > > > > > > > + @param PrimaryRootPorts A pointer to > > PRIMARY_ROOT_PORT_NODE > > > > > > > > > > + @param NumberOfRootPorts Total number of pysical primary = PCI > > > > Root > > > > > ports > > > > > > > > > > + > > > > > > > > > > + @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to sto= re > > PCI > > > > > feature > > > > > > > > > > + configuration table for all the = physical PCI root > > > > > > > > > > + ports given > > > > > > > > > > + EFI_INVALID_PARAMETER if the primary PCI root ports li= st is > > vacant > > > > > when > > > > > > > > > > + there is one or more PCI Root po= rt indicated as per > > > > > > > > > > + input parameter > > > > > > > > > > + EFI_UNSUPPORTED The PCI Root Port nodes not pair= ed > > equally > > > > with > > > > > > > > > > + the PCI Configuration Table node= s > > > > > > > > > > + EFI_SUCCESS each PCI feature configuration n= ode is paired > > > > > equally > > > > > > > > > > + with each PCI Root port in the l= ist > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PreparePciControllerConfigurationTable ( > > > > > > > > > > + IN PRIMARY_ROOT_PORT_NODE *PrimaryRootPorts, > > > > > > > > > > + IN UINTN NumberOfRootPorts > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + mPrimaryRootPortList =3D PrimaryRootPorts; > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "Number of primary Root Ports found on this br= idge > > > > > =3D %d\n", > > > > > > > > > > + NumberOfRootPorts > > > > > > > > > > + )); > > > > > > > > > > + > > > > > > > > > > + Status =3D CreatePciFeaturesConfigurationTableInstances > > > > > ( NumberOfRootPorts); > > > > > > > > > > + if ( EFI_ERROR(Status)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, "Unexpected memory node creation error for = PCI > > > > > features!\n" > > > > > > > > > > + )); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // align the primary root port nodes list with the PCI Featu= re > > > > configuration > > > > > > > > > > + // table. Note that the PCI Feature configuration table is n= ot > > maintain > > > > for > > > > > > > > > > + // the RCiEP devices > > > > > > > > > > + // > > > > > > > > > > + Status =3D AssignPciFeaturesConfigurationTable > > ( NumberOfRootPorts); > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Scan all the nodes of the RootBridge to identify and create a = separate > > list > > > > > > > > > > + of all primary physical PCI root ports and link each with its = own > > instance > > > > of > > > > > > > > > > + the PCI Feature Configuration Table. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE of the PC= I > > Root > > > > > Bridge > > > > > > > > > > + > > > > > > > > > > + @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to sto= re > > PCI > > > > > feature > > > > > > > > > > + configuration table for all the = physical PCI root > > > > > > > > > > + ports given > > > > > > > > > > + EFI_NOT_FOUND No PCI Bridge device found > > > > > > > > > > + EFI_SUCCESS PCI Feature COnfiguration table = created for all > > > > > > > > > > + the PCI Rooot ports found > > > > > > > > > > + EFI_INVALID_PARAMETER invalid parameter passed to the > > routine > > > > > which > > > > > > > > > > + creates the PCI controller node = for the primary > > > > > > > > > > + Root post list > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +RecordPciRootPortBridges ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status =3D EFI_NOT_FOUND; > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_IO_DEVICE *Device; > > > > > > > > > > + UINTN NumberOfRootPorts; > > > > > > > > > > + PRIMARY_ROOT_PORT_NODE *PrimaryRootPorts, > > > > > > > > > > + *TempNode; > > > > > > > > > > + UINT8 RootPortSecBus, > > > > > > > > > > + RootPortSubBus; > > > > > > > > > > + > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** RecordPciRootPortBridges -start > > > > > *************>>\n" > > > > > > > > > > + )); > > > > > > > > > > + NumberOfRootPorts =3D 0; > > > > > > > > > > + PrimaryRootPorts =3D NULL; > > > > > > > > > > + for ( Link =3D RootBridge->ChildList.ForwardLink > > > > > > > > > > + ; Link !=3D &RootBridge->ChildList > > > > > > > > > > + ; Link =3D Link->ForwardLink > > > > > > > > > > + ) { > > > > > > > > > > + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); > > > > > > > > > > + if (IS_PCI_BRIDGE (&Device->Pci)) { > > > > > > > > > > + Status =3D GetPciRootPortBusAssigned ( > > > > > > > > > > + Device, > > > > > > > > > > + NULL, > > > > > > > > > > + &RootPortSecBus, > > > > > > > > > > + &RootPortSubBus > > > > > > > > > > + ); > > > > > > > > > > + if ( !EFI_ERROR(Status)) { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "::Device [%02x|%02x|%02x] - SecBus=3D0x= %x, > > > > > SubBus=3D0x%x\n", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber, > > > > > > > > > > + RootPortSecBus, RootPortSubBus > > > > > > > > > > + )); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, "Unexpected read error [0x%lx]::Device > > > > > [%02x|%02x|%02x]\n", > > > > > > > > > > + Status, Device->BusNumber, Device->DeviceNumber, Dev= ice- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + RootPortSecBus =3D RootPortSubBus =3D 0; > > > > > > > > > > + continue; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( !PrimaryRootPorts) { > > > > > > > > > > + NumberOfRootPorts++; > > > > > > > > > > + Status =3D CreatePrimaryPciRootPortNode ( > > > > > > > > > > + RootBridge, > > > > > > > > > > + Device, > > > > > > > > > > + RootPortSecBus, > > > > > > > > > > + RootPortSubBus, > > > > > > > > > > + &PrimaryRootPorts > > > > > > > > > > + ); > > > > > > > > > > + if ( EFI_ERROR(Status)) { > > > > > > > > > > + // > > > > > > > > > > + // abort mission to scan for all primary roots ports o= f a bridge > > > > > > > > > > + // controller if error encountered for very first PCI = primary root > > port > > > > > > > > > > + // > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, "Unexpected node creation error > > [0x%lx]::Device > > > > > [%02x|%02x|%02x]\n", > > > > > > > > > > + Status, Device->BusNumber, Device->DeviceNumber, D= evice- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + return Status; > > > > > > > > > > + } > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "first primary root port found::Device > > > > > [%02x|%02x|%02x]\n", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + } else { > > > > > > > > > > + if ( !CheckChildRootPort ( PrimaryRootPorts, RootPortSec= Bus, > > > > > RootPortSubBus)) { > > > > > > > > > > + NumberOfRootPorts++; > > > > > > > > > > + TempNode =3D NULL; > > > > > > > > > > + Status =3D CreatePrimaryPciRootPortNode ( > > > > > > > > > > + RootBridge, > > > > > > > > > > + Device, > > > > > > > > > > + RootPortSecBus, > > > > > > > > > > + RootPortSubBus, > > > > > > > > > > + &TempNode > > > > > > > > > > + ); > > > > > > > > > > + if ( !EFI_ERROR(Status)) { > > > > > > > > > > + // > > > > > > > > > > + // another primary root port found on the same bridg= e > > controller > > > > > > > > > > + // insert in the node list > > > > > > > > > > + // > > > > > > > > > > + InsertTailList ( &PrimaryRootPorts->NeighborRootPort= , > > > > &TempNode- > > > > > >NeighborRootPort); > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "next primary root port found::Devic= e > > > > > [%02x|%02x|%02x]\n", > > > > > > > > > > + Device->BusNumber, Device->DeviceNumber, Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_ERROR, "Unexpected node creation error > > [0x%lx]::Device > > > > > [%02x|%02x|%02x]\n", > > > > > > > > > > + Status, Device->BusNumber, Device->DeviceNumber,= Device- > > > > > >FunctionNumber > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // prepare the PCI root port and its feature configuration tab= le list > > > > > > > > > > + // > > > > > > > > > > + if ( NumberOfRootPorts) { > > > > > > > > > > + Status =3D PreparePciControllerConfigurationTable ( > > > > > > > > > > + PrimaryRootPorts, > > > > > > > > > > + NumberOfRootPorts > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + } else { > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "No PCI Root port found on this bridge!\n" > > > > > > > > > > + )); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** RecordPciRootPortBridges - end > > > > > **********>>\n" > > > > > > > > > > + )); > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Enumerate all the nodes of the specified root bridge or PCI-PC= I > > Bridge, to > > > > > > > > > > + configure the other PCI features. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The other PCI features configura= tion > > during > > > > > enumeration > > > > > > > > > > + of all the nodes of the PCI root= bridge instance were > > > > > > > > > > + programmed in PCI-compliance pat= tern along with the > > > > > > > > > > + device-specific policy, as appli= cable. > > > > > > > > > > + @retval EFI_UNSUPPORTED One of the override operation ma= ong > > the > > > > > nodes of > > > > > > > > > > + the PCI hierarchy resulted in a = incompatible address > > > > > > > > > > + range. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER The override operation is > > performed > > > > > with invalid input > > > > > > > > > > + parameters. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +EnumerateOtherPciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + CHAR16 *Str; > > > > > > > > > > + UINTN OtherPciFeatureConfigPhase; > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // check on PCI features configuration is complete and re- > > enumeration is > > > > > required > > > > > > > > > > + // > > > > > > > > > > + if ( !CheckPciFeaturesConfigurationRequired ( RootBridge)) { > > > > > > > > > > + return EFI_ALREADY_STARTED; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + Str =3D ConvertDevicePathToText ( > > > > > > > > > > + DevicePathFromHandle (RootBridge->Handle), > > > > > > > > > > + FALSE, > > > > > > > > > > + FALSE > > > > > > > > > > + ); > > > > > > > > > > + DEBUG ((DEBUG_INFO, "Enumerating PCI features for Root > > Bridge %s\n", > > > > > Str !=3D NULL ? Str : L"")); > > > > > > > > > > + > > > > > > > > > > + for ( OtherPciFeatureConfigPhase =3D PciFeatureRootBridgeScan > > > > > > > > > > + ; OtherPciFeatureConfigPhase <=3D > > PciFeatureConfigurationComplete > > > > > > > > > > + ; OtherPciFeatureConfigPhase++ > > > > > > > > > > + ) { > > > > > > > > > > + switch ( OtherPciFeatureConfigPhase){ > > > > > > > > > > + case PciFeatureRootBridgeScan: > > > > > > > > > > + SetupPciFeaturesConfigurationDefaults (); > > > > > > > > > > + // > > > > > > > > > > + //first scan the entire root bridge heirarchy for the pr= imary PCI > > root > > > > > ports > > > > > > > > > > + // > > > > > > > > > > + RecordPciRootPortBridges ( RootBridge); > > > > > > > > > > + break; > > > > > > > > > > + > > > > > > > > > > + case PciFeatureGetDevicePolicy: > > > > > > > > > > + case PciFeatureSetupPhase: > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** SetupPciFeatures - start > > > > > **********>>\n" > > > > > > > > > > + )); > > > > > > > > > > + // > > > > > > > > > > + // enumerate the other PCI features > > > > > > > > > > + // > > > > > > > > > > + Status =3D SetupPciFeatures ( RootBridge, > > OtherPciFeatureConfigPhase); > > > > > > > > > > + > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** SetupPciFeatures - end > > > > > **********>>\n" > > > > > > > > > > + )); > > > > > > > > > > + break; > > > > > > > > > > + > > > > > > > > > > + case PciFeatureConfigurationPhase: > > > > > > > > > > + // > > > > > > > > > > + // override the PCI features as per enumeration phase > > > > > > > > > > + // > > > > > > > > > > + DEBUG ((DEBUG_INFO, "PCI features override for Root > > Bridge %s\n", > > > > > Str !=3D NULL ? Str : L"")); > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** ProgramPciFeatures - start > > > > > **********>>\n" > > > > > > > > > > + )); > > > > > > > > > > + Status =3D ProgramPciFeatures ( RootBridge); > > > > > > > > > > + DEBUG (( > > > > > > > > > > + DEBUG_INFO, "<<********** ProgramPciFeatures - end > > > > > **********>>\n" > > > > > > > > > > + )); > > > > > > > > > > + break; > > > > > > > > > > + > > > > > > > > > > + case PciFeatureConfigurationComplete: > > > > > > > > > > + // > > > > > > > > > > + // clean up the temporary resource nodes created for thi= s root > > bridge > > > > > > > > > > + // > > > > > > > > > > + DestroyPrimaryRootPortNodes (); > > > > > > > > > > + > > > > > > > > > > + ErasePciFeaturesConfigurationTable (); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (Str !=3D NULL) { > > > > > > > > > > + FreePool (Str); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // mark this root bridge as PCI features configuration complet= e, and > > no > > > > > new > > > > > > > > > > + // enumeration is required > > > > > > > > > > + // > > > > > > > > > > + AddRootBridgeInPciFeaturesConfigCompletionList ( RootBridge, > > FALSE); > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine is invoked from the Stop () interface for the EFI= handle of > > > > the > > > > > > > > > > + RootBridge. Free up its node of type > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +DestroyRootBridgePciFeaturesConfigCompletionList ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + LIST_ENTRY *Link; > > > > > > > > > > + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; > > > > > > > > > > + > > > > > > > > > > + if ( mPciFeaturesConfigurationCompletionList) { > > > > > > > > > > + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink; > > > > > > > > > > + > > > > > > > > > > + do { > > > > > > > > > > + Temp =3D > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK > > (Link); > > > > > > > > > > + if ( Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { > > > > > > > > > > + RemoveEntryList ( Link); > > > > > > > > > > + FreePool ( Temp); > > > > > > > > > > + return; > > > > > > > > > > + } > > > > > > > > > > + Link =3D Link->ForwardLink; > > > > > > > > > > + } while (Link !=3D &mPciFeaturesConfigurationCompletionList- > > > > > >RootBridgeLink); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // not found on the PCI feature configuration completion list,= return > > > > > > > > > > + // > > > > > > > > > > + return; > > > > > > > > > > +} > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > new file mode 100644 > > > > > index 0000000000..9f225fa993 > > > > > --- /dev/null > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > @@ -0,0 +1,201 @@ > > > > > +/** @file > > > > > > > > > > + PCI standard feature support functions implementation for PCI = Bus > > > > > module.. > > > > > > > > > > + > > > > > > > > > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > > > > > > > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > + > > > > > > > > > > +#ifndef _EFI_PCI_FEATURES_SUPPORT_H_ > > > > > > > > > > +#define _EFI_PCI_FEATURES_SUPPORT_H_ > > > > > > > > > > + > > > > > > > > > > +#include "PciBus.h" > > > > > > > > > > +#include "PciPlatformSupport.h" > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Macro definitions for the PCI Features support PCD > > > > > > > > > > +// > > > > > > > > > > +#define PCI_FEATURE_SUPPORT_FLAG_MPS BIT0 > > > > > > > > > > +#define PCI_FEATURE_SUPPORT_FLAG_MRRS BIT1 > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// defines the data structure to hold the details of the PCI Roo= t port > > > > devices > > > > > > > > > > +// > > > > > > > > > > +typedef struct _PRIMARY_ROOT_PORT_NODE > > > > > PRIMARY_ROOT_PORT_NODE; > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// defines the data structure to hold the configuration data for= the > > other > > > > > PCI > > > > > > > > > > +// features > > > > > > > > > > +// > > > > > > > > > > +typedef struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > OTHER_PCI_FEATURES_CONFIGURATION_TABLE; > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Defines for the PCI features configuration completion and re- > > > > > enumeration list > > > > > > > > > > +// > > > > > > > > > > +typedef struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST; > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Signature value for the PCI Root Port node > > > > > > > > > > +// > > > > > > > > > > +#define PCI_ROOT_PORT_SIGNATURE SIGNATURE_32 ('p',= 'c', > > 'i', > > > > 'p') > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Definitions of the PCI Root Port data structure members > > > > > > > > > > +// > > > > > > > > > > +struct _PRIMARY_ROOT_PORT_NODE { > > > > > > > > > > + // > > > > > > > > > > + // Signature header > > > > > > > > > > + // > > > > > > > > > > + UINT32 Signature; > > > > > > > > > > + // > > > > > > > > > > + // linked list pointers to next node > > > > > > > > > > + // > > > > > > > > > > + LIST_ENTRY NeighborRootPort; > > > > > > > > > > + // > > > > > > > > > > + // EFI handle of the parent Root Bridge instance > > > > > > > > > > + // > > > > > > > > > > + EFI_HANDLE RootBridgeHandle; > > > > > > > > > > + // > > > > > > > > > > + // EFI handle of the PCI controller > > > > > > > > > > + // > > > > > > > > > > + EFI_HANDLE RootPortHandle; > > > > > > > > > > + // > > > > > > > > > > + // PCI Secondary bus value of the PCI controller > > > > > > > > > > + // > > > > > > > > > > + UINT8 SecondaryBusStart; > > > > > > > > > > + // > > > > > > > > > > + // PCI Subordinate bus value of the PCI controller > > > > > > > > > > + // > > > > > > > > > > + UINT8 SecondaryBusEnd; > > > > > > > > > > + // > > > > > > > > > > + // pointer to the corresponding PCI feature configuration Tabl= e node > > > > > > > > > > + // > > > > > > > > > > + OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > *OtherPciFeaturesConfigurationTable; > > > > > > > > > > +}; > > > > > > > > > > + > > > > > > > > > > +#define PRIMARY_ROOT_PORT_NODE_FROM_LINK(a) \ > > > > > > > > > > + CR (a, PRIMARY_ROOT_PORT_NODE, NeighborRootPort, > > > > > PCI_ROOT_PORT_SIGNATURE) > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Definition of the PCI Feature configuration Table members > > > > > > > > > > +// > > > > > > > > > > +struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE { > > > > > > > > > > + // > > > > > > > > > > + // Configuration Table ID > > > > > > > > > > + // > > > > > > > > > > + UINTN ID; > > > > > > > > > > + // > > > > > > > > > > + // to configure the PCI feature Maximum payload size to mainta= in the > > > > data > > > > > packet > > > > > > > > > > + // size among all the PCI devices in the PCI hierarchy > > > > > > > > > > + // > > > > > > > > > > + UINT8 Max_Payload_Size; > > > > > > > > > > + // > > > > > > > > > > + // to configure the PCI feature maximum read request size to > > maintain > > > > the > > > > > memory > > > > > > > > > > + // requester size among all the PCI devices in the PCI hierarc= hy > > > > > > > > > > + // > > > > > > > > > > + UINT8 Max_Read_Request_Siz= e; > > > > > > > > > > + // > > > > > > > > > > + // lock the Max_Read_Request_Size for the entire PCI tree of a= root > > port > > > > > > > > > > + // > > > > > > > > > > + BOOLEAN Lock_Max_Read_Reques= t_Size; > > > > > > > > > > +}; > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// PCI feature configuration node signature value > > > > > > > > > > +// > > > > > > > > > > +#define PCI_FEATURE_CONFIGURATION_SIGNATURE > > > > > SIGNATURE_32 ('p', 'c', 'i', 'f') > > > > > > > > > > + > > > > > > > > > > +struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST { > > > > > > > > > > + // > > > > > > > > > > + // Signature header > > > > > > > > > > + // > > > > > > > > > > + UINT32 Signature; > > > > > > > > > > + // > > > > > > > > > > + // link to next Root Bridge whose PCI Feature configuration is > > complete > > > > > > > > > > + // > > > > > > > > > > + LIST_ENTRY RootBridgeLink; > > > > > > > > > > + // > > > > > > > > > > + // EFI handle of the Root Bridge whose PCI feature configurati= on is > > > > > complete > > > > > > > > > > + // > > > > > > > > > > + EFI_HANDLE RootBridgeHandle; > > > > > > > > > > + // > > > > > > > > > > + // indication for complete re-enumeration of the PCI feature > > > > configuration > > > > > > > > > > + // > > > > > > > > > > + BOOLEAN ReEnumeratePciFeatur= eConfiguration; > > > > > > > > > > +}; > > > > > > > > > > + > > > > > > > > > > +#define > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK(a) \ > > > > > > > > > > + CR (a, PCI_FEATURE_CONFIGURATION_COMPLETION_LIST, > > > > > RootBridgeLink, PCI_FEATURE_CONFIGURATION_SIGNATURE) > > > > > > > > > > + > > > > > > > > > > +// > > > > > > > > > > +// Declaration of the internal sub-phases within the PCI Feature > > > > > enumeration > > > > > > > > > > +// > > > > > > > > > > +typedef enum { > > > > > > > > > > + // > > > > > > > > > > + // initial phase in configuring the other PCI features to reco= rd the > > primary > > > > > > > > > > + // root ports > > > > > > > > > > + // > > > > > > > > > > + PciFeatureRootBridgeScan, > > > > > > > > > > + // > > > > > > > > > > + // get the PCI device-specific platform policies and align wit= h device > > > > > capabilities > > > > > > > > > > + // > > > > > > > > > > + PciFeatureGetDevicePolicy, > > > > > > > > > > + // > > > > > > > > > > + // align all PCI nodes in the PCI heirarchical tree > > > > > > > > > > + // > > > > > > > > > > + PciFeatureSetupPhase, > > > > > > > > > > + // > > > > > > > > > > + // finally override to complete configuration of the PCI featu= re > > > > > > > > > > + // > > > > > > > > > > + PciFeatureConfigurationPhase, > > > > > > > > > > + // > > > > > > > > > > + // PCI feature configuration complete > > > > > > > > > > + // > > > > > > > > > > + PciFeatureConfigurationComplete > > > > > > > > > > + > > > > > > > > > > +}PCI_FEATURE_CONFIGURATION_PHASE; > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Main routine to indicate platform selection of any of the othe= r PCI > > > > features > > > > > > > > > > + to be configured by this driver > > > > > > > > > > + > > > > > > > > > > + @retval TRUE platform has selected the other PCI features t= o be > > > > > configured > > > > > > > > > > + FALSE platform has not selected any of the other PCI= features > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckOtherPciFeaturesPcd ( > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Enumerate all the nodes of the specified root bridge or PCI-PC= I > > Bridge, to > > > > > > > > > > + configure the other PCI features. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The other PCI features configura= tion > > during > > > > > enumeration > > > > > > > > > > + of all the nodes of the PCI root= bridge instance were > > > > > > > > > > + programmed in PCI-compliance pat= tern along with the > > > > > > > > > > + device-specific policy, as appli= cable. > > > > > > > > > > + @retval EFI_UNSUPPORTED One of the override operation ma= ong > > the > > > > > nodes of > > > > > > > > > > + the PCI hierarchy resulted in a = incompatible address > > > > > > > > > > + range. > > > > > > > > > > + @retval EFI_INVALID_PARAMETER The override operation is > > performed > > > > > with invalid input > > > > > > > > > > + parameters. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +EnumerateOtherPciFeatures ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This routine is invoked from the Stop () interface for the EFI= handle of > > > > the > > > > > > > > > > + RootBridge. Free up its node of type > > > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST. > > > > > > > > > > + > > > > > > > > > > + @param RootBridge A pointer to the PCI_IO_DEVICE > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +DestroyRootBridgePciFeaturesConfigCompletionList ( > > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > > > > > + ); > > > > > > > > > > +#endif > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > new file mode 100644 > > > > > index 0000000000..d94037d69a > > > > > --- /dev/null > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > @@ -0,0 +1,565 @@ > > > > > +/** @file > > > > > > > > > > + This file encapsulate the usage of PCI Platform Protocol > > > > > > > > > > + > > > > > > > > > > + This file define the necessary hooks used to obtain the platfo= rm > > > > > > > > > > + level data and policies which could be used in the PCI Enumera= tion > > > > phases > > > > > > > > > > + > > > > > > > > > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > > > > > > > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > + > > > > > > > > > > +#include "PciPlatformSupport.h" > > > > > > > > > > + > > > > > > > > > > +EFI_PCI_PLATFORM_PROTOCOL *mPciPlatformProto= col; > > > > > > > > > > +EFI_PCI_OVERRIDE_PROTOCOL *mPciOverrideProto= col; > > > > > > > > > > + > > > > > > > > > > +EFI_PCI_PLATFORM_PROTOCOL2 *mPciPlatformProto= col2; > > > > > > > > > > +EFI_PCI_OVERRIDE_PROTOCOL2 *mPciOverrideProto= col2; > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the PCI Platform Protocol published by > > platform > > > > > driver > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +GetPciPlatformProtocol ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + mPciPlatformProtocol2 =3D NULL; > > > > > > > > > > + gBS->LocateProtocol ( > > > > > > > > > > + &gEfiPciPlatformProtocol2Guid, > > > > > > > > > > + NULL, > > > > > > > > > > + (VOID **) &mPciPlatformProtocol2 > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // If PCI Platform protocol doesn't exist, try to get Pci Over= ride > > Protocol. > > > > > > > > > > + // > > > > > > > > > > + if (mPciPlatformProtocol2 =3D=3D NULL) { > > > > > > > > > > + mPciOverrideProtocol2 =3D NULL; > > > > > > > > > > + gBS->LocateProtocol ( > > > > > > > > > > + &gEfiPciOverrideProtocol2Guid, > > > > > > > > > > + NULL, > > > > > > > > > > + (VOID **) &mPciOverrideProtocol2 > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // fetch the old PCI Platform Protocols if new are not install= ed > > > > > > > > > > + // > > > > > > > > > > + if (mPciOverrideProtocol2 =3D=3D NULL) { > > > > > > > > > > + > > > > > > > > > > + mPciPlatformProtocol =3D NULL; > > > > > > > > > > + gBS->LocateProtocol ( > > > > > > > > > > + &gEfiPciPlatformProtocolGuid, > > > > > > > > > > + NULL, > > > > > > > > > > + (VOID **) &mPciPlatformProtocol > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + // > > > > > > > > > > + // If PCI Platform protocol doesn't exist, try to get Pci O= verride > > Protocol. > > > > > > > > > > + // > > > > > > > > > > + if (mPciPlatformProtocol =3D=3D NULL) { > > > > > > > > > > + mPciOverrideProtocol =3D NULL; > > > > > > > > > > + gBS->LocateProtocol ( > > > > > > > > > > + &gEfiPciOverrideProtocolGuid, > > > > > > > > > > + NULL, > > > > > > > > > > + (VOID **) &mPciOverrideProtocol > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function indicates the presence of PCI Platform driver > > > > > > > > > > + @retval TRUE or FALSE > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckPciPlatformProtocolInstall ( > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + if (mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + return TRUE; > > > > > > > > > > + } else if (mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + return TRUE; > > > > > > > > > > + } else { > > > > > > > > > > + if (mPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + return TRUE; > > > > > > > > > > + } else if (mPciOverrideProtocol !=3D NULL){ > > > > > > > > > > + return TRUE; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return FALSE; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Provides the hooks from the PCI bus driver to every PCI contro= ller > > > > > (device/function) at various > > > > > > > > > > + stages of the PCI enumeration process that allow the host brid= ge > > driver > > > > to > > > > > preinitialize individual > > > > > > > > > > + PCI controllers before enumeration. > > > > > > > > > > + > > > > > > > > > > + This function is called during the PCI enumeration process. No= specific > > > > > action is expected from this > > > > > > > > > > + member function. It allows the host bridge driver to preinitia= lize > > > > individual > > > > > PCI controllers before > > > > > > > > > > + enumeration. > > > > > > > > > > + > > > > > > > > > > + @param[in] HostBridgeHandle The associated PCI host bridge > > handle. > > > > > > > > > > + @param[in] RootBridgeHandle The associated PCI root bridge > > handle. > > > > > > > > > > + @param[in] RootBridgePciAddress The address of the PCI device = on > > the > > > > > PCI bus. > > > > > > > > > > + @param[in] Phase The phase of the PCI controller enum= eration. > > > > > > > > > > + @param[in] ExecPhase Defines the execution phase of the P= CI > > chipset > > > > > driver. > > > > > > > > > > + > > > > > > > > > > + @retval Status returns the status from the PCI Plat= form > > protocol as > > > > is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciPlatformPreprocessController ( > > > > > > > > > > + IN EFI_HANDLE HostBridgeHan= dle, > > > > > > > > > > + IN EFI_HANDLE RootBridgeHan= dle, > > > > > > > > > > + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS > > > > > RootBridgePciAddress, > > > > > > > > > > + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, > > > > > > > > > > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + if (mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > + // > > > > > > > > > > + Status =3D mPciPlatformProtocol2->PlatformPrepController ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciPlatformProtocol2, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else if (mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is pre= sent. > > > > > > > > > > + // > > > > > > > > > > + Status =3D mPciOverrideProtocol2->PlatformPrepController ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciOverrideProtocol2, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + if (mPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is p= resent. > > > > > > > > > > + // > > > > > > > > > > + Status =3D mPciPlatformProtocol->PlatformPrepController ( > > > > > > > > > > + mPciPlatformProtocol, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else if (mPciOverrideProtocol !=3D NULL) { > > > > > > > > > > + // > > > > > > > > > > + // Call PlatformPci::PrepController() if the protocol is p= resent. > > > > > > > > > > + // > > > > > > > > > > + Status =3D mPciOverrideProtocol->PlatformPrepController ( > > > > > > > > > > + mPciOverrideProtocol, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + RootBridgeHandle, > > > > > > > > > > + RootBridgePciAddress, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // return PCI Platform Protocol not found > > > > > > > > > > + // > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function notifies the PCI Platform driver about the PCI h= ost > > bridge > > > > > resource > > > > > > > > > > + allocation phase and PCI execution phase. > > > > > > > > > > + > > > > > > > > > > + @param[in] HostBridge The handle of the host bridge contr= oller. > > > > > > > > > > + @param[in] Phase The phase of the PCI bus enumeratio= n. > > > > > > > > > > + @param[in] ExecPhase Defines the execution phase of the = PCI > > > > chipset > > > > > driver. > > > > > > > > > > + @retval Status returns the status from the PCI Pl= atform > > protocol > > > > as > > > > > is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciPlatformNotifyPhase ( > > > > > > > > > > + IN EFI_HANDLE HostBridge= Handle, > > > > > > > > > > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, > > > > > > > > > > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + if ( mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol2->PlatformNotify ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciPlatformProtocol2, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else if ( mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciOverrideProtocol2->PlatformNotify ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciOverrideProtocol2, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + > > > > > > > > > > + if ( mPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol->PlatformNotify ( > > > > > > > > > > + mPciPlatformProtocol, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else if ( mPciOverrideProtocol !=3D NULL){ > > > > > > > > > > + Status =3D mPciOverrideProtocol->PlatformNotify ( > > > > > > > > > > + mPciOverrideProtocol, > > > > > > > > > > + HostBridgeHandle, > > > > > > > > > > + Phase, > > > > > > > > > > + ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // return PCI Platform Protocol not found > > > > > > > > > > + // > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the PCI platform policy. > > > > > > > > > > + > > > > > > > > > > + @param PciPolicy pointer to the legacy > > EFI_PCI_PLATFORM_POLICY > > > > > > > > > > + @retval Status returns the status from the PCI Platform= protocol > > as is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciGetPlatformPolicy ( > > > > > > > > > > + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + if ( mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol2->GetPlatformPolicy ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciPlatformProtocol2, > > > > > > > > > > + PciPolicy > > > > > > > > > > + ); > > > > > > > > > > + } else if ( mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciOverrideProtocol2->GetPlatformPolicy ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciOverrideProtocol2, > > > > > > > > > > + PciPolicy > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + if ( mPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol->GetPlatformPolicy ( > > > > > > > > > > + mPciPlatformProtocol, > > > > > > > > > > + PciPolicy > > > > > > > > > > + ); > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if ( mPciOverrideProtocol !=3D NULL) { > > > > > > > > > > + Status =3D mPciOverrideProtocol->GetPlatformPolicy ( > > > > > > > > > > + mPciOverrideProtocol, > > > > > > > > > > + PciPolicy > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // return PCI Platform Protocol not found > > > > > > > > > > + // > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the Option ROM image and size from the > > Platform. > > > > > > > > > > + > > > > > > > > > > + It uses the PCI_IO_DEVICE internal fields are used to store Op= ROM > > > > > image/size > > > > > > > > > > + > > > > > > > > > > + @param Controller An EFI handle for the PCI bus controller= . > > > > > > > > > > + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO de= vice > > to > > > > be > > > > > registered. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The option ROM was available fo= r this > > device > > > > > and loaded into memory. > > > > > > > > > > + @retval EFI_NOT_FOUND No option ROM was available for= this > > > > device. > > > > > > > > > > + @retval EFI_OUT_OF_RESOURCES No memory was available to load > > the > > > > > option ROM. > > > > > > > > > > + @retval EFI_DEVICE_ERROR An error occurred in obtaining = the > > option > > > > > ROM. > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPlatformPciOptionRom ( > > > > > > > > > > + IN EFI_HANDLE Controller, > > > > > > > > > > + IN PCI_IO_DEVICE *PciIoDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + VOID *PlatformOpRomBuffer; > > > > > > > > > > + UINTN PlatformOpRomSize; > > > > > > > > > > + > > > > > > > > > > + if (mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol2->GetPciRom ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciPlatformProtocol2, > > > > > > > > > > + PciIoDevice->Handle, > > > > > > > > > > + &PlatformOpRomBuffer, > > > > > > > > > > + &PlatformOpRomSize > > > > > > > > > > + ); > > > > > > > > > > + } else if (mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + Status =3D mPciOverrideProtocol2->GetPciRom ( > > > > > > > > > > + > > > > > (EFI_PCI_PLATFORM_PROTOCOL*)mPciOverrideProtocol2, > > > > > > > > > > + PciIoDevice->Handle, > > > > > > > > > > + &PlatformOpRomBuffer, > > > > > > > > > > + &PlatformOpRomSize > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + if (mPciPlatformProtocol !=3D NULL) { > > > > > > > > > > + Status =3D mPciPlatformProtocol->GetPciRom ( > > > > > > > > > > + mPciPlatformProtocol, > > > > > > > > > > + PciIoDevice->Handle, > > > > > > > > > > + &PlatformOpRomBuffer, > > > > > > > > > > + &PlatformOpRomSize > > > > > > > > > > + ); > > > > > > > > > > + } else if (mPciOverrideProtocol !=3D NULL) { > > > > > > > > > > + Status =3D mPciOverrideProtocol->GetPciRom ( > > > > > > > > > > + mPciOverrideProtocol, > > > > > > > > > > + PciIoDevice->Handle, > > > > > > > > > > + &PlatformOpRomBuffer, > > > > > > > > > > + &PlatformOpRomSize > > > > > > > > > > + ); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // return PCI Platform Protocol not found > > > > > > > > > > + // > > > > > > > > > > + return EFI_NOT_FOUND; > > > > > > > > > > + } > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (!EFI_ERROR (Status)) { > > > > > > > > > > + PciIoDevice->EmbeddedRom =3D FALSE; > > > > > > > > > > + PciIoDevice->RomSize =3D (UINT32)PlatformOpRomSize; > > > > > > > > > > + PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > > > > > > > > > > + PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > > > > > > > > > > + } > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine to indicate whether the given PCI device specif= ic > > policy > > > > > value > > > > > > > > > > + dictates to override the Max_Payload_Size to a particular valu= e, or > > set as > > > > > per > > > > > > > > > > + device capability. > > > > > > > > > > + > > > > > > > > > > + @param MPS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval TRUE Setup Max_Payload_Size as per device capabilit= y > > > > > > > > > > + FALSE override as per device-specific platform polic= y > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMpsAsPerDeviceCapability ( > > > > > > > > > > + IN UINT8 MPS > > > > > > > > > > +) > > > > > > > > > > +{ > > > > > > > > > > + if ( MPS =3D=3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO) { > > > > > > > > > > + return TRUE; > > > > > > > > > > + } else { > > > > > > > > > > + return FALSE; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine to indicate whether the given PCI device specif= ic > > policy > > > > > value > > > > > > > > > > + dictates to override the Max_Read_Req_Size to a particular val= ue, or > > set > > > > as > > > > > per > > > > > > > > > > + device capability. > > > > > > > > > > + > > > > > > > > > > + @param MRRS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval TRUE Setup Max_Read_Req_Size as per device capabili= ty > > > > > > > > > > + FALSE override as per device-specific platform polic= y > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMrrsAsPerDeviceCapability ( > > > > > > > > > > + IN UINT8 MRRS > > > > > > > > > > +) > > > > > > > > > > +{ > > > > > > > > > > + if ( MRRS =3D=3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO) { > > > > > > > > > > + return TRUE; > > > > > > > > > > + } else { > > > > > > > > > > + return FALSE; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Routine to translate the given device-specific platform policy= from > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI > > > > Base > > > > > Specification > > > > > > > > > > + Revision 4.0; for the PCI feature Max_Payload_Size. > > > > > > > > > > + > > > > > > > > > > + @param MPS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval Range values for the Max_Payload_Size as defin= ed in the > > > > PCI > > > > > > > > > > + Base Specification 4.0 > > > > > > > > > > +**/ > > > > > > > > > > +UINT8 > > > > > > > > > > +TranslateMpsSetupValueToPci ( > > > > > > > > > > + IN UINT8 MPS > > > > > > > > > > +) > > > > > > > > > > +{ > > > > > > > > > > + switch (MPS) { > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_128B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_256B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_256B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_512B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_512B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_1024B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_1024B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_2048B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_2048B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_4096B: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_4096B; > > > > > > > > > > + default: > > > > > > > > > > + return PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Routine to translate the given device-specific platform policy= from > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per > > PCI > > > > > Base Specification > > > > > > > > > > + Revision 4.0; for the PCI feature Max_Read_Req_Size. > > > > > > > > > > + > > > > > > > > > > + @param MRRS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval Range values for the Max_Read_Req_Size as defi= ned in > > the > > > > > PCI > > > > > > > > > > + Base Specification 4.0 > > > > > > > > > > +**/ > > > > > > > > > > +UINT8 > > > > > > > > > > +TranslateMrrsSetupValueToPci ( > > > > > > > > > > + IN UINT8 MRRS > > > > > > > > > > +) > > > > > > > > > > +{ > > > > > > > > > > + switch (MRRS) { > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_128B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_128B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_256B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_256B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_512B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_512B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_1024B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_1024B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_2048B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_2048B; > > > > > > > > > > + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_4096B: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_4096B; > > > > > > > > > > + default: > > > > > > > > > > + return PCIE_MAX_READ_REQ_SIZE_128B; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Generic routine to setup the PCI features as per its predeterm= ined > > > > > defaults. > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +SetupDefaultsDevicePlatformPolicy ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; > > > > > > > > > > + PciDevice->SetupMRRS =3D > > EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Intermediate routine to either get the PCI device specific pla= tform > > > > policies > > > > > > > > > > + through the PCI Platform Protocol, or its alias the PCI Overri= de > > Protocol. > > > > > > > > > > + > > > > > > > > > > + @param PciIoDevice A pointer to PCI_IO_DEVICE > > > > > > > > > > + @param PciPlatformProtocol A pointer to > > > > > EFI_PCI_PLATFORM_PROTOCOL2 > > > > > > > > > > + > > > > > > > > > > + @retval EFI_STATUS The direct status from the PCI Pla= tform > > Protocol > > > > > > > > > > + @retval EFI_SUCCESS if on returning predetermined PCI = features > > > > > defaults, > > > > > > > > > > + for the case when protocol returns= as > > EFI_UNSUPPORTED > > > > > > > > > > + to indicate PCI device exist and i= t has no platform > > > > > > > > > > + policy defined. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPciDevicePlatformPolicyEx ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciIoDevice, > > > > > > > > > > + IN EFI_PCI_PLATFORM_PROTOCOL2 *PciPlatformProtocol > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + EFI_PCI_PLATFORM_EXTENDED_POLICY PciPlatformExtendedPolicy; > > > > > > > > > > + EFI_STATUS Status; > > > > > > > > > > + > > > > > > > > > > + ZeroMem ( &PciPlatformExtendedPolicy, sizeof > > > > > (EFI_PCI_PLATFORM_EXTENDED_POLICY)); > > > > > > > > > > + Status =3D PciPlatformProtocol->GetDevicePolicy ( > > > > > > > > > > + PciPlatformProtocol, > > > > > > > > > > + PciIoDevice->Handle, > > > > > > > > > > + &PciPlatformExtendedPolicy > > > > > > > > > > + ); > > > > > > > > > > + // > > > > > > > > > > + // platform chipset policies are returned for this PCI device > > > > > > > > > > + // > > > > > > > > > > + if (!EFI_ERROR(Status)) { > > > > > > > > > > + PciIoDevice->SetupMPS =3D PciPlatformExtendedPolicy.DeviceCt= lMPS; > > > > > > > > > > + PciIoDevice->SetupMRRS =3D > > PciPlatformExtendedPolicy.DeviceCtlMRRS; > > > > > > > > > > + } > > > > > > > > > > + // > > > > > > > > > > + // platform chipset policies are not provided for this PCI dev= ice > > > > > > > > > > + // > > > > > > > > > > + if (EFI_ERROR(Status) =3D=3D EFI_UNSUPPORTED) { > > > > > > > > > > + // > > > > > > > > > > + // let the enumeration happen as per the PCI standard way > > > > > > > > > > + // > > > > > > > > > > + SetupDefaultsDevicePlatformPolicy ( PciIoDevice); > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + return Status; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Gets the PCI device-specific platform policy from the PCI Plat= form > > > > Protocol. > > > > > > > > > > + If no PCI Platform protocol is published than setup the PCI fe= ature to > > > > > predetermined > > > > > > > > > > + defaults, in order to align all the PCI devices in the PCI hie= rarchy, as > > > > > applicable. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to PCI_IO_DEVICE > > > > > > > > > > + > > > > > > > > > > + @retval EFI_STATUS The direct status from the PCI Platform > > Protocol > > > > > > > > > > + @retval EFI_SUCCESS On return of predetermined PCI features > > defaults, > > > > > for > > > > > > > > > > + the case when protocol returns as EFI_UN= SUPPORTED to > > > > > > > > > > + indicate PCI device exist and it has no = platform policy > > > > > > > > > > + defined. Also, on returns when no PCI Pl= atform Protocol > > > > > > > > > > + exist. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPciDevicePlatformPolicy ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ) > > > > > > > > > > +{ > > > > > > > > > > + if ( mPciPlatformProtocol2 !=3D NULL) { > > > > > > > > > > + return GetPciDevicePlatformPolicyEx ( PciDevice, > > > > mPciPlatformProtocol2); > > > > > > > > > > + } else if (mPciOverrideProtocol2 !=3D NULL) { > > > > > > > > > > + return GetPciDevicePlatformPolicyEx ( PciDevice, > > > > mPciOverrideProtocol2); > > > > > > > > > > + } else { > > > > > > > > > > + // > > > > > > > > > > + // new PCI Platform Protocol 2 is not installed; let the enu= meration > > > > > happen > > > > > > > > > > + // as per PCI standard way > > > > > > > > > > + // > > > > > > > > > > + SetupDefaultsDevicePlatformPolicy ( PciDevice); > > > > > > > > > > + return EFI_SUCCESS; > > > > > > > > > > + } > > > > > > > > > > +} > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > new file mode 100644 > > > > > index 0000000000..d54e46b950 > > > > > --- /dev/null > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > @@ -0,0 +1,193 @@ > > > > > +/** @file > > > > > > > > > > + This file encapsulate the usage of PCI Platform Protocol > > > > > > > > > > + > > > > > > > > > > + This file define the necessary hooks used to obtain the platfo= rm > > > > > > > > > > + level data and policies which could be used in the PCI Enumera= tion > > > > phases > > > > > > > > > > + > > > > > > > > > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > > > > > > > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > +#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_ > > > > > > > > > > +#define _EFI_PCI_PLATFORM_SUPPORT_H_ > > > > > > > > > > + > > > > > > > > > > +#include "PciBus.h" > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the PCI Platform Protocol published by > > platform > > > > > driver > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +VOID > > > > > > > > > > +GetPciPlatformProtocol ( > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function indicates the presence of PCI Platform driver > > > > > > > > > > + @retval TRUE or FALSE > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +CheckPciPlatformProtocolInstall ( > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Provides the hooks from the PCI bus driver to every PCI contro= ller > > > > > (device/function) at various > > > > > > > > > > + stages of the PCI enumeration process that allow the host brid= ge > > driver > > > > to > > > > > preinitialize individual > > > > > > > > > > + PCI controllers before enumeration. > > > > > > > > > > + > > > > > > > > > > + This function is called during the PCI enumeration process. No= specific > > > > > action is expected from this > > > > > > > > > > + member function. It allows the host bridge driver to preinitia= lize > > > > individual > > > > > PCI controllers before > > > > > > > > > > + enumeration. > > > > > > > > > > + > > > > > > > > > > + @param[in] HostBridgeHandle The associated PCI host bridge > > handle. > > > > > > > > > > + @param[in] RootBridgeHandle The associated PCI root bridge > > handle. > > > > > > > > > > + @param[in] RootBridgePciAddress The address of the PCI device = on > > the > > > > > PCI bus. > > > > > > > > > > + @param[in] Phase The phase of the PCI controller enum= eration. > > > > > > > > > > + @param[in] ExecPhase Defines the execution phase of the P= CI > > chipset > > > > > driver. > > > > > > > > > > + > > > > > > > > > > + @retval Status returns the status from the PCI Plat= form > > protocol as > > > > is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciPlatformPreprocessController ( > > > > > > > > > > + IN EFI_HANDLE HostBridgeHan= dle, > > > > > > > > > > + IN EFI_HANDLE RootBridgeHan= dle, > > > > > > > > > > + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS > > > > > RootBridgePciAddress, > > > > > > > > > > + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, > > > > > > > > > > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function notifies the PCI Platform driver about the PCI h= ost > > bridge > > > > > resource > > > > > > > > > > + allocation phase and PCI execution phase. > > > > > > > > > > + > > > > > > > > > > + @param[in] HostBridge The handle of the host bridge contr= oller. > > > > > > > > > > + @param[in] Phase The phase of the PCI bus enumeratio= n. > > > > > > > > > > + @param[in] ExecPhase Defines the execution phase of the = PCI > > > > chipset > > > > > driver. > > > > > > > > > > + @retval Status returns the status from the PCI Pl= atform > > protocol > > > > as > > > > > is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciPlatformNotifyPhase ( > > > > > > > > > > + IN EFI_HANDLE HostBridge= Handle, > > > > > > > > > > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, > > > > > > > > > > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the PCI platform policy. > > > > > > > > > > + > > > > > > > > > > + @param PciPolicy pointer to the legacy > > EFI_PCI_PLATFORM_POLICY > > > > > > > > > > + @retval Status returns the status from the PCI Platform= protocol > > as is > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +PciGetPlatformPolicy ( > > > > > > > > > > + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + This function retrieves the Option ROM image and size from the > > Platform. > > > > > > > > > > + > > > > > > > > > > + It uses the PCI_IO_DEVICE internal fields are used to store Op= ROM > > > > > image/size > > > > > > > > > > + > > > > > > > > > > + @param Controller An EFI handle for the PCI bus controller= . > > > > > > > > > > + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO de= vice > > to > > > > be > > > > > registered. > > > > > > > > > > + > > > > > > > > > > + @retval EFI_SUCCESS The option ROM was available fo= r this > > device > > > > > and loaded into memory. > > > > > > > > > > + @retval EFI_NOT_FOUND No option ROM was available for= this > > > > device. > > > > > > > > > > + @retval EFI_OUT_OF_RESOURCES No memory was available to load > > the > > > > > option ROM. > > > > > > > > > > + @retval EFI_DEVICE_ERROR An error occurred in obtaining = the > > option > > > > > ROM. > > > > > > > > > > + > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPlatformPciOptionRom ( > > > > > > > > > > + IN EFI_HANDLE Controller, > > > > > > > > > > + IN PCI_IO_DEVICE *PciIoDevice > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Gets the PCI device-specific platform policy from the PCI Plat= form > > > > Protocol. > > > > > > > > > > + If no PCI Platform protocol is published than setup the PCI fe= ature to > > > > > predetermined > > > > > > > > > > + defaults, in order to align all the PCI devices in the PCI hie= rarchy, as > > > > > applicable. > > > > > > > > > > + > > > > > > > > > > + @param PciDevice A pointer to PCI_IO_DEVICE > > > > > > > > > > + > > > > > > > > > > + @retval EFI_STATUS The direct status from the PCI Platform > > Protocol > > > > > > > > > > + @retval EFI_SUCCESS On return of predetermined PCI features > > defaults, > > > > > for > > > > > > > > > > + the case when protocol returns as EFI_UN= SUPPORTED to > > > > > > > > > > + indicate PCI device exist and it has no = platform policy > > > > > > > > > > + defined. Also, on returns when no PCI Pl= atform Protocol > > > > > > > > > > + exist. > > > > > > > > > > +**/ > > > > > > > > > > +EFI_STATUS > > > > > > > > > > +GetPciDevicePlatformPolicy ( > > > > > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > > > > > + ); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine to indicate whether the given PCI device specif= ic > > policy > > > > > value > > > > > > > > > > + dictates to override the Max_Payload_Size to a particular valu= e, or > > set as > > > > > per > > > > > > > > > > + device capability. > > > > > > > > > > + > > > > > > > > > > + @param MPS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval TRUE Setup Max_Payload_Size as per device capabilit= y > > > > > > > > > > + FALSE override as per device-specific platform polic= y > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMpsAsPerDeviceCapability ( > > > > > > > > > > + IN UINT8 MPS > > > > > > > > > > +); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Helper routine to indicate whether the given PCI device specif= ic > > policy > > > > > value > > > > > > > > > > + dictates to override the Max_Read_Req_Size to a particular val= ue, or > > set > > > > as > > > > > per > > > > > > > > > > + device capability. > > > > > > > > > > + > > > > > > > > > > + @param MRRS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval TRUE Setup Max_Read_Req_Size as per device capabili= ty > > > > > > > > > > + FALSE override as per device-specific platform polic= y > > > > > > > > > > +**/ > > > > > > > > > > +BOOLEAN > > > > > > > > > > +SetupMrrsAsPerDeviceCapability ( > > > > > > > > > > + IN UINT8 MRRS > > > > > > > > > > +); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Routine to translate the given device-specific platform policy= from > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI > > > > Base > > > > > Specification > > > > > > > > > > + Revision 4.0; for the PCI feature Max_Payload_Size. > > > > > > > > > > + > > > > > > > > > > + @param MPS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval Range values for the Max_Payload_Size as defin= ed in the > > > > PCI > > > > > > > > > > + Base Specification 4.0 > > > > > > > > > > +**/ > > > > > > > > > > +UINT8 > > > > > > > > > > +TranslateMpsSetupValueToPci ( > > > > > > > > > > + IN UINT8 MPS > > > > > > > > > > +); > > > > > > > > > > + > > > > > > > > > > +/** > > > > > > > > > > + Routine to translate the given device-specific platform policy= from > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per > > PCI > > > > > Base Specification > > > > > > > > > > + Revision 4.0; for the PCI feature Max_Read_Req_Size. > > > > > > > > > > + > > > > > > > > > > + @param MRRS Input device-specific policy should be in term= s of > > type > > > > > > > > > > + EFI_PCI_CONF_MAX_READ_REQ_SIZE > > > > > > > > > > + > > > > > > > > > > + @retval Range values for the Max_Read_Req_Size as defi= ned in > > the > > > > > PCI > > > > > > > > > > + Base Specification 4.0 > > > > > > > > > > +**/ > > > > > > > > > > +UINT8 > > > > > > > > > > +TranslateMrrsSetupValueToPci ( > > > > > > > > > > + IN UINT8 MRRS > > > > > > > > > > +); > > > > > > > > > > +#endif > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > > > > > index 4969ee0f64..755423f77b 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > > > > > @@ -198,20 +198,7 @@ CalculateApertureIo16 ( > > > > > // > > > > > > > > > > Status =3D EFI_NOT_FOUND; > > > > > > > > > > PciPolicy =3D 0; > > > > > > > > > > - if (gPciPlatformProtocol !=3D NULL) { > > > > > > > > > > - Status =3D gPciPlatformProtocol->GetPlatformPolicy ( > > > > > > > > > > - gPciPlatformProtocol, > > > > > > > > > > - &PciPolicy > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > - > > > > > > > > > > - if (EFI_ERROR (Status) && gPciOverrideProtocol !=3D NULL) { > > > > > > > > > > - Status =3D gPciOverrideProtocol->GetPlatformPolicy ( > > > > > > > > > > - gPciOverrideProtocol, > > > > > > > > > > - &PciPolicy > > > > > > > > > > - ); > > > > > > > > > > - } > > > > > > > > > > - > > > > > > > > > > + Status =3D PciGetPlatformPolicy ( &PciPolicy); > > > > > > > > > > if (!EFI_ERROR (Status)) { > > > > > > > > > > if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) !=3D 0) { > > > > > > > > > > mReserveIsaAliases =3D TRUE; > > > > > > > > > > diff --git a/MdeModulePkg/MdeModulePkg.dec > > > > > b/MdeModulePkg/MdeModulePkg.dec > > > > > index 17beb45235..7bcbe5a3ea 100644 > > > > > --- a/MdeModulePkg/MdeModulePkg.dec > > > > > +++ b/MdeModulePkg/MdeModulePkg.dec > > > > > @@ -1026,6 +1026,16 @@ > > > > > # @Prompt Enable UEFI Stack Guard. > > > > > > > > > > > > > > > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0 > > > > > x30001055 > > > > > > > > > > > > > > > > > > > > + ## This PCD is to indicate the PCI Bus driver to setup other n= ew PCI > > > > > features. > > > > > > > > > > + # Each PCI feature is represented by its mask bit position an= d it > > > > configures > > > > > > > > > > + # if that bit is set. > > > > > > > > > > + # > > > > > > > > > > + # Bit 0 - if set, the PCI Bus driver programs the device's > > > > > Max_Payload_Size.
> > > > > > > > > > + # Bit 1 - if set, the PCI Bus driver programs the device's > > > > > Max_Read_Req_Size.
> > > > > > > > > > + # Bit 2 to 31 - Reserved for future use by the PCI Bus drive= r.
> > > > > > > > > > + # @Prompt The UEFI PCU Bus driver enables the new set of other= PCI > > > > > Features. > > > > > > > > > > + > > > > > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdOtherPciFeatures|0x00000003|UIN > > > > > T32|0x30001056 > > > > > > > > > > + > > > > > > > > > > [PcdsFixedAtBuild, PcdsPatchableInModule] > > > > > > > > > > ## Dynamic type PCD can be registered callback function for Pc= d > > setting > > > > > action. > > > > > > > > > > # PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum > > > > > number of callback function > > > > > > > > > > -- > > > > > 2.21.0.windows.1