From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.5401.1573186227074038467 for ; Thu, 07 Nov 2019 20:10:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 20:10:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,280,1569308400"; d="scan'208";a="233504180" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga002.fm.intel.com with ESMTP; 07 Nov 2019 20:10:26 -0800 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 20:10:25 -0800 Received: from bgsmsx109.gar.corp.intel.com (10.223.4.211) by FMSMSX157.amr.corp.intel.com (10.18.116.73) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 20:10:25 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.199]) by BGSMSX109.gar.corp.intel.com ([169.254.10.209]) with mapi id 14.03.0439.000; Fri, 8 Nov 2019 09:40:22 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Thread-Index: AQHVkULbej08Z3wkQ0uCOUT+82//4KeAsYpA Date: Fri, 8 Nov 2019 04:10:22 +0000 Message-ID: <95C5C2B113DE604FB208120C742E982457909893@BGSMSX101.gar.corp.intel.com> References: <15D34310CBE1F8C3.20918@groups.io> In-Reply-To: <15D34310CBE1F8C3.20918@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzg4MDNhMjktNmFkMS00MWNiLTkzYzQtYjQ0ZjM5MzE3MTE1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoicHZNZGlrZ0t5S3pzSGtQWk45dHBTVkNDQlA5cUpPVENhM1AwT1djY0JrcnUwREZmN1wvTkJFWHV5dithcFFIVHIifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jian, Hao, and Ray; Kindly review my patch set from 1 to 12 to enhance the PCI Bus driver to su= pport the new PCI features.. Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Saturday, November 2, 2019 11:30 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 00/12] > New PCI features - MPS, MRRS, RO, NS, CTO >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 >=20 > The EDK2 Kernel PciBusDxe driver is enhanced to enable the configuration = of PCI > features like > (1) Max_Payload_Size > (2) Max_Read_Req_Size > (3) Relax Ordering > (4) No-Snoop > (5) Completion Timeout >=20 > Max_Payload_Size:- The PCI Device Control register provides this feature > register field which controls the maximum data packet (TLP) size that a P= CI > device should maintain as a requester. The PCI Bus driver is required to = maintain > a highest common value supported by all the PCI devices in a PCIe hierarc= hy, > especially in case of isochronous applications. >=20 > Max_Read_Req_Size:- The PCI Device Control register provides this feature > register field which controls the maximum memory read request size that a= PCI > device should maintain as a requester. The PCI Bus driver is required to = maintain > a common value, same as Max_Payload_Size, in case of isochronous > applications only; or else, it should maintain the user requested value u= niformly > in a PCIe hierarchy (PCI root port and its downstream devices). >=20 > Relax Ordering:- The PCI Device Control register has the enabling of Rela= x > Ordering functionality register field (bit 4). If this bit is Set, the PC= I Function is > permitted to set the Relaxed Ordering bit in the Attributes field of tran= sactions it > initiates that do not require strong write ordering (see PCI Base Specifi= cation 4, > Section 2.2.6.4 and Sect- ion 2.4). Any supporting PCI function is expect= ed have > this bit enabled as per its hardware default; the code enhancement is to = enable / > disable as per the PCI device policy provided by the platform firmware. I= f no > device policy override is provided than it shall be ignored by the PCI Bu= s driver > for that PCI function. >=20 > No-Snoop:- The PCI Device Control register has the enabling of No-Snoop > functionality register field (bit 11). If this bit is Set, the PCI Functi= on is permitted > to Set the No Snoop bit in the Requester Attributes of transactions it in= itiates > that do not require hardware enforced cache coherency (see PCI Base > Specification 4, Section 2.2.6.5). Any supporting PCI function is expecte= d have > this bit enabled as per its hardware default; the code enhancement is to = enable / > disable as per the PCI device policy provided by the platform firmware. I= f no > device policy override is provided than it shall be ignored by the PCI Bu= s driver > for that PCI function. >=20 > Completion Timeout:- The PCI Device Control 2 register provides two regis= ter > fields based on its Device Capability 2 register; the CTO Ranges (bits [3= :0]) and > the disabling of CTO detection mechanism (bit 4). The software is permitt= ed to > change the CTO ranges and enable/disable the CTO detection mechanism any > time. The code enhancement here is to override these register fields as p= er the > platform device policy. If no device policy override is provided than it = shall be > ignored by the PCI Bus driver for that PCI function. >=20 > The PCI Base Specification 4 Revision 1 contains detailed information abo= ut > these features. The EDK2 PCI Bus driver needs to enable the configuration= of > these features as per the PCI Base specification. >=20 > The EDK2 PCI Bus driver also needs to take the PCI device-specific platfo= rm > policy into the consideration while programming these features; thus the = code > changes to support these, is explicitly dependent on the new PCI Platform > Protocol interface definition defined in the below > record:- > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 >=20 >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- >=20 > V2: Fixed message format and added feature change reference links > --- >=20 > Ashraf Javeed (12): > MdeModulePkg/PciBusDxe:New PCI features separation with PCD > PciBusDxe: Reorganize the PCI Platform Protocol usage code > PciBusDxe: Separation of the PCI device registration and start > PciBusDxe: Inclusion of new PCI Platform Protocol 2 > PciBusDxe: Setup sub-phases for PCI feature enumeration > PciBusDxe: Integration of setup for PCI feature enumeration > PciBusDxe: Record the PCI-Express Capability Structure > PciBusDxe: New PCI feature Max_Payload_Size > PciBusDxe: New PCI feature Max_Read_Req_Size > PciBusDxe: New PCI feature Relax Ordering > PciBusDxe: New PCI feature No-Snoop > PciBusDxe: New PCI feature Completion Timeout >=20 > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 +---------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 20 ++++++++-- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 9 ++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 233 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++-------------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 > ++++++++++++++++------------------------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 > ++++++++++------ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 2030 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 223 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 749 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 191 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +------ > MdeModulePkg/MdeModulePkg.dec | 22 +++++++++++ > 12 files changed, 3450 insertions(+), 238 deletions(-) create mode 1006= 44 > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > create mode 100644 MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > create mode 100644 MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > create mode 100644 MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h >=20 > -- > 2.21.0.windows.1 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. >=20 > View/Reply Online (#49883): https://edk2.groups.io/g/devel/message/49883 > Mute This Topic: https://groups.io/mt/40632595/1835458 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [ashraf.javeed@intel.c= om] > -=3D-=3D-=3D-=3D-=3D-=3D