From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.2347.1573615433114786190 for ; Tue, 12 Nov 2019 19:23:53 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2019 19:23:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,299,1569308400"; d="scan'208";a="194536705" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga007.jf.intel.com with ESMTP; 12 Nov 2019 19:23:52 -0800 Received: from fmsmsx608.amr.corp.intel.com (10.18.126.88) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 Nov 2019 19:23:51 -0800 Received: from fmsmsx608.amr.corp.intel.com (10.18.126.88) by fmsmsx608.amr.corp.intel.com (10.18.126.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 12 Nov 2019 19:23:51 -0800 Received: from bgsmsx105.gar.corp.intel.com (10.223.43.197) by fmsmsx608.amr.corp.intel.com (10.18.126.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 12 Nov 2019 19:23:51 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.49]) by BGSMSX105.gar.corp.intel.com ([169.254.3.118]) with mapi id 14.03.0439.000; Wed, 13 Nov 2019 08:53:49 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Thread-Index: AQHVkMZ6ykkEyYcgUUayO64yD2iJaKeIgbYw Date: Wed, 13 Nov 2019 03:23:48 +0000 Message-ID: <95C5C2B113DE604FB208120C742E982457917180@BGSMSX101.gar.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127AABF5037C.32624@groups.io> In-Reply-To: <15D3127AABF5037C.32624@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDlkMTJkYWUtZTUzMi00NTY5LWJmZTUtYjc5ZGMwMzc5YjQwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoia2p5TldYUFpZQnZoQ3lSM2ZESXczcWRcL2hmcWt3UXhiMDR2RWZYc0xzaGVVbFJSQklmanIrY3BMVzdEbDVMUGYifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch is also uploaded in the following Repo, for review:- https://github.com/ashrafj/edk2-staging/commit/ff68bb88bdb81d3921ebc7410c6= 9e52e9d2fdb0e Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Friday, November 1, 2019 8:40 PM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] > PciBusDxe: Reorganize the PCI Platform Protocol usage code >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 >=20 > The following legacy PCI Platform Protocol usage is reorganized in the s= eparate > source files:- > (1) PlatformPrepController > (2) PlatformNotify > (3) GetPlatformPolicy > (4) GetPciRom >=20 > This code changes are made to support the new PCI Platform Protocol alon= g > with the existing legacy interface in the PCI Bus driver. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 ++-----------= ---------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 3 +-- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 58 +++++++++++--= --- > ------------------------------------------ > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 > +++++++++++++++++++++++++++++++++---------------------------------------= --------- > ---------------------------------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 254 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 109 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +------------= -- > 8 files changed, 413 insertions(+), 190 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > index b020ce5..45cd64d 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > @@ -8,7 +8,7 @@ > PCI Root Bridges. So it means platform needs install PCI Root Bridge = IO > protocol for each > PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol= . >=20 > -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -34,8 +34,6 @@ BOOLEAN gFullEnu= meration =3D > TRUE; > UINT64 gAllOne =3D = 0xFFFFFFFFFFFFFFFFULL; > UINT64 gAllZero =3D = 0; >=20 > -EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; > -EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; > EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; >=20 >=20 > @@ -266,24 +264,7 @@ PciBusDriverBindingStart ( > // If PCI Platform protocol is available, get it now. > // If the platform implements this, it must be installed before BDS p= hase > // > - gPciPlatformProtocol =3D NULL; > - gBS->LocateProtocol ( > - &gEfiPciPlatformProtocolGuid, > - NULL, > - (VOID **) &gPciPlatformProtocol > - ); > - > - // > - // If PCI Platform protocol doesn't exist, try to Pci Override Protoc= ol. > - // > - if (gPciPlatformProtocol =3D=3D NULL) { > - gPciOverrideProtocol =3D NULL; > - gBS->LocateProtocol ( > - &gEfiPciOverrideProtocolGuid, > - NULL, > - (VOID **) &gPciOverrideProtocol > - ); > - } > + LocatePciPlatformProtocol (); >=20 > if (mIoMmuProtocol =3D=3D NULL) { > gBS->LocateProtocol ( > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 504a1b1..141c158 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -79,6 +79,7 @@ typedef enum { > #include "PciPowerManagement.h" > #include "PciHotPlugSupport.h" > #include "PciLib.h" > +#include "PciPlatformSupport.h" >=20 > #define VGABASE1 0x3B0 > #define VGALIMIT1 0x3BB > @@ -307,8 +308,6 @@ extern UINTN > gPciHostBridgeNumber; > extern EFI_HANDLE > gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]; > extern UINT64 gAllOne; > extern UINT64 gAllZero; > -extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtoc= ol; > -extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtoc= ol; > extern BOOLEAN mReserveIsaAliases; > extern BOOLEAN mReserveVgaAliases; >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > index 6dab970..4ce99ce 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -59,6 +59,8 @@ > PciBus.h > PciFeatureSupport.c > PciFeatureSupport.h > + PciPlatformSupport.c > + PciPlatformSupport.h >=20 > [Packages] > MdePkg/MdePkg.dec > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > index b7832c6..149a120 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > @@ -208,8 +208,6 @@ RegisterPciDevice ( > ) > { > EFI_STATUS Status; > - VOID *PlatformOpRomBuffer; > - UINTN PlatformOpRomSize; > EFI_PCI_IO_PROTOCOL *PciIo; > UINT8 Data8; > BOOLEAN HasEfiImage; > @@ -244,49 +242,16 @@ RegisterPciDevice ( > // > // Get the OpRom provided by platform > // > - if (gPciPlatformProtocol !=3D NULL) { > - Status =3D gPciPlatformProtocol->GetPciRom ( > - gPciPlatformProtocol, > - PciIoDevice->Handle, > - &PlatformOpRomBuffer, > - &PlatformOpRomSize > - ); > - if (!EFI_ERROR (Status)) { > - PciIoDevice->EmbeddedRom =3D FALSE; > - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSize; > - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > - // > - // For OpROM read from gPciPlatformProtocol: > - // Add the Rom Image to internal database for later PCI light e= numeration > - // > - PciRomAddImageMapping ( > - NULL, > - PciIoDevice->PciRootBridgeIo->SegmentNumber, > - PciIoDevice->BusNumber, > - PciIoDevice->DeviceNumber, > - PciIoDevice->FunctionNumber, > - PciIoDevice->PciIo.RomImage, > - PciIoDevice->PciIo.RomSize > - ); > - } > - } else if (gPciOverrideProtocol !=3D NULL) { > - Status =3D gPciOverrideProtocol->GetPciRom ( > - gPciOverrideProtocol, > - PciIoDevice->Handle, > - &PlatformOpRomBuffer, > - &PlatformOpRomSize > - ); > - if (!EFI_ERROR (Status)) { > - PciIoDevice->EmbeddedRom =3D FALSE; > - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSize; > - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > - // > - // For OpROM read from gPciOverrideProtocol: > - // Add the Rom Image to internal database for later PCI light e= numeration > - // > - PciRomAddImageMapping ( > + Status =3D GetPlatformPciOptionRom ( > + Controller, > + PciIoDevice > + ); > + if (!EFI_ERROR (Status)) { > + // > + // For OpROM read from the PCI Platform Protocol: > + // Add the Rom Image to internal database for later PCI light enu= meration > + // > + PciRomAddImageMapping ( > NULL, > PciIoDevice->PciRootBridgeIo->SegmentNumber, > PciIoDevice->BusNumber, > @@ -294,8 +259,7 @@ RegisterPciDevice ( > PciIoDevice->FunctionNumber, > PciIoDevice->PciIo.RomImage, > PciIoDevice->PciIo.RomSize > - ); > - } > + ); > } > } >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > index 8db1ebf..aef8a3b 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c > @@ -1003,7 +1003,7 @@ PciHostBridgeAdjustAllocation ( > Status =3D RejectPciDevice (PciResNode->PciDev); > if (Status =3D=3D EFI_SUCCESS) { > DEBUG (( > - EFI_D_ERROR, > + DEBUG_ERROR, > "PciBus: [%02x|%02x|%02x] was rejected due to resource conflict= ion.\n", > PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber= , > PciResNode->PciDev->FunctionNumber > )); > @@ -1746,7 +1746,7 @@ NotifyPhase ( >=20 > HostBridgeHandle =3D NULL; > RootBridgeHandle =3D NULL; > - if (gPciPlatformProtocol !=3D NULL) { > + if (CheckPciPlatformProtocolInstall()) { > // > // Get Host Bridge Handle. > // > @@ -1770,42 +1770,11 @@ NotifyPhase ( > // > // Call PlatformPci::PlatformNotify() if the protocol is present. > // > - gPciPlatformProtocol->PlatformNotify ( > - gPciPlatformProtocol, > - HostBridgeHandle, > - Phase, > - ChipsetEntry > - ); > - } else if (gPciOverrideProtocol !=3D NULL){ > - // > - // Get Host Bridge Handle. > - // > - PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle); > - > - // > - // Get the rootbridge Io protocol to find the host bridge handle > - // > - Status =3D gBS->HandleProtocol ( > - RootBridgeHandle, > - &gEfiPciRootBridgeIoProtocolGuid, > - (VOID **) &PciRootBridgeIo > - ); > - > - if (EFI_ERROR (Status)) { > - return EFI_NOT_FOUND; > - } > - > - HostBridgeHandle =3D PciRootBridgeIo->ParentHandle; > - > - // > - // Call PlatformPci::PhaseNotify() if the protocol is present. > - // > - gPciOverrideProtocol->PlatformNotify ( > - gPciOverrideProtocol, > - HostBridgeHandle, > - Phase, > - ChipsetEntry > - ); > + PciPlatformNotifyPhase ( > + HostBridgeHandle, > + Phase, > + ChipsetEntry > + ); > } >=20 > Status =3D PciResAlloc->NotifyPhase ( > @@ -1813,27 +1782,15 @@ NotifyPhase ( > Phase > ); >=20 > - if (gPciPlatformProtocol !=3D NULL) { > + if (CheckPciPlatformProtocolInstall()) { > // > // Call PlatformPci::PlatformNotify() if the protocol is present. > // > - gPciPlatformProtocol->PlatformNotify ( > - gPciPlatformProtocol, > - HostBridgeHandle, > - Phase, > - ChipsetExit > - ); > - > - } else if (gPciOverrideProtocol !=3D NULL) { > - // > - // Call PlatformPci::PhaseNotify() if the protocol is present. > - // > - gPciOverrideProtocol->PlatformNotify ( > - gPciOverrideProtocol, > - HostBridgeHandle, > - Phase, > - ChipsetExit > - ); > + PciPlatformNotifyPhase ( > + HostBridgeHandle, > + Phase, > + ChipsetExit > + ); > } >=20 > return Status; > @@ -1914,31 +1871,16 @@ PreprocessController ( > RootBridgePciAddress.Bus =3D Bus; > RootBridgePciAddress.ExtendedRegister =3D 0; >=20 > - if (gPciPlatformProtocol !=3D NULL) { > - // > - // Call PlatformPci::PrepController() if the protocol is present. > - // > - gPciPlatformProtocol->PlatformPrepController ( > - gPciPlatformProtocol, > - HostBridgeHandle, > - RootBridgeHandle, > - RootBridgePciAddress, > - Phase, > - ChipsetEntry > - ); > - } else if (gPciOverrideProtocol !=3D NULL) { > - // > - // Call PlatformPci::PrepController() if the protocol is present. > - // > - gPciOverrideProtocol->PlatformPrepController ( > - gPciOverrideProtocol, > - HostBridgeHandle, > - RootBridgeHandle, > - RootBridgePciAddress, > - Phase, > - ChipsetEntry > - ); > - } > + // > + // Call PlatformPci::PrepController() if the protocol is present. > + // > + PciPlatformPreprocessController ( > + HostBridgeHandle, > + RootBridgeHandle, > + RootBridgePciAddress, > + Phase, > + ChipsetEntry > + ); >=20 > Status =3D PciResAlloc->PreprocessController ( > PciResAlloc, > @@ -1947,31 +1889,16 @@ PreprocessController ( > Phase > ); >=20 > - if (gPciPlatformProtocol !=3D NULL) { > - // > - // Call PlatformPci::PrepController() if the protocol is present. > - // > - gPciPlatformProtocol->PlatformPrepController ( > - gPciPlatformProtocol, > - HostBridgeHandle, > - RootBridgeHandle, > - RootBridgePciAddress, > - Phase, > - ChipsetExit > - ); > - } else if (gPciOverrideProtocol !=3D NULL) { > - // > - // Call PlatformPci::PrepController() if the protocol is present. > - // > - gPciOverrideProtocol->PlatformPrepController ( > - gPciOverrideProtocol, > - HostBridgeHandle, > - RootBridgeHandle, > - RootBridgePciAddress, > - Phase, > - ChipsetExit > - ); > - } > + // > + // Call PlatformPci::PrepController() if the protocol is present. > + // > + PciPlatformPreprocessController ( > + HostBridgeHandle, > + RootBridgeHandle, > + RootBridgePciAddress, > + Phase, > + ChipsetExit > + ); >=20 > return EFI_SUCCESS; > } > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > new file mode 100644 > index 0000000..6f95794 > --- /dev/null > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > @@ -0,0 +1,254 @@ > +/** @file > + This file encapsulate the usage of PCI Platform Protocol > + > + This file define the necessary hooks used to obtain the platform > + level data and policies which could be used in the PCI Enumeration > + phases > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "PciBus.h" > + > +EFI_PCI_PLATFORM_PROTOCOL *mPciPlatformProtocol; > +EFI_PCI_OVERRIDE_PROTOCOL *mPciOverrideProtocol; > + > + > + > +/** > + This function retrieves the PCI Platform Protocol published by > +platform driver > + > +**/ > +VOID > +LocatePciPlatformProtocol ( > + ) > +{ > + mPciPlatformProtocol =3D NULL; > + gBS->LocateProtocol ( > + &gEfiPciPlatformProtocolGuid, > + NULL, > + (VOID **) &mPciPlatformProtocol > + ); > + > + // > + // If PCI Platform protocol doesn't exist, try to get Pci Override= Protocol. > + // > + if (mPciPlatformProtocol =3D=3D NULL) { > + mPciOverrideProtocol =3D NULL; > + gBS->LocateProtocol ( > + &gEfiPciOverrideProtocolGuid, > + NULL, > + (VOID **) &mPciOverrideProtocol > + ); > + } > +} > + > +/** > + This function indicates the presence of PCI Platform driver > + @retval TRUE or FALSE > +**/ > +BOOLEAN > +CheckPciPlatformProtocolInstall ( > + ) > +{ > + > + if (mPciPlatformProtocol !=3D NULL) { > + return TRUE; > + } else if (mPciOverrideProtocol !=3D NULL){ > + return TRUE; > + } > + > + return FALSE; > +} > + > +/** > + Provides the hooks from the PCI bus driver to every PCI controller > +(device/function) at various > + stages of the PCI enumeration process that allow the host bridge > +driver to preinitialize individual > + PCI controllers before enumeration. > + > + This function is called during the PCI enumeration process. No > + specific action is expected from this member function. It allows the > + host bridge driver to preinitialize individual PCI controllers before > enumeration. > + > + @param[in] HostBridgeHandle The associated PCI host bridge handle= . > + @param[in] RootBridgeHandle The associated PCI root bridge handle= . > + @param[in] RootBridgePciAddress The address of the PCI device on the = PCI > bus. > + @param[in] Phase The phase of the PCI controller enumeration= . > + @param[in] ExecPhase Defines the execution phase of the PCI chip= set > driver. > + > + @retval Status returns the status from the PCI Platform pr= otocol as is > + > +**/ > +EFI_STATUS > +PciPlatformPreprocessController ( > + IN EFI_HANDLE HostBridgeHandle, > + IN EFI_HANDLE RootBridgeHandle, > + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS > RootBridgePciAddress, > + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > + ) > +{ > + EFI_STATUS Status; > + if (mPciPlatformProtocol !=3D NULL) { > + // > + // Call PlatformPci::PrepController() if the protocol is present. > + // > + Status =3D mPciPlatformProtocol->PlatformPrepController ( > + mPciPlatformProtocol, > + HostBridgeHandle, > + RootBridgeHandle, > + RootBridgePciAddress, > + Phase, > + ExecPhase > + ); > + } else if (mPciOverrideProtocol !=3D NULL) { > + // > + // Call PlatformPci::PrepController() if the protocol is present. > + // > + Status =3D mPciOverrideProtocol->PlatformPrepController ( > + mPciOverrideProtocol, > + HostBridgeHandle, > + RootBridgeHandle, > + RootBridgePciAddress, > + Phase, > + ExecPhase > + ); > + } else { > + // > + // return PCI Platform Protocol not found > + // > + return EFI_NOT_FOUND; > + } > + return Status; > +} > + > +/** > + This function notifies the PCI Platform driver about the PCI host > +bridge resource > + allocation phase and PCI execution phase. > + > + @param[in] HostBridge The handle of the host bridge controller. > + @param[in] Phase The phase of the PCI bus enumeration. > + @param[in] ExecPhase Defines the execution phase of the PCI chi= pset > driver. > + @retval Status returns the status from the PCI Platform = protocol as is > + > +**/ > +EFI_STATUS > +PciPlatformNotifyPhase ( > + IN EFI_HANDLE HostBridgeHandle, > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > + ) > +{ > + EFI_STATUS Status; > + > + > + if (mPciPlatformProtocol !=3D NULL) { > + Status =3D mPciPlatformProtocol->PlatformNotify ( > + mPciPlatformProtocol, > + HostBridgeHandle, > + Phase, > + ExecPhase > + ); > + } else if (mPciOverrideProtocol !=3D NULL){ > + Status =3D mPciOverrideProtocol->PlatformNotify ( > + mPciOverrideProtocol, > + HostBridgeHandle, > + Phase, > + ExecPhase > + ); > + } else { > + // > + // return PCI Platform Protocol not found > + // > + return EFI_NOT_FOUND; > + } > + return Status; > +} > + > +/** > + This function retrieves the PCI platform policy. > + > + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY > + @retval Status returns the status from the PCI Platform protoc= ol as is > + > +**/ > +EFI_STATUS > +PciGetPlatformPolicy ( > + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy > + ) > +{ > + EFI_STATUS Status; > + if (mPciPlatformProtocol !=3D NULL) { > + Status =3D mPciPlatformProtocol->GetPlatformPolicy ( > + mPciPlatformProtocol, > + PciPolicy > + ); > + } > + > + if (mPciOverrideProtocol !=3D NULL) { > + Status =3D mPciOverrideProtocol->GetPlatformPolicy ( > + mPciOverrideProtocol, > + PciPolicy > + ); > + } else { > + // > + // return PCI Platform Protocol not found > + // > + return EFI_NOT_FOUND; > + } > + return Status; > +} > + > +/** > + This function retrieves the Option ROM image and size from the Platfo= rm. > + > + It uses the PCI_IO_DEVICE internal fields are used to store OpROM > + image/size > + > + @param Controller An EFI handle for the PCI bus controller. > + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to= be > registered. > + > + @retval EFI_SUCCESS The option ROM was available for this = device and > loaded into memory. > + @retval EFI_NOT_FOUND No option ROM was available for this d= evice. > + @retval EFI_OUT_OF_RESOURCES No memory was available to load the > option ROM. > + @retval EFI_DEVICE_ERROR An error occurred in obtaining the opt= ion > ROM. > + > +**/ > +EFI_STATUS > +GetPlatformPciOptionRom ( > + IN EFI_HANDLE Controller, > + IN PCI_IO_DEVICE *PciIoDevice > + ) > +{ > + EFI_STATUS Status; > + VOID *PlatformOpRomBuffer; > + UINTN PlatformOpRomSize; > + if (mPciPlatformProtocol !=3D NULL) { > + Status =3D mPciPlatformProtocol->GetPciRom ( > + mPciPlatformProtocol, > + PciIoDevice->Handle, > + &PlatformOpRomBuffer, > + &PlatformOpRomSize > + ); > + } else if (mPciOverrideProtocol !=3D NULL) { > + Status =3D mPciOverrideProtocol->GetPciRom ( > + mPciOverrideProtocol, > + PciIoDevice->Handle, > + &PlatformOpRomBuffer, > + &PlatformOpRomSize > + ); > + } else { > + // > + // return PCI Platform Protocol not found > + // > + return EFI_NOT_FOUND; > + } > + > + if (!EFI_ERROR (Status)) { > + PciIoDevice->EmbeddedRom =3D FALSE; > + PciIoDevice->RomSize =3D (UINT32)PlatformOpRomSize; > + PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; > + PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; > + } > + return Status; > +} > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > new file mode 100644 > index 0000000..c0d3b49 > --- /dev/null > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > @@ -0,0 +1,109 @@ > +/** @file > + This file encapsulate the usage of PCI Platform Protocol > + > + This file define the necessary hooks used to obtain the platform > + level data and policies which could be used in the PCI Enumeration > + phases > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > + > +#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_ > +#define _EFI_PCI_PLATFORM_SUPPORT_H_ > + > +/** > + This function retrieves the PCI Platform Protocol published by > +platform driver > + > +**/ > +VOID > +LocatePciPlatformProtocol ( > + ); > + > +/** > + This function indicates the presence of PCI Platform driver > + @retval TRUE or FALSE > +**/ > +BOOLEAN > +CheckPciPlatformProtocolInstall ( > + ); > + > + > +/** > + Provides the hooks from the PCI bus driver to every PCI controller > +(device/function) at various > + stages of the PCI enumeration process that allow the host bridge > +driver to preinitialize individual > + PCI controllers before enumeration. > + > + This function is called during the PCI enumeration process. No > + specific action is expected from this member function. It allows the > + host bridge driver to preinitialize individual PCI controllers before > enumeration. > + > + @param[in] HostBridgeHandle The associated PCI host bridge handle= . > + @param[in] RootBridgeHandle The associated PCI root bridge handle= . > + @param[in] RootBridgePciAddress The address of the PCI device on the = PCI > bus. > + @param[in] Phase The phase of the PCI controller enumeration= . > + @param[in] ExecPhase Defines the execution phase of the PCI chip= set > driver. > + > + @retval Status returns the status from the PCI Platform pr= otocol as is > + > +**/ > +EFI_STATUS > +PciPlatformPreprocessController ( > + IN EFI_HANDLE HostBridgeHandle, > + IN EFI_HANDLE RootBridgeHandle, > + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS > RootBridgePciAddress, > + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > + ); > + > +/** > + This function notifies the PCI Platform driver about the PCI host > +bridge resource > + allocation phase and PCI execution phase. > + > + @param[in] HostBridge The handle of the host bridge controller. > + @param[in] Phase The phase of the PCI bus enumeration. > + @param[in] ExecPhase Defines the execution phase of the PCI chi= pset > driver. > + @retval Status returns the status from the PCI Platform = protocol as is > + > +**/ > +EFI_STATUS > +PciPlatformNotifyPhase ( > + IN EFI_HANDLE HostBridgeHandle, > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_EXECUTION_PHASE ExecPhase > + ); > + > +/** > + This function retrieves the PCI platform policy. > + > + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY > + @retval Status returns the status from the PCI Platform protoc= ol as is > + > +**/ > +EFI_STATUS > +PciGetPlatformPolicy ( > + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy > + ); > + > +/** > + This function retrieves the Option ROM image and size from the Platfo= rm. > + > + It uses the PCI_IO_DEVICE internal fields are used to store OpROM > + image/size > + > + @param Controller An EFI handle for the PCI bus controller. > + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to= be > registered. > + > + @retval EFI_SUCCESS The option ROM was available for this = device and > loaded into memory. > + @retval EFI_NOT_FOUND No option ROM was available for this d= evice. > + @retval EFI_OUT_OF_RESOURCES No memory was available to load the > option ROM. > + @retval EFI_DEVICE_ERROR An error occurred in obtaining the opt= ion > ROM. > + > +**/ > +EFI_STATUS > +GetPlatformPciOptionRom ( > + IN EFI_HANDLE Controller, > + IN PCI_IO_DEVICE *PciIoDevice > + ); > + > +#endif > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > index 4969ee0..be6f42a 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c > @@ -198,20 +198,7 @@ CalculateApertureIo16 ( > // > Status =3D EFI_NOT_FOUND; > PciPolicy =3D 0; > - if (gPciPlatformProtocol !=3D NULL) { > - Status =3D gPciPlatformProtocol->GetPlatformPolicy ( > - gPciPlatformProtocol, > - &PciPolicy > - ); > - } > - > - if (EFI_ERROR (Status) && gPciOverrideProtocol !=3D NULL) { > - Status =3D gPciOverrideProtocol->GetPlatformPolicy ( > - gPciOverrideProtocol, > - &PciPolicy > - ); > - } > - > + Status =3D PciGetPlatformPolicy (&PciPolicy); > if (!EFI_ERROR (Status)) { > if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) !=3D 0) { > mReserveIsaAliases =3D TRUE; > -- > 2.21.0.windows.1 >=20 >=20 >=20