From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.2417.1573615783333212852 for ; Tue, 12 Nov 2019 19:29:43 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2019 19:29:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,299,1569308400"; d="scan'208";a="194537959" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga007.jf.intel.com with ESMTP; 12 Nov 2019 19:29:42 -0800 Received: from BGSMSX108.gar.corp.intel.com (10.223.4.192) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 Nov 2019 19:29:42 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.49]) by BGSMSX108.gar.corp.intel.com ([169.254.8.186]) with mapi id 14.03.0439.000; Wed, 13 Nov 2019 08:59:38 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Thread-Index: AQHVkMaDc9co8K5pNEClJvkVck+KjKeIg2Nw Date: Wed, 13 Nov 2019 03:29:38 +0000 Message-ID: <95C5C2B113DE604FB208120C742E982457917240@BGSMSX101.gar.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127C6DFCD4A7.12315@groups.io> In-Reply-To: <15D3127C6DFCD4A7.12315@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMWM2ZmIzNTgtZDY3ZS00OTVkLWE5YmQtMjA2N2M4NDUxMzA1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoid1wvTGkwQWduMlNBSm81MGg1SFd4cHJwWVRFMXBzOUZpaGt3VDk2WjZZczd4OFBYYjVUcFwvZVpiSWJORTZkbVwvZyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch is also uploaded in the following Repo, for review:- https://github.com/ashrafj/edk2-staging/commit/8b40bc5cf23c57ad468939b8444= 9a87c9d90b90a thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Friday, November 1, 2019 8:40 PM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] > PciBusDxe: Record the PCI-Express Capability Structure >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 >=20 > The code changes are made to record the PCI device's PCI-Express Capabil= ity > Structure register set during early PCI enumeration phase. > This data shall be used during PCI feature enumeration phase. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 6 +++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 > ++++++++++++++++++++++------------ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 51 > +++++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 78 insertions(+), 13 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 95a677b..dc29ef3 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -266,9 +266,13 @@ struct _PCI_IO_DEVICE { >=20 > BOOLEAN IsPciExp; > // > - // For SR-IOV > + // For PCI Express Capability List Structure > // > UINT8 PciExpressCapabilityOffset; > + PCI_CAPABILITY_PCIEXP PciExpStruct; > + // > + // For SR-IOV > + // > UINT32 AriCapabilityOffset; > UINT32 SrIovCapabilityOffset; > UINT32 MrIovCapabilityOffset; > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > index c7eafff..2343702 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > @@ -230,7 +230,7 @@ PciSearchDevice ( > PciIoDevice =3D NULL; >=20 > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > "PciBus: Discovered %s @ [%02x|%02x|%02x]\n", > IS_PCI_BRIDGE (Pci) ? L"PPB" : > IS_CARDBUS_BRIDGE (Pci) ? L"P2C" : > @@ -397,7 +397,7 @@ DumpPpbPaddingResource ( >=20 > if ((Type !=3D PciBarTypeUnknown) && ((ResourceType =3D=3D PciBarTy= peUnknown) > || (ResourceType =3D=3D Type))) { > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " Padding: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%l= x\n", > mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLe= n > )); > @@ -424,7 +424,7 @@ DumpPciBars ( > } >=20 > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " BAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;= \tOffset =3D > 0x%02x\n", > Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, > PciBarTypeMaxType)], > PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].= Length, > PciIoDevice->PciBar[Index].Offset @@ -437,13 +437,13 @@ DumpPciBars ( > } >=20 > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " VFBAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;= \tOffset =3D > 0x%02x\n", > Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, > PciBarTypeMaxType)], > PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice- > >VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset > )); > } > - DEBUG ((EFI_D_INFO, "\n")); > + DEBUG ((DEBUG_INFO, "\n")); > } >=20 > /** > @@ -1903,7 +1903,7 @@ PciParseBar ( > // Fix the length to support some special 64 bit BAR > // > if (Value =3D=3D 0) { > - DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM= 64 BAR > returns 0, change to 0xFFFFFFFF.\n")); > + DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of > + MEM64 BAR returns 0, change to 0xFFFFFFFF.\n")); > Value =3D (UINT32) -1; > } else { > Value |=3D ((UINT32)(-1) << HighBitSet32 (Value)); @@ -2153,7 += 2153,17 @@ > CreatePciIoDevice ( > NULL > ); > if (!EFI_ERROR (Status)) { > - PciIoDevice->IsPciExp =3D TRUE; > + PciIoDevice->IsPciExp =3D TRUE; > + // > + // read the PCI device's entire PCI Express Capability structure > + // > + PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint8, > + PciIoDevice->PciExpressCapabilityOffset, > + sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8), > + &PciIoDevice->PciExpStruct > + ); > } >=20 > if (PcdGetBool (PcdAriSupport)) { > @@ -2206,7 +2216,7 @@ CreatePciIoDevice ( > &Data32 > ); > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n", > Bridge->BusNumber, > Bridge->DeviceNumber, > @@ -2215,7 +2225,7 @@ CreatePciIoDevice ( > } > } >=20 > - DEBUG ((EFI_D_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDevice- > >AriCapabilityOffset)); > + DEBUG ((DEBUG_INFO, " ARI: CapOffset =3D 0x%x\n", > + PciIoDevice->AriCapabilityOffset)); > } > } >=20 > @@ -2325,12 +2335,12 @@ CreatePciIoDevice ( > PciIoDevice->ReservedBusNum =3D (UINT16)(EFI_PCI_BUS_OF_RID (Last= VF) - > Bus + 1); >=20 > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " SR-IOV: SupportedPageSize =3D 0x%x; SystemPageSize =3D 0x%x; = FirstVFOffset > =3D 0x%x;\n", > SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOf= fset > )); > DEBUG (( > - EFI_D_INFO, > + DEBUG_INFO, > " InitialVFs =3D 0x%x; ReservedBusNum =3D 0x%x; CapOffs= et =3D 0x%x\n", > PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevi= ce- > >SrIovCapabilityOffset > )); > @@ -2345,7 +2355,7 @@ CreatePciIoDevice ( > NULL > ); > if (!EFI_ERROR (Status)) { > - DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIoDevice- > >MrIovCapabilityOffset)); > + DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset =3D 0x%x\n", > + PciIoDevice->MrIovCapabilityOffset)); > } > } >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > index 9e6671d..df9e696 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > @@ -467,6 +467,14 @@ GetPciFeaturesConfigurationTable ( > return EFI_SUCCESS; > } >=20 > + // > + // The PCI features configuration table is not built for RCiEP, > + return NULL // if > + (PciDevice->PciExpStruct.Capability.Bits.DevicePortType =3D=3D \ > + PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) { > + *PciFeaturesConfigTable =3D NULL; > + return EFI_SUCCESS; > + } >=20 > if (IsDevicePathEnd (PciDevice->DevicePath)){ > // > @@ -575,6 +583,45 @@ IsPciRootPortEmpty ( } >=20 >=20 > +/** > + helper routine to dump the PCIe Device Port Type **/ VOID > +DumpDevicePortType ( > + IN UINT8 DevicePortType > + ) > +{ > + switch (DevicePortType){ > + case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT: > + DEBUG (( DEBUG_INFO, "PCIe endpoint found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT: > + DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_ROOT_PORT: > + DEBUG (( DEBUG_INFO, "PCIe Root Port found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT: > + DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT: > + DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE: > + DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE: > + DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT: > + DEBUG (( DEBUG_INFO, "RCiEP found\n")); > + break; > + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR: > + DEBUG (( DEBUG_INFO, "RC Event Collector found\n")); > + break; > + } > +} > + > /** > Process each PCI device as per the pltaform and device-specific poli= cy. >=20 > @@ -590,8 +637,12 @@ SetupDevicePciFeatures ( > ) > { > EFI_STATUS Status; > + PCI_REG_PCIE_CAPABILITY PcieCap; > OTHER_PCI_FEATURES_CONFIGURATION_TABLE > *OtherPciFeaturesConfigTable; >=20 > + PcieCap.Uint16 =3D PciDevice->PciExpStruct.Capability.Uint16; > + DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType); > + > OtherPciFeaturesConfigTable =3D NULL; > Status =3D GetPciFeaturesConfigurationTable (PciDevice, > &OtherPciFeaturesConfigTable); > if (EFI_ERROR( Status)) { > -- > 2.21.0.windows.1 >=20 >=20 >=20