From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.2445.1573615953054277248 for ; Tue, 12 Nov 2019 19:32:33 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2019 19:32:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,299,1569308400"; d="scan'208";a="404475365" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga005.fm.intel.com with ESMTP; 12 Nov 2019 19:32:32 -0800 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 Nov 2019 19:32:32 -0800 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 12 Nov 2019 19:32:31 -0800 Received: from bgsmsx102.gar.corp.intel.com (10.223.4.172) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 12 Nov 2019 19:32:31 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.49]) by BGSMSX102.gar.corp.intel.com ([169.254.2.60]) with mapi id 14.03.0439.000; Wed, 13 Nov 2019 09:02:29 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Thread-Index: AQHVkMaEPgAP6OSW4kCs+9b6p5LShqeIhETA Date: Wed, 13 Nov 2019 03:32:28 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579172E5@BGSMSX101.gar.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127E471DF360.32624@groups.io> In-Reply-To: <15D3127E471DF360.32624@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzAxZmRlNjktMmQ4OC00ZGVhLWFhMzUtOTNhNDU0YzkzMmM3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiczBcL3pIMjNCcE5RMnV5bk9HSFEwdkRKZlJJc2RydVF5VHN3cTRaTll2Z0FyanoxZ0tiWWJWRUFoUDVRMmVPZlMifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch is also uploaded in the following Repo for review:- https://github.com/ashrafj/edk2-staging/commit/8575d730644eda27a4b88888b0e= b05ee1f804b35 Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Friday, November 1, 2019 8:40 PM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] > PciBusDxe: New PCI feature Relax Ordering >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 >=20 > The code changes are made to enable the configuration of new PCI feature > Relax Ordering (OR), which enables the PCI function to initiate requests= if it does > not require strong write ordering for its transactions; as per the PCI B= ase > Specification 4 Revision 1. >=20 > The code changes are made to configure only those PCI devices which are > requested to override by platform through the new PCI Platform protocol > interface for device-specific policies. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 2 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 78 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 26 > ++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 44 > ++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 150 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 38abd20..9f017b7 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -82,6 +82,7 @@ typedef enum { > #include "PciHotPlugSupport.h" > #include "PciLib.h" > #include "PciPlatformSupport.h" > +#include "PciFeatureSupport.h" >=20 > #define VGABASE1 0x3B0 > #define VGALIMIT1 0x3BB > @@ -291,6 +292,7 @@ struct _PCI_IO_DEVICE { > // > UINT8 SetupMPS; > UINT8 SetupMRRS; > + PCI_FEATURE_POLICY SetupRO; > }; >=20 > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > index 614285f..a60cb42 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > @@ -911,6 +911,81 @@ OverrideMaxReadReqSize ( > return Status; > } >=20 > +/** > + Overrides the PCI Device Control register Relax Order register field; > +if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance= . > + > + @retval EFI_SUCCESS The data was read from or written to th= e PCI > device. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, > and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +OverrideRelaxOrder ( > + IN PCI_IO_DEVICE *PciDevice > + ) > +{ > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > + UINT32 Offset; > + EFI_STATUS Status; > + EFI_TPL OldTpl; > + > + PcieDev.Uint16 =3D 0; > + Offset =3D PciDevice->PciExpressCapabilityOffset + > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > + Status =3D PciDevice->PciIo.Pci.Read ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + if (EFI_ERROR(Status)){ > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) rea= d > error!", > + Offset > + )); > + return Status; > + } > + if (PciDevice->SetupRO.Override > + && PcieDev.Bits.RelaxedOrdering !=3D PciDevice->SetupRO.Act > + ) { > + PcieDev.Bits.RelaxedOrdering =3D PciDevice->SetupRO.Act; > + DEBUG (( DEBUG_INFO, "RO=3D%d,", PciDevice->SetupRO.Act)); > + > + // > + // Raise TPL to high level to disable timer interrupt while the wri= te operation > completes > + // > + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); > + > + Status =3D PciDevice->PciIo.Pci.Write ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + // > + // Restore TPL to its original level > + // > + gBS->RestoreTPL (OldTpl); > + > + if (!EFI_ERROR(Status)) { > + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.Uint16; > + } else { > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) w= rite > error!", > + Offset > + )); > + } > + } else { > + DEBUG (( DEBUG_INFO, "No write of RO,", PciDevice->SetupRO.Act)); > + } > + > + return Status; > +} > + > /** > helper routine to dump the PCIe Device Port Type **/ @@ -1122,6 +119= 7,9 > @@ ProgramDevicePciFeatures ( > if (SetupMaxReadReqSize ()) { > Status =3D OverrideMaxReadReqSize (PciDevice); > } > + if (SetupRelaxOrder ()) { > + Status =3D OverrideRelaxOrder (PciDevice); } > DEBUG (( DEBUG_INFO, "\n")); > return Status; > } > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > index 96ee6ff..5044dc2 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > @@ -40,6 +40,11 @@ typedef struct > _OTHER_PCI_FEATURES_CONFIGURATION_TABLE > OTHER_PCI_FEATURES_CONFI // typedef struct > _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST; >=20 > +// > +// define the data type for the PCI feature policy support // typedef > +struct _PCI_FEATURE_POLICY PCI_FEATURE_POLICY; > + > // > // Signature value for the PCI Root Port node // @@ -151,6 +156,27 @@ > typedef enum { >=20 > }PCI_FEATURE_CONFIGURATION_PHASE; >=20 > +// > +// declaration for the data type to harbor the PCI feature policies // > +struct _PCI_FEATURE_POLICY { > + // > + // if set, it indicates the feature should be enabled > + // if clear, it indicates the feature should be disabled > + // > + UINT8 Act : 1; > + // > + // this field will be specific to feature, it can be implementation > +specific > + // or it can be reserved and remain unused > + // > + UINT8 Support : 6; > + // > + // if set indicates override the feature policy defined by the > +members above > + // if clear it indicates that this feature policy should be ignored > +completely > + // this means the above two members should not be used > + // > + UINT8 Override : 1; > +}; >=20 > /** > Main routine to indicate platform selection of any of the other PCI f= eatures > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > index f032b5d..f1e7039 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > @@ -470,6 +470,45 @@ TranslateMrrsSetupValueToPci ( > } > } >=20 > +/** > + Routine to set the device-specific policy for the PCI feature Relax > +Ordering > + > + @param RelaxOrder value corresponding to data type > EFI_PCI_CONF_RELAX_ORDER > + @param PciDevice A pointer to PCI_IO_DEVICE > +**/ > +VOID > +SetDevicePolicyRelaxOrder ( > + IN EFI_PCI_CONF_RELAX_ORDER RelaxOrder, > + OUT PCI_IO_DEVICE *PciDevice > + ) > +{ > + // > + // implementation specific rules for the usage of PCI_FEATURE_POLICY > +members > + // exclusively for the PCI Feature Relax Ordering (RO) > + // > + // .Override =3D 0 to skip this PCI feature RO for the PCI device > + // .Override =3D 1 to program this RO PCI feature > + // .Act =3D 1 to enable the RO in the PCI device > + // .Act =3D 0 to disable the RO in the PCI device > + // > + switch (RelaxOrder) { > + case EFI_PCI_CONF_RO_AUTO: > + PciDevice->SetupRO.Override =3D 0; > + break; > + case EFI_PCI_CONF_RO_DISABLE: > + PciDevice->SetupRO.Override =3D 1; > + PciDevice->SetupRO.Act =3D 0; > + break; > + case EFI_PCI_CONF_RO_ENABLE: > + PciDevice->SetupRO.Override =3D 1; > + PciDevice->SetupRO.Act =3D 1; > + break; > + default: > + PciDevice->SetupRO.Override =3D 0; > + break; > + } > +} > + > /** > Generic routine to setup the PCI features as per its predetermined de= faults. > **/ > @@ -480,6 +519,7 @@ SetupDefaultsDevicePlatformPolicy ( { > PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; > PciDevice->SetupMRRS =3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; > + PciDevice->SetupRO.Override =3D 0; > } >=20 > /** > @@ -517,6 +557,10 @@ GetPciDevicePlatformPolicyEx ( > // > PciIoDevice->SetupMPS =3D PciPlatformExtendedPolicy.DeviceCtlMPS; > PciIoDevice->SetupMRRS =3D PciPlatformExtendedPolicy.DeviceCtlMRR= S; > + // > + // set device specific policy for Relax Ordering > + // > + SetDevicePolicyRelaxOrder > + (PciPlatformExtendedPolicy.DeviceCtlRelaxOrder, PciIoDevice); >=20 > DEBUG (( > DEBUG_INFO, "[device policy: platform]" > -- > 2.21.0.windows.1 >=20 >=20 >=20