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From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: "Ni, Ray" <ray.ni@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Wang, Jian J" <jian.j.wang@intel.com>, "Wu, Hao A" <hao.a.wu@intel.com>
Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration
Date: Wed, 18 Dec 2019 07:14:24 +0000	[thread overview]
Message-ID: <95C5C2B113DE604FB208120C742E98245797C292@BGSMSX101.gar.corp.intel.com> (raw)
In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C3A05B7@SHSMSX104.ccr.corp.intel.com>

Thanks for the review, Ray!
My response in line

> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Tuesday, December 17, 2019 5:26 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12]
> PciBusDxe: Setup sub-phases for PCI feature enumeration
> 
> Please check comments below.
> I may have more comments regarding to the four phases after I finish review of
> further patches.
> 
> Besides the comments below, I have a general comments to the debug
> message: can you please review the existing debug message in the PciBus driver
> and make sure your newly added debug message aligns to existing style. And try
> to use less lines of debug messages with still enough debug information.
Ok, will look into that.

> 
> > > +PRIMARY_ROOT_PORT_NODE                      *mPrimaryRootPortList;
> > > +
> > > +/**
> > > +  A global pointer to PCI_FEATURE_CONFIGURATION_COMPLETION_LIST,
> > > which
> > > +stores all
> > > +  the PCI Root Bridge instances that are enumerated for the other
> > > +PCI features,
> > > +  like MaxPayloadSize & MaxReadReqSize; during the the Start()
> > > +interface of the
> > > +  driver binding protocol. The records pointed by this pointer
> > > +would be destroyed
> > > +  when the DXE core invokes the Stop() interface.
> > > +**/
> > > +PCI_FEATURE_CONFIGURATION_COMPLETION_LIST
> > > *mPciFeaturesConfigurationCompletionList = NULL;
> 
> 1. Please follow existing linked list usage style. The first node in the list is an
> empty header node.
> 
> LIST_ENTRY   mPrimaryRootPortList;
> LIST_ENTRY   mPciFeaturesConfigurationCompletionList;
> 
Ok, will make the change when I incorporate the ECR 0.75 or greater version.

> > > +BOOLEAN
> > > +CheckPciFeatureConfigurationRecordExist (
> > > +  IN  PCI_IO_DEVICE                             *RootBridge,
> > > +  OUT PCI_FEATURE_CONFIGURATION_COMPLETION_LIST
> > > +**PciFeatureConfigRecord
> > > +  )
> 
> 2. Is this function to check whether the PCIE features under a root bridge is
> already initialized?
> Can you use the existing variable gFullEnumeration?
> The variable is set to TRUE when the enumeration is done to a host bridge in the
> first time.
> By using gFullEnumeration, the entire function is not needed.
> 
Ok, will look into this.

> > > +EFI_STATUS AddRootBridgeInPciFeaturesConfigCompletionList (
> > > +  IN PCI_IO_DEVICE          *RootBridge,
> > > +  IN BOOLEAN                ReEnumerationRequired
> > > +  )
> 
> 3. Same question as #2. I think by using gFullEnumeration, this function is not
> needed.
> 
OK

> 
> > > +BOOLEAN
> > > +IsPciRootPortEmpty (
> > > +  IN  PCI_IO_DEVICE                           *PciDevice
> > > +  )
> 
> 4. Please use IsListEmpty() directly from callers and remove this function.
> 
Will consider this.

> > > +**/
> > > +EFI_STATUS
> > > +EnumerateOtherPciFeatures (
> 
> 5. Can it be "EnumeratePcieFeatures"?
> 
Yes, with the change to ECR 0.75, this routine name shall be changed.

> > > +  IN PCI_IO_DEVICE          *RootBridge
> > > +  )
> > > +{
> > > +  EFI_STATUS            Status;
> > > +  UINTN                 OtherPciFeatureConfigPhase;
> > > +
> > > +  //
> > > +  // check on PCI features configuration is complete and
> > > + re-enumeration is required  //  if
> > > + (!CheckPciFeaturesConfigurationRequired
> > > + (RootBridge)) {
> > > +    return EFI_ALREADY_STARTED;
> > > +  }
> > > +
>  > > +  CHAR16                *Str;
> > > +  Str = ConvertDevicePathToText (
> > > +          DevicePathFromHandle (RootBridge->Handle),
> > > +          FALSE,
> > > +          FALSE
> > > +        );
> > > +  DEBUG ((DEBUG_INFO, "Enumerating PCI features for Root Bridge
> > > + %s\n", Str != NULL ? Str : L""));
> 
> 6. Please use DEBUG_CODE macro to include ConvertDevicePathToText() and
> DEBUG().
> Please remember to call FreePool().
> 
Ok, will can under DEBUG_CODE, and free pool is called in the end

> > > +
> > > +  for ( OtherPciFeatureConfigPhase = PciFeatureRootBridgeScan
> > > +      ; OtherPciFeatureConfigPhase <= PciFeatureConfigurationComplete
> > > +      ; OtherPciFeatureConfigPhase++
> > > +      ) {
> > > +    switch (OtherPciFeatureConfigPhase){
> > > +      case  PciFeatureRootBridgeScan:
> > > +        SetupPciFeaturesConfigurationDefaults ();
> > > +        //
> > > +        //first scan the entire root bridge heirarchy for the
> > > + primary PCI root
> > ports
> > > +        //
> > > +        RecordPciRootPortBridges (RootBridge);
> 
> 7. How about "RecordPciRootPorts (RootBridge)"? The "Bridges" suffix is a bit
> confusing.
> 
Fine, will change.

> > > +      case  PciFeatureGetDevicePolicy:
> > > +      case  PciFeatureSetupPhase:
> 
> 8. In SetupPciFeatures(), why do you need to call DeviceExist()?
> Did you see any case that a device is detected in the beginning of PciBus scan
> but is hidden when calling SetupPciFeatures()?
> 
Yes, that is the case; device detected during the beginning of PciBus scan appears to be hidden by the platform drivers, since numerous legacy callbacks are initiated at different phase of PCI enumeration to the PCI Host Bridge, and PciPlatform drivers.
This can be avoided if the PciBus driver is enhanced to check for PCI device existence before the publication of the PCI IO Protocol, and removal of the PCI_IO_DEVICE instance from the linked list.

> 9. In GetPciFeaturesConfigurationTable() when checking whether a PCI device
> belongs to a root port, we can use below simpler logic:
>   SizeOfPciDevicePath = GetDevicePathSize (PciDevicePath);
>   SizeOfRootPortDevicePath = GetDevicePathSize (RootPortPath);
>   if ((SizeOfRootPortDevicePath < SizeOfPciDevicePath) &&
>       CompareMem (PciDevicePath, RootPortPath, SizeOfRootPortDevicePath -
> END_DEVICE_PATH_LENGTH) == 0)) {
>     // PCI device belongs to the root port.
>   }
> 
Ok.

> > > +        Status = ProgramPciFeatures (RootBridge);
> 10. ProgramPcieFeatures()?
> 
OK

> > > +
> > > +  if (Str != NULL) {
> > > +    FreePool (Str);
> > > +  }
> 
> 11. OK the Str is freed here because Str is needed for other debug messages
> inside the function.
> 
Yes

> > > +  //
> > > +  // mark this root bridge as PCI features configuration complete,
> > > +and no new
> > > +  // enumeration is required
> > > +  //
> > > +  AddRootBridgeInPciFeaturesConfigCompletionList (RootBridge,
> > > +FALSE);
> 
> 12. Not needed.
> 
ok, after incorporating the logic of gFullEnumeration it won't be required

> > > +_PRIMARY_ROOT_PORT_NODE {
> 
> > > +  //
> > > +  // Signature header
> > > +  //
> > > +  UINT32                                    Signature;
> > > +  //
> > > +  // linked list pointers to next node
> > > +  //
> > > +  LIST_ENTRY                                NeighborRootPort;
> > > +  //
> > > +  // pointer to PCI_IO_DEVICE of the primary PCI Controller device
> > > +  //
> > > +  EFI_DEVICE_PATH_PROTOCOL                  *RootPortDevicePath;
> > > +  //
> > > +  // pointer to the corresponding PCI feature configuration Table
> > > +node
> > > +  // all the child PCI devices of the controller are aligned based
> > > +on this table
> > > +  //
> > > +  OTHER_PCI_FEATURES_CONFIGURATION_TABLE
> > > *OtherPciFeaturesConfigurationTable;
> > > +};
> 
> 13. Can you add the OTHER_PCI_FEATURES_CONFIGURATION_TABLE field to
> PCI_IO_DEVICE structure?
> So this structure PRIMARY_ROOT_PORT_NODE is not needed.
> 
I think it is better to maintain separately as this configuration table is confined to a group of PCI devices and for the RCiEP it is not applicable hence not required. Moreover, I am maintaining a variable for each PCIe feature in the PCI_IO_DEVICE; perhaps I can consider having just pointer of it....
 
> > > +struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST {
> 14. This structure is not needed if using gFullEnumeration.
Yes.

  reply	other threads:[~2019-12-18  7:14 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-01 15:09 [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe:New PCI features separation with PCD Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: Separation of the PCI device registration and start Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: Inclusion of new PCI Platform Protocol 2 Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: Integration of setup " Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI feature Max_Read_Req_Size Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI feature No-Snoop Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI feature Completion Timeout Javeed, Ashraf
     [not found] ` <15D3127A726D26A6.7420@groups.io>
2019-11-13  3:22   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe:New PCI features separation with PCD Javeed, Ashraf
2019-12-16 12:46     ` Ni, Ray
     [not found] ` <15D3127AABF5037C.32624@groups.io>
2019-11-13  3:23   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Javeed, Ashraf
2019-12-16 12:46     ` Ni, Ray
     [not found] ` <15D3127A98E21087.7420@groups.io>
2019-11-13  3:25   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: Separation of the PCI device registration and start Javeed, Ashraf
2019-12-17  1:38     ` Ni, Ray
2019-12-17  3:19       ` Javeed, Ashraf
2019-12-19  1:34         ` Ni, Ray
2019-12-19  4:12           ` Javeed, Ashraf
     [not found] ` <15D3127AAE5DC481.32624@groups.io>
2019-11-13  3:26   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: Inclusion of new PCI Platform Protocol 2 Javeed, Ashraf
     [not found] ` <15D3127B934F51D3.12315@groups.io>
2019-11-13  3:27   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Javeed, Ashraf
2019-12-17 11:56     ` Ni, Ray
2019-12-18  7:14       ` Javeed, Ashraf [this message]
2019-12-19  5:48         ` Ni, Ray
     [not found]         ` <15E1AFB3EABD031C.30484@groups.io>
2020-03-05 14:12           ` Ni, Ray
2020-03-16  9:33             ` Javeed, Ashraf
2020-03-16 14:00               ` Ni, Ray
2020-03-17  7:20                 ` Javeed, Ashraf
2020-03-17 15:36                   ` Ni, Ray
2020-04-20 13:22                     ` Javeed, Ashraf
2020-04-21  6:03                       ` Javeed, Ashraf
2020-04-21  6:22                         ` Javeed, Ashraf
2020-05-08  8:26                           ` Ni, Ray
     [not found] ` <15D3127BE430E7DA.31784@groups.io>
2019-11-13  3:28   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: Integration of setup " Javeed, Ashraf
2019-12-17 11:59     ` Ni, Ray
2019-12-18  7:15       ` Javeed, Ashraf
     [not found] ` <15D3127C6DFCD4A7.12315@groups.io>
2019-11-13  3:29   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Javeed, Ashraf
2019-12-17 12:03     ` Ni, Ray
2019-12-18  7:32       ` Javeed, Ashraf
     [not found] ` <15D3127D273722D4.32624@groups.io>
2019-11-13  3:30   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Javeed, Ashraf
2019-12-18  8:38     ` Ni, Ray
2019-12-18  9:10       ` Ni, Ray
2019-12-18 14:35         ` Javeed, Ashraf
2019-12-19  2:14           ` Ni, Ray
     [not found] ` <15D3127DA6E2D860.7420@groups.io>
2019-11-13  3:31   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI feature Max_Read_Req_Size Javeed, Ashraf
     [not found] ` <15D3127E471DF360.32624@groups.io>
2019-11-13  3:32   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Javeed, Ashraf
     [not found] ` <15D3127EB6ED8506.12315@groups.io>
2019-11-13  3:33   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI feature No-Snoop Javeed, Ashraf
     [not found] ` <15D3127F5541064B.31784@groups.io>
2019-11-13  3:34   ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI feature Completion Timeout Javeed, Ashraf

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