From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: "Ni, Ray" <ray.ni@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Wang, Jian J" <jian.j.wang@intel.com>, "Wu, Hao A" <hao.a.wu@intel.com>
Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure
Date: Wed, 18 Dec 2019 07:32:44 +0000 [thread overview]
Message-ID: <95C5C2B113DE604FB208120C742E98245797C2C2@BGSMSX101.gar.corp.intel.com> (raw)
In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C3A05E7@SHSMSX104.ccr.corp.intel.com>
> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Tuesday, December 17, 2019 5:34 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12]
> PciBusDxe: Record the PCI-Express Capability Structure
>
> 2 minor comments.
>
> And I suggest you don't change EFI_D_xxx in this patch. Or you could change in a
> separate patch.
>
The below patch check script fails, if I don't change it...
/Git/Tianocore/edk2/BaseTools/Scripts/PatchCheck.py
> > > + PCI_CAPABILITY_PCIEXP PciExpStruct;
>
> 1. to align "Pci" which buffers the PCI config space, this can be simply "PciExp".
>
Ok
> > > + //
> > > + // For SR-IOV
> > > + //
> > > UINT32 AriCapabilityOffset;
> > > UINT32 SrIovCapabilityOffset;
> > > UINT32 MrIovCapabilityOffset;
> > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> > > index c7eafff..2343702 100644
> > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> > > @@ -230,7 +230,7 @@ PciSearchDevice (
> > > PciIoDevice = NULL;
> > >
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
> > > IS_PCI_BRIDGE (Pci) ? L"PPB" :
> > > IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
> > > @@ -397,7 +397,7 @@ DumpPpbPaddingResource (
> > >
> > > if ((Type != PciBarTypeUnknown) && ((ResourceType ==
> > > PciBarTypeUnknown)
> > > || (ResourceType == Type))) {
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
> > > mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen
> > > ));
> > > @@ -424,7 +424,7 @@ DumpPciBars (
> > > }
> > >
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset =
> > > 0x%02x\n",
> > > Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType,
> > > PciBarTypeMaxType)],
> > > PciIoDevice->PciBar[Index].Alignment,
> > > PciIoDevice->PciBar[Index].Length,
> > > PciIoDevice->PciBar[Index].Offset @@ -437,13 +437,13 @@ DumpPciBars
> > > PciIoDevice->(
> > > }
> > >
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength =
> > > 0x%lx;\tOffset = 0x%02x\n",
> > > Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType,
> > > PciBarTypeMaxType)],
> > > PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice-
> > > >VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
> > > ));
> > > }
> > > - DEBUG ((EFI_D_INFO, "\n"));
> > > + DEBUG ((DEBUG_INFO, "\n"));
> > > }
> > >
> > > /**
> > > @@ -1903,7 +1903,7 @@ PciParseBar (
> > > // Fix the length to support some special 64 bit BAR
> > > //
> > > if (Value == 0) {
> > > - DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64
> BAR
> > > returns 0, change to 0xFFFFFFFF.\n"));
> > > + DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of
> > > + MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
> > > Value = (UINT32) -1;
> > > } else {
> > > Value |= ((UINT32)(-1) << HighBitSet32 (Value)); @@ -2153,7
> > > +2153,17 @@ CreatePciIoDevice (
> > > NULL
> > > );
> > > if (!EFI_ERROR (Status)) {
> > > - PciIoDevice->IsPciExp = TRUE;
> > > + PciIoDevice->IsPciExp = TRUE;
> > > + //
> > > + // read the PCI device's entire PCI Express Capability structure
> > > + //
> > > + PciIo->Pci.Read (
> > > + PciIo,
> > > + EfiPciIoWidthUint8,
> > > + PciIoDevice->PciExpressCapabilityOffset,
> > > + sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8),
> > > + &PciIoDevice->PciExpStruct
> > > + );
>
> 2. Please follow EDKII coding style document regarding the indent.
>
Ok, got missed for this routine.
> > > }
> > >
> > > if (PcdGetBool (PcdAriSupport)) { @@ -2206,7 +2216,7 @@
> > > CreatePciIoDevice (
> > > &Data32
> > > );
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
> > > Bridge->BusNumber,
> > > Bridge->DeviceNumber,
> > > @@ -2215,7 +2225,7 @@ CreatePciIoDevice (
> > > }
> > > }
> > >
> > > - DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice-
> > > >AriCapabilityOffset));
> > > + DEBUG ((DEBUG_INFO, " ARI: CapOffset = 0x%x\n",
> > > + PciIoDevice->AriCapabilityOffset));
> > > }
> > > }
> > >
> > > @@ -2325,12 +2335,12 @@ CreatePciIoDevice (
> > > PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID
> > > (LastVF) - Bus + 1);
> > >
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x;
> > > FirstVFOffset = 0x%x;\n",
> > > SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
> > > ));
> > > DEBUG ((
> > > - EFI_D_INFO,
> > > + DEBUG_INFO,
> > > " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
> > > PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum,
> > > PciIoDevice-
> > > >SrIovCapabilityOffset
> > > ));
> > > @@ -2345,7 +2355,7 @@ CreatePciIoDevice (
> > > NULL
> > > );
> > > if (!EFI_ERROR (Status)) {
> > > - DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice-
> > > >MrIovCapabilityOffset));
> > > + DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset = 0x%x\n",
> > > + PciIoDevice->MrIovCapabilityOffset));
> > > }
> > > }
> > >
> > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> > > index 9e6671d..df9e696 100644
> > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c
> > > @@ -467,6 +467,14 @@ GetPciFeaturesConfigurationTable (
> > > return EFI_SUCCESS;
> > > }
> > >
> > > + //
> > > + // The PCI features configuration table is not built for RCiEP,
> > > + return NULL // if
> > > + (PciDevice->PciExpStruct.Capability.Bits.DevicePortType == \
> > > + PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT)
> {
> > > + *PciFeaturesConfigTable = NULL;
> > > + return EFI_SUCCESS;
> > > + }
> > >
> > > if (IsDevicePathEnd (PciDevice->DevicePath)){
> > > //
> > > @@ -575,6 +583,45 @@ IsPciRootPortEmpty ( }
> > >
> > >
> > > +/**
> > > + helper routine to dump the PCIe Device Port Type **/ VOID
> > > +DumpDevicePortType (
> > > + IN UINT8 DevicePortType
> > > + )
> > > +{
> > > + switch (DevicePortType){
> > > + case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT:
> > > + DEBUG (( DEBUG_INFO, "PCIe endpoint found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT:
> > > + DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
> > > + DEBUG (( DEBUG_INFO, "PCIe Root Port found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT:
> > > + DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
> > > + DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE:
> > > + DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE:
> > > + DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n"));
> > > + break;
> > > + case
> PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT:
> > > + DEBUG (( DEBUG_INFO, "RCiEP found\n"));
> > > + break;
> > > + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR:
> > > + DEBUG (( DEBUG_INFO, "RC Event Collector found\n"));
> > > + break;
> > > + }
> > > +}
> > > +
> > > /**
> > > Process each PCI device as per the pltaform and device-specific policy.
> > >
> > > @@ -590,8 +637,12 @@ SetupDevicePciFeatures (
> > > )
> > > {
> > > EFI_STATUS Status;
> > > + PCI_REG_PCIE_CAPABILITY PcieCap;
> > > OTHER_PCI_FEATURES_CONFIGURATION_TABLE
> > > *OtherPciFeaturesConfigTable;
> > >
> > > + PcieCap.Uint16 = PciDevice->PciExpStruct.Capability.Uint16;
> > > + DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType);
> > > +
> > > OtherPciFeaturesConfigTable = NULL;
> > > Status = GetPciFeaturesConfigurationTable (PciDevice,
> > > &OtherPciFeaturesConfigTable);
> > > if (EFI_ERROR( Status)) {
> > > --
> > > 2.21.0.windows.1
> > >
> > >
> > >
next prev parent reply other threads:[~2019-12-18 7:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-01 15:09 [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe:New PCI features separation with PCD Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: Separation of the PCI device registration and start Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: Inclusion of new PCI Platform Protocol 2 Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: Integration of setup " Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI feature Max_Read_Req_Size Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI feature No-Snoop Javeed, Ashraf
2019-11-01 15:09 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI feature Completion Timeout Javeed, Ashraf
[not found] ` <15D3127A726D26A6.7420@groups.io>
2019-11-13 3:22 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe:New PCI features separation with PCD Javeed, Ashraf
2019-12-16 12:46 ` Ni, Ray
[not found] ` <15D3127AABF5037C.32624@groups.io>
2019-11-13 3:23 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Javeed, Ashraf
2019-12-16 12:46 ` Ni, Ray
[not found] ` <15D3127A98E21087.7420@groups.io>
2019-11-13 3:25 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: Separation of the PCI device registration and start Javeed, Ashraf
2019-12-17 1:38 ` Ni, Ray
2019-12-17 3:19 ` Javeed, Ashraf
2019-12-19 1:34 ` Ni, Ray
2019-12-19 4:12 ` Javeed, Ashraf
[not found] ` <15D3127AAE5DC481.32624@groups.io>
2019-11-13 3:26 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: Inclusion of new PCI Platform Protocol 2 Javeed, Ashraf
[not found] ` <15D3127B934F51D3.12315@groups.io>
2019-11-13 3:27 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Javeed, Ashraf
2019-12-17 11:56 ` Ni, Ray
2019-12-18 7:14 ` Javeed, Ashraf
2019-12-19 5:48 ` Ni, Ray
[not found] ` <15E1AFB3EABD031C.30484@groups.io>
2020-03-05 14:12 ` Ni, Ray
2020-03-16 9:33 ` Javeed, Ashraf
2020-03-16 14:00 ` Ni, Ray
2020-03-17 7:20 ` Javeed, Ashraf
2020-03-17 15:36 ` Ni, Ray
2020-04-20 13:22 ` Javeed, Ashraf
2020-04-21 6:03 ` Javeed, Ashraf
2020-04-21 6:22 ` Javeed, Ashraf
2020-05-08 8:26 ` Ni, Ray
[not found] ` <15D3127BE430E7DA.31784@groups.io>
2019-11-13 3:28 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: Integration of setup " Javeed, Ashraf
2019-12-17 11:59 ` Ni, Ray
2019-12-18 7:15 ` Javeed, Ashraf
[not found] ` <15D3127C6DFCD4A7.12315@groups.io>
2019-11-13 3:29 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Javeed, Ashraf
2019-12-17 12:03 ` Ni, Ray
2019-12-18 7:32 ` Javeed, Ashraf [this message]
[not found] ` <15D3127D273722D4.32624@groups.io>
2019-11-13 3:30 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Javeed, Ashraf
2019-12-18 8:38 ` Ni, Ray
2019-12-18 9:10 ` Ni, Ray
2019-12-18 14:35 ` Javeed, Ashraf
2019-12-19 2:14 ` Ni, Ray
[not found] ` <15D3127DA6E2D860.7420@groups.io>
2019-11-13 3:31 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI feature Max_Read_Req_Size Javeed, Ashraf
[not found] ` <15D3127E471DF360.32624@groups.io>
2019-11-13 3:32 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Javeed, Ashraf
[not found] ` <15D3127EB6ED8506.12315@groups.io>
2019-11-13 3:33 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI feature No-Snoop Javeed, Ashraf
[not found] ` <15D3127F5541064B.31784@groups.io>
2019-11-13 3:34 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI feature Completion Timeout Javeed, Ashraf
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