From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Javeed, Ashraf" <ashraf.javeed@intel.com>
Cc: "Wang, Jian J" <jian.j.wang@intel.com>,
"Wu, Hao A" <hao.a.wu@intel.com>, "Ni, Ray" <ray.ni@intel.com>
Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase
Date: Fri, 7 Feb 2020 20:18:13 +0000 [thread overview]
Message-ID: <95C5C2B113DE604FB208120C742E9824579AAF7C@BGSMSX101.gar.corp.intel.com> (raw)
In-Reply-To: <15F137802DC889C4.7869@groups.io>
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/8c06ec777429cde1bddf368b16a886b3083ec12c
Thanks
Ashraf
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8, 2020 1:35 AM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>;
> Ni, Ray <ray.ni@intel.com>
> Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12]
> MdeModulePkg/PciBusDxe: Setup PCI Express init phase
>
> References:-
> https://bugzilla.tianocore.org/show_bug.cgi?id=1954
> https://bugzilla.tianocore.org/show_bug.cgi?id=2194
> https://bugzilla.tianocore.org/show_bug.cgi?id=2313
> https://bugzilla.tianocore.org/show_bug.cgi?id=2499
> https://bugzilla.tianocore.org/show_bug.cgi?id=2500
>
> This code change represents the preparation of phase for initializing the PCI
> Express features at the end of PCI enumeration phase.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Jian J Wang <jian.j.wang@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> ---
> MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 181
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++-----------------------------------
> MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 23
> +++++++++++++++++++++++
> 2 files changed, 169 insertions(+), 35 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> index b7832c6..07ee9ba 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> @@ -1,7 +1,7 @@
> /** @file
> Supporting functions implementation for PCI devices management.
>
> -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
> (C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -597,7 +597,7 @@ DeRegisterPciDevice ( }
>
> /**
> - Start to manage the PCI device on the specified root bridge or PCI-PCI Bridge.
> + Start the PCI root Ports or PCI-PCI Bridge only.
>
> @param Controller The root bridge handle.
> @param RootBridge A pointer to the PCI_IO_DEVICE.
> @@ -612,7 +612,82 @@ DeRegisterPciDevice (
>
> **/
> EFI_STATUS
> -StartPciDevicesOnBridge (
> +EnablePciBridges (
> + IN EFI_HANDLE Controller,
> + IN PCI_IO_DEVICE *RootBridge
> + )
> +
> +{
> + PCI_IO_DEVICE *PciIoDevice;
> + EFI_STATUS Status;
> + LIST_ENTRY *CurrentLink;
> + UINT64 Supports;
> +
> + PciIoDevice = NULL;
> + CurrentLink = RootBridge->ChildList.ForwardLink;
> +
> + while (CurrentLink != NULL && CurrentLink != &RootBridge->ChildList)
> + {
> +
> + PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
> +
> + //
> + // check if the device has been assigned with required resource
> + // and registered
> + //
> + if (!PciIoDevice->Registered && !PciIoDevice->Allocated) {
> + return EFI_NOT_READY;
> + }
> +
> + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
> + Status = EnablePciBridges (
> + Controller,
> + PciIoDevice
> + );
> +
> + PciIoDevice->PciIo.Attributes (
> + &(PciIoDevice->PciIo),
> + EfiPciIoAttributeOperationSupported,
> + 0,
> + &Supports
> + );
> + Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
> + PciIoDevice->PciIo.Attributes (
> + &(PciIoDevice->PciIo),
> + EfiPciIoAttributeOperationEnable,
> + Supports,
> + NULL
> + );
> +
> + }
> +
> + CurrentLink = CurrentLink->ForwardLink; }
> +
> + if (PciIoDevice == NULL) {
> + return EFI_NOT_FOUND;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +
> +/**
> + Register to manage the PCI device on the specified root bridge or PCI-PCI
> Bridge.
> +
> + @param Controller The root bridge handle.
> + @param RootBridge A pointer to the PCI_IO_DEVICE.
> + @param RemainingDevicePath A pointer to the
> EFI_DEVICE_PATH_PROTOCOL.
> + @param NumberOfChildren Children number.
> + @param ChildHandleBuffer A pointer to the child handle buffer.
> +
> + @retval EFI_NOT_READY Device is not allocated.
> + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge.
> + @retval EFI_NOT_FOUND Can not find the specific device.
> + @retval EFI_SUCCESS Success to start Pci devices on bridge.
> +
> +**/
> +EFI_STATUS
> +RegisterPciDevicesOnBridge (
> IN EFI_HANDLE Controller,
> IN PCI_IO_DEVICE *RootBridge,
> IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
> @@ -626,7 +701,6 @@ StartPciDevicesOnBridge (
> EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath;
> EFI_STATUS Status;
> LIST_ENTRY *CurrentLink;
> - UINT64 Supports;
>
> PciIoDevice = NULL;
> CurrentLink = RootBridge->ChildList.ForwardLink;
> @@ -681,7 +755,7 @@ StartPciDevicesOnBridge (
> // If it is a PPB
> //
> if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
> - Status = StartPciDevicesOnBridge (
> + Status = RegisterPciDevicesOnBridge (
> Controller,
> PciIoDevice,
> CurrentDevicePath,
> @@ -689,20 +763,6 @@ StartPciDevicesOnBridge (
> ChildHandleBuffer
> );
>
> - PciIoDevice->PciIo.Attributes (
> - &(PciIoDevice->PciIo),
> - EfiPciIoAttributeOperationSupported,
> - 0,
> - &Supports
> - );
> - Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
> - PciIoDevice->PciIo.Attributes (
> - &(PciIoDevice->PciIo),
> - EfiPciIoAttributeOperationEnable,
> - Supports,
> - NULL
> - );
> -
> return Status;
> } else {
>
> @@ -733,28 +793,13 @@ StartPciDevicesOnBridge (
> }
>
> if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
> - Status = StartPciDevicesOnBridge (
> + Status = RegisterPciDevicesOnBridge (
> Controller,
> PciIoDevice,
> RemainingDevicePath,
> NumberOfChildren,
> ChildHandleBuffer
> );
> -
> - PciIoDevice->PciIo.Attributes (
> - &(PciIoDevice->PciIo),
> - EfiPciIoAttributeOperationSupported,
> - 0,
> - &Supports
> - );
> - Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
> - PciIoDevice->PciIo.Attributes (
> - &(PciIoDevice->PciIo),
> - EfiPciIoAttributeOperationEnable,
> - Supports,
> - NULL
> - );
> -
> }
>
> CurrentLink = CurrentLink->ForwardLink; @@ -768,6 +813,72 @@
> StartPciDevicesOnBridge (
> }
> }
>
> +/**
> + Start to manage the PCI device on the specified root bridge or PCI-PCI Bridge.
> +
> + @param Controller The root bridge handle.
> + @param RootBridge A pointer to the PCI_IO_DEVICE.
> + @param RemainingDevicePath A pointer to the
> EFI_DEVICE_PATH_PROTOCOL.
> + @param NumberOfChildren Children number.
> + @param ChildHandleBuffer A pointer to the child handle buffer.
> +
> + @retval EFI_NOT_READY Device is not allocated.
> + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge.
> + @retval EFI_NOT_FOUND Can not find the specific device.
> + @retval EFI_SUCCESS Success to start Pci devices on bridge.
> +
> +**/
> +EFI_STATUS
> +StartPciDevicesOnBridge (
> + IN EFI_HANDLE Controller,
> + IN PCI_IO_DEVICE *RootBridge,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath,
> + IN OUT UINT8 *NumberOfChildren,
> + IN OUT EFI_HANDLE *ChildHandleBuffer
> + )
> +
> +{
> + EFI_STATUS Status;
> +
> + //
> + // first register all the PCI devices // Status =
> + RegisterPciDevicesOnBridge (
> + Controller,
> + RootBridge,
> + RemainingDevicePath,
> + NumberOfChildren,
> + ChildHandleBuffer
> + );
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + } else {
> + //
> + // the late configuration of PCI Express features
> + // the platform is required to indicate its requirement for the initialization
> + // of PCI Express features by publishing its protocol
> + //
> + if (
> + gFullEnumeration
> + && IsPciExpressProtocolPresent ()
> + ) {
> +
> + Status = EnumeratePciExpressFeatures (
> + Controller,
> + RootBridge
> + );
> + }
> + //
> + // finally start those PCI bridge port devices only
> + //
> + return EnablePciBridges (
> + Controller,
> + RootBridge
> + );
> + }
> +}
> +
> /**
> Start to manage all the PCI devices it found previously under
> the entire host bridge.
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> index 2eff8aa..9b7e51f 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h
> @@ -223,4 +223,27 @@ typedef struct {
> }PCI_EXPRESS_FEATURE_INITIALIZATION_POINT;
>
>
> +
> +/**
> + Enumerate all the nodes of the specified root bridge or PCI-PCI
> +Bridge, to
> + configure the other PCI features.
> +
> + @param RootBridge A pointer to the PCI_IO_DEVICE.
> +
> + @retval EFI_SUCCESS The other PCI features configuration during
> enumeration
> + of all the nodes of the PCI root bridge instance were
> + programmed in PCI-compliance pattern along with the
> + device-specific policy, as applicable.
> + @retval EFI_UNSUPPORTED One of the override operation maong the
> nodes of
> + the PCI hierarchy resulted in a incompatible address
> + range.
> + @retval EFI_INVALID_PARAMETER The override operation is performed with
> invalid input
> + parameters.
> +**/
> +EFI_STATUS
> +EnumeratePciExpressFeatures (
> + IN EFI_HANDLE Controller,
> + IN PCI_IO_DEVICE *RootBridge
> + );
> +
> #endif
> --
> 2.21.0.windows.1
>
>
>
next prev parent reply other threads:[~2020-02-07 20:18 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 20:04 [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 00/12] PciBusDxe: New PCI Express features Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe: Setup for " Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: New PCI Express feature Max_Payload_Size Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: New PCI Express feature Max_Read_Req_Size Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: New PCI Express feature Relax Ordering Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: New PCI Express feature No-Snoop Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: New PCI Express feature Completion Timeout Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI Express feature AtomicOp Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI Express feature LTR Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI Express feature Extended Tag Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI Express feature ASPM support Javeed, Ashraf
2020-02-07 20:04 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI Express feature Common CLock Config Javeed, Ashraf
[not found] ` <15F1377EA7D1AA4F.7869@groups.io>
2020-02-07 20:16 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe: Setup for PCI Express features Javeed, Ashraf
2020-02-10 7:20 ` Ni, Ray
2020-02-10 8:26 ` Javeed, Ashraf
2020-02-10 8:37 ` Ni, Ray
2020-02-11 3:59 ` Javeed, Ashraf
[not found] ` <15F137802DC889C4.7869@groups.io>
2020-02-07 20:18 ` Javeed, Ashraf [this message]
2020-02-10 7:37 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase Ni, Ray
2020-02-10 8:32 ` Javeed, Ashraf
2020-02-10 8:46 ` Ni, Ray
2020-02-11 7:14 ` Javeed, Ashraf
[not found] ` <15F137813D8F0C21.4848@groups.io>
2020-02-07 20:19 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: New PCI Express feature Max_Payload_Size Javeed, Ashraf
[not found] ` <15F13782B6D7AE2E.15938@groups.io>
2020-02-07 20:20 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: New PCI Express feature Max_Read_Req_Size Javeed, Ashraf
[not found] ` <15F1378301D514E4.15938@groups.io>
2020-02-07 20:21 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: New PCI Express feature Relax Ordering Javeed, Ashraf
[not found] ` <15F1378385E00982.18602@groups.io>
2020-02-07 20:22 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: New PCI Express feature No-Snoop Javeed, Ashraf
[not found] ` <15F137842EDDF11D.15938@groups.io>
2020-02-07 20:24 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: New PCI Express feature Completion Timeout Javeed, Ashraf
[not found] ` <15F13784AAF69472.18602@groups.io>
2020-02-07 20:25 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI Express feature AtomicOp Javeed, Ashraf
[not found] ` <15F1389AA432C2B6.18602@groups.io>
2020-02-07 20:27 ` Javeed, Ashraf
[not found] ` <15F13785436D3273.18602@groups.io>
2020-02-07 20:28 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI Express feature LTR Javeed, Ashraf
[not found] ` <15F137861A640F9F.15938@groups.io>
2020-02-07 20:29 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI Express feature Extended Tag Javeed, Ashraf
[not found] ` <15F13786546CB2AB.15938@groups.io>
2020-02-07 20:30 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI Express feature ASPM support Javeed, Ashraf
[not found] ` <15F13786E92D19E9.15938@groups.io>
2020-02-07 20:31 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI Express feature Common CLock Config Javeed, Ashraf
2020-02-10 7:40 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 00/12] PciBusDxe: New PCI Express features Ni, Ray
2020-02-10 8:34 ` Javeed, Ashraf
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=95C5C2B113DE604FB208120C742E9824579AAF7C@BGSMSX101.gar.corp.intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox