From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.10645.1581106698779895338 for ; Fri, 07 Feb 2020 12:18:18 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:18:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="232471766" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 07 Feb 2020 12:18:17 -0800 Received: from fmsmsx123.amr.corp.intel.com (10.18.125.38) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:18:17 -0800 Received: from bgsmsx105.gar.corp.intel.com (10.223.43.197) by fmsmsx123.amr.corp.intel.com (10.18.125.38) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:18:17 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.155]) by BGSMSX105.gar.corp.intel.com ([169.254.3.119]) with mapi id 14.03.0439.000; Sat, 8 Feb 2020 01:48:14 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase Thread-Index: AQHV3fIQbOuO9DDKrEu6zJtNcxXaxagQK1gA Date: Fri, 7 Feb 2020 20:18:13 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579AAF7C@BGSMSX101.gar.corp.intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> <15F137802DC889C4.7869@groups.io> In-Reply-To: <15F137802DC889C4.7869@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWEwYmRhMTgtOGNkNC00YTdiLThjOWQtMjNjOTBiMjQ4ZmRlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiQnl5WXR3WERtK0Z6K2JzdXBWZWFRV2lyczhBOFBKRzd3d1lJVUxDZ2x6OXZxK0Z5UElXYTAyNVR0Wm1mdTNvMiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch can also be viewed in the following repo:- https://github.com/ashrafj/edk2-staging/commit/8c06ec777429cde1bddf368b16a= 886b3083ec12c Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Saturday, February 8, 2020 1:35 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] > MdeModulePkg/PciBusDxe: Setup PCI Express init phase >=20 > References:- > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 >=20 > This code change represents the preparation of phase for initializing th= e PCI > Express features at the end of PCI enumeration phase. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 181 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++----------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 23 > +++++++++++++++++++++++ > 2 files changed, 169 insertions(+), 35 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > index b7832c6..07ee9ba 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > @@ -1,7 +1,7 @@ > /** @file > Supporting functions implementation for PCI devices management. >=20 > -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
> (C) Copyright 2018 Hewlett Packard Enterprise Development LP
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -597,7 +597,7 @@ DeRegisterPciDevice ( } >=20 > /** > - Start to manage the PCI device on the specified root bridge or PCI-PC= I Bridge. > + Start the PCI root Ports or PCI-PCI Bridge only. >=20 > @param Controller The root bridge handle. > @param RootBridge A pointer to the PCI_IO_DEVICE. > @@ -612,7 +612,82 @@ DeRegisterPciDevice ( >=20 > **/ > EFI_STATUS > -StartPciDevicesOnBridge ( > +EnablePciBridges ( > + IN EFI_HANDLE Controller, > + IN PCI_IO_DEVICE *RootBridge > + ) > + > +{ > + PCI_IO_DEVICE *PciIoDevice; > + EFI_STATUS Status; > + LIST_ENTRY *CurrentLink; > + UINT64 Supports; > + > + PciIoDevice =3D NULL; > + CurrentLink =3D RootBridge->ChildList.ForwardLink; > + > + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridge->ChildLi= st) > + { > + > + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); > + > + // > + // check if the device has been assigned with required resource > + // and registered > + // > + if (!PciIoDevice->Registered && !PciIoDevice->Allocated) { > + return EFI_NOT_READY; > + } > + > + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > + Status =3D EnablePciBridges ( > + Controller, > + PciIoDevice > + ); > + > + PciIoDevice->PciIo.Attributes ( > + &(PciIoDevice->PciIo), > + EfiPciIoAttributeOperationSupported, > + 0, > + &Supports > + ); > + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > + PciIoDevice->PciIo.Attributes ( > + &(PciIoDevice->PciIo), > + EfiPciIoAttributeOperationEnable, > + Supports, > + NULL > + ); > + > + } > + > + CurrentLink =3D CurrentLink->ForwardLink; } > + > + if (PciIoDevice =3D=3D NULL) { > + return EFI_NOT_FOUND; > + } else { > + return EFI_SUCCESS; > + } > +} > + > + > +/** > + Register to manage the PCI device on the specified root bridge or PCI= -PCI > Bridge. > + > + @param Controller The root bridge handle. > + @param RootBridge A pointer to the PCI_IO_DEVICE. > + @param RemainingDevicePath A pointer to the > EFI_DEVICE_PATH_PROTOCOL. > + @param NumberOfChildren Children number. > + @param ChildHandleBuffer A pointer to the child handle buffer. > + > + @retval EFI_NOT_READY Device is not allocated. > + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. > + @retval EFI_NOT_FOUND Can not find the specific device. > + @retval EFI_SUCCESS Success to start Pci devices on bridge. > + > +**/ > +EFI_STATUS > +RegisterPciDevicesOnBridge ( > IN EFI_HANDLE Controller, > IN PCI_IO_DEVICE *RootBridge, > IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, > @@ -626,7 +701,6 @@ StartPciDevicesOnBridge ( > EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath; > EFI_STATUS Status; > LIST_ENTRY *CurrentLink; > - UINT64 Supports; >=20 > PciIoDevice =3D NULL; > CurrentLink =3D RootBridge->ChildList.ForwardLink; > @@ -681,7 +755,7 @@ StartPciDevicesOnBridge ( > // If it is a PPB > // > if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > - Status =3D StartPciDevicesOnBridge ( > + Status =3D RegisterPciDevicesOnBridge ( > Controller, > PciIoDevice, > CurrentDevicePath, > @@ -689,20 +763,6 @@ StartPciDevicesOnBridge ( > ChildHandleBuffer > ); >=20 > - PciIoDevice->PciIo.Attributes ( > - &(PciIoDevice->PciIo), > - EfiPciIoAttributeOperationSupported, > - 0, > - &Supports > - ); > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > - PciIoDevice->PciIo.Attributes ( > - &(PciIoDevice->PciIo), > - EfiPciIoAttributeOperationEnable, > - Supports, > - NULL > - ); > - > return Status; > } else { >=20 > @@ -733,28 +793,13 @@ StartPciDevicesOnBridge ( > } >=20 > if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > - Status =3D StartPciDevicesOnBridge ( > + Status =3D RegisterPciDevicesOnBridge ( > Controller, > PciIoDevice, > RemainingDevicePath, > NumberOfChildren, > ChildHandleBuffer > ); > - > - PciIoDevice->PciIo.Attributes ( > - &(PciIoDevice->PciIo), > - EfiPciIoAttributeOperationSupported, > - 0, > - &Supports > - ); > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > - PciIoDevice->PciIo.Attributes ( > - &(PciIoDevice->PciIo), > - EfiPciIoAttributeOperationEnable, > - Supports, > - NULL > - ); > - > } >=20 > CurrentLink =3D CurrentLink->ForwardLink; @@ -768,6 +813,72 @@ > StartPciDevicesOnBridge ( > } > } >=20 > +/** > + Start to manage the PCI device on the specified root bridge or PCI-PC= I Bridge. > + > + @param Controller The root bridge handle. > + @param RootBridge A pointer to the PCI_IO_DEVICE. > + @param RemainingDevicePath A pointer to the > EFI_DEVICE_PATH_PROTOCOL. > + @param NumberOfChildren Children number. > + @param ChildHandleBuffer A pointer to the child handle buffer. > + > + @retval EFI_NOT_READY Device is not allocated. > + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. > + @retval EFI_NOT_FOUND Can not find the specific device. > + @retval EFI_SUCCESS Success to start Pci devices on bridge. > + > +**/ > +EFI_STATUS > +StartPciDevicesOnBridge ( > + IN EFI_HANDLE Controller, > + IN PCI_IO_DEVICE *RootBridge, > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, > + IN OUT UINT8 *NumberOfChildren, > + IN OUT EFI_HANDLE *ChildHandleBuffer > + ) > + > +{ > + EFI_STATUS Status; > + > + // > + // first register all the PCI devices // Status =3D > + RegisterPciDevicesOnBridge ( > + Controller, > + RootBridge, > + RemainingDevicePath, > + NumberOfChildren, > + ChildHandleBuffer > + ); > + > + if (EFI_ERROR (Status)) { > + return Status; > + } else { > + // > + // the late configuration of PCI Express features > + // the platform is required to indicate its requirement for the ini= tialization > + // of PCI Express features by publishing its protocol > + // > + if ( > + gFullEnumeration > + && IsPciExpressProtocolPresent () > + ) { > + > + Status =3D EnumeratePciExpressFeatures ( > + Controller, > + RootBridge > + ); > + } > + // > + // finally start those PCI bridge port devices only > + // > + return EnablePciBridges ( > + Controller, > + RootBridge > + ); > + } > +} > + > /** > Start to manage all the PCI devices it found previously under > the entire host bridge. > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > index 2eff8aa..9b7e51f 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > @@ -223,4 +223,27 @@ typedef struct { > }PCI_EXPRESS_FEATURE_INITIALIZATION_POINT; >=20 >=20 > + > +/** > + Enumerate all the nodes of the specified root bridge or PCI-PCI > +Bridge, to > + configure the other PCI features. > + > + @param RootBridge A pointer to the PCI_IO_DEVICE. > + > + @retval EFI_SUCCESS The other PCI features configuration du= ring > enumeration > + of all the nodes of the PCI root bridge= instance were > + programmed in PCI-compliance pattern al= ong with the > + device-specific policy, as applicable. > + @retval EFI_UNSUPPORTED One of the override operation maong the > nodes of > + the PCI hierarchy resulted in a incompa= tible address > + range. > + @retval EFI_INVALID_PARAMETER The override operation is performed wit= h > invalid input > + parameters. > +**/ > +EFI_STATUS > +EnumeratePciExpressFeatures ( > + IN EFI_HANDLE Controller, > + IN PCI_IO_DEVICE *RootBridge > + ); > + > #endif > -- > 2.21.0.windows.1 >=20 >=20 >=20