From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.10694.1581106759228407982 for ; Fri, 07 Feb 2020 12:19:19 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:19:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="379501558" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga004.jf.intel.com with ESMTP; 07 Feb 2020 12:19:18 -0800 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:19:18 -0800 Received: from bgsmsx152.gar.corp.intel.com (10.224.48.50) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:19:17 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.155]) by BGSMSX152.gar.corp.intel.com ([169.254.6.38]) with mapi id 14.03.0439.000; Sat, 8 Feb 2020 01:49:14 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: New PCI Express feature Max_Payload_Size Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: New PCI Express feature Max_Payload_Size Thread-Index: AQHV3fIRPKU9XKnDqUWWc0799T0ff6gQK7Eg Date: Fri, 7 Feb 2020 20:19:13 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579AAF94@BGSMSX101.gar.corp.intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> <15F137813D8F0C21.4848@groups.io> In-Reply-To: <15F137813D8F0C21.4848@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDFkNDg1M2EtOGRkZC00MjY2LTk4ZTEtM2QzMmMzYTczYTBiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiOFNzUUlFRTZyVFd6eWxRejVZbzlqSDdRQVBPTXFqd0hpa240Ym1qbEtKRDVDMnA3cndHeTVjWHFIbzJZZEwwWCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch can also be viewed in the following repo:- https://github.com/ashrafj/edk2-staging/commit/5c835eb3a75da8a65198ba25544= 2e112f0970f39 Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Saturday, February 8, 2020 1:35 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] > PciBusDxe: New PCI Express feature Max_Payload_Size >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 >=20 > The code changes are made to enable the configuration of new PCI Express > feature Max_Payload_Size (MPS), which defines the data packet size for t= he PCI > transactions, as per the PCI Base Specification 4 Revision 1. >=20 > The code changes are made to calibrate highest common value that is appl= - > icable to all the child nodes originating from the primary root bridge d= evice > instance. >=20 > This programming of MPS is based on each PCI device's capability, and al= so its > device-specific platform policy obtained using the new PCI Express Platf= orm > Protocol interface, defined in the below feature request:- > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 193 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 55 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 22 > ++++++++++++++++------ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 5 +++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 80 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 17 > +++++++++++++++++ > 8 files changed, 369 insertions(+), 6 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 225229d..5dc5f61 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -287,6 +287,7 @@ struct _PCI_IO_DEVICE { > // This field is used to support this case. > // > UINT16 BridgeIoAlignment; > + UINT8 SetupMPS; > }; >=20 > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > index f06b411..e3ad105 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -61,6 +61,8 @@ > PciFeatureSupport.h > PciPlatformSupport.c > PciPlatformSupport.h > + PciExpressFeatures.c > + PciExpressFeatures.h >=20 > [Packages] > MdePkg/MdePkg.dec > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > new file mode 100644 > index 0000000..6084446 > --- /dev/null > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > @@ -0,0 +1,193 @@ > +/** @file > + PCI standard feature support functions implementation for PCI Bus mod= ule.. > + > +Copyright (c) 2020, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "PciBus.h" > +#include "PciFeatureSupport.h" > + > +VOID > +ReportPciWriteError ( > + IN UINT8 Bus, > + IN UINT8 Device, > + IN UINT8 Function, > + IN UINT32 Offset > + ) > +{ > + DEBUG (( > + DEBUG_ERROR, > + "Unexpected PCI register (%d,%d,%d,0x%x) write error!", > + Bus, > + Device, > + Function, > + Offset > + )); > +} > + > +/** > + Compare and Swap the payload value - between the global variable to > +maaintain > + common value among all the devices in the PCIe heirarchy from the > +root bridge > + device and all its child devices; with the device-sepcific setup valu= e. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE. > + @param PciExpressConfigurationTable pointer to > + PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > + > + @retval EFI_SUCCESS processing of PCI feature Max_P= ayload_Size > + is successful. > +**/ > +EFI_STATUS > +CasMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciExpressConfigurationTable > + ) > +{ > + UINT8 MpsValue; > + > + // > + // align the MPS of the tree to the HCF with this device // if > + (PciExpressConfigurationTable) { > + MpsValue =3D PciExpressConfigurationTable->Max_Payload_Size; > + > + MpsValue =3D MIN (PciDevice->SetupMPS, MpsValue); > + PciDevice->SetupMPS =3D MIN (PciDevice->SetupMPS, MpsValue); > + > + if (MpsValue !=3D PciExpressConfigurationTable->Max_Payload_Size) { > + PciExpressConfigurationTable->Max_Payload_Size =3D MpsValue; > + } > + } > + > + DEBUG (( > + DEBUG_INFO, > + "MPS: %d [DevCap:%d],", > + PciDevice->SetupMPS, > + PciDevice->PciExpressCapabilityStructure.DeviceCapability.Bits.MaxPayl > + oadSize > + )); > + > + return EFI_SUCCESS; > +} > + > +/** > + The main routine which process the PCI feature Max_Payload_Size as > +per the > + device-specific platform policy, as well as in complaince with the > +PCI Base > + specification Revision 4, that aligns the value for the entire PCI > +heirarchy > + starting from its physical PCI Root port / Bridge device. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE. > + @param PciExpressConfigurationTable pointer to > + PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > + > + @retval EFI_SUCCESS processing of PCI feature Max_P= ayload_Size > + is successful. > +**/ > +EFI_STATUS > +SetupMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciExpressConfigurationTable > + ) > +{ > + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; > + UINT8 MpsValue; > + > + > + PciDeviceCap.Uint32 =3D > + PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32; > + > + if (PciDevice->SetupMPS =3D=3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO)= { > + // > + // configure this feature as per its PCIe device capabilities > + // > + MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; > + // > + // no change to PCI Root ports without any endpoint device > + // > + if (IS_PCI_BRIDGE (&PciDevice->Pci) && PciDeviceCap.Bits.MaxPayload= Size) { > + if (IsListEmpty (&PciDevice->ChildList)) { > + // > + // No device on root bridge > + // > + MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; > + } > + } > + } else { > + MpsValue =3D SetDevicePolicyPciExpressMps (PciDevice->SetupMPS); } > + // // discard device policy override request if greater than PCI > + device capability // PciDevice->SetupMPS =3D MIN > + ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, MpsValue); > + > + return CasMaxPayloadSize ( > + PciDevice, > + PciExpressConfigurationTable > + ); > +} > + > +/** > + Overrides the PCI Device Control register MaxPayloadSize register > +field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance= . > + > + @retval EFI_SUCCESS The data was read from or written to th= e PCI > device. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, > and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ) > +{ > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > + UINT32 Offset; > + EFI_STATUS Status; > + EFI_TPL OldTpl; > + > + PcieDev.Uint16 =3D 0; > + Offset =3D PciDevice->PciExpressCapabilityOffset + > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > + Status =3D PciDevice->PciIo.Pci.Read ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + ASSERT (Status =3D=3D EFI_SUCCESS); > + > + if (PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) { > + PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS; > + DEBUG (( DEBUG_INFO, "MPS=3D%d,", PciDevice->SetupMPS)); > + > + // > + // Raise TPL to high level to disable timer interrupt while the wri= te operation > completes > + // > + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); > + > + Status =3D PciDevice->PciIo.Pci.Write ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + // > + // Restore TPL to its original level > + // > + gBS->RestoreTPL (OldTpl); > + > + if (!EFI_ERROR(Status)) { > + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D > PcieDev.Uint16; > + } else { > + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumbe= r, > PciDevice->FunctionNumber, Offset); > + } > + } else { > + DEBUG (( DEBUG_INFO, "No MPS=3D%d,", PciDevice->SetupMPS)); } > + > + return Status; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > new file mode 100644 > index 0000000..460437b > --- /dev/null > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > @@ -0,0 +1,55 @@ > +/** @file > + PCI standard feature support functions implementation for PCI Bus mod= ule.. > + > +Copyright (c) 2020, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _EFI_PCI_EXPRESS_FEATURES_H_ > +#define _EFI_PCI_EXPRESS_FEATURES_H_ > + > + > +/** > + The main routine which process the PCI feature Max_Payload_Size as > +per the > + device-specific platform policy, as well as in complaince with the > +PCI Base > + specification Revision 4, that aligns the value for the entire PCI > +heirarchy > + starting from its physical PCI Root port / Bridge device. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE. > + @param PciFeaturesConfigurationTable pointer to > + PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > + > + @retval EFI_SUCCESS processing of PCI feature Max_P= ayload_Size > + is successful. > +**/ > +EFI_STATUS > +SetupMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciFeaturesConfigurationTable > + ); > + > +EFI_STATUS > +CasMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciFeaturesConfigurationTable > + ); > + > +/** > + Overrides the PCI Device Control register Max_Read_Req_Size register > +field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance= . > + > + @retval EFI_SUCCESS The data was read from or written to th= e PCI > controller. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, > and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramMaxPayloadSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ); > + > +#endif > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > index 3980a8e..aae6139 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > #include "PciBus.h" > #include "PciFeatureSupport.h" > +#include "PciExpressFeatures.h" >=20 > /** > Hold the current instance of Root Bridge IO protocol Handle > @@ -29,7 +30,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY > mPciExpressPlatformPolicy =3D { > // > // support for PCI Express feature - Max. Payload Size > // > - FALSE, > + TRUE, > // > // support for PCI Express feature - Max. Read Request Size > // > @@ -94,11 +95,16 @@ BOOLEAN mPciExpressGetPlatformPolicyComplete =3D > FALSE; > // PCI Express feature initialization phase handle routines // > PCI_EXPRESS_FEATURE_INITIALIZATION_POINT > mPciExpressFeatureInitializationList[] =3D { > - // > - // vacant entry, shall be replaced with actual entry when the PCI E= xpress > - // feature are added. > - // > - { 0, 0, NULL} > + > + { > + PciExpressFeatureSetupPhase, PciExpressMps, > SetupMaxPayloadSize > + }, > + { > + PciExpressFeatureEntendedSetupPhase, PciExpressMps, > CasMaxPayloadSize > + }, > + { > + PciExpressFeatureProgramPhase, PciExpressMps, > ProgramMaxPayloadSize > + } > }; >=20 > /** > @@ -597,6 +603,10 @@ CreatePciRootBridgeDeviceNode ( > ); > if (PciConfigTable) { > PciConfigTable->ID =3D PortNumber; > + // > + // start by assuming 4096B as the default value for the Max. Payloa= d Size > + // > + PciConfigTable->Max_Payload_Size =3D > PCIE_MAX_PAYLOAD_SIZE_4096B; > } >=20 > RootBridgeNode->PciExFeaturesConfigurationTable =3D PciConfigTable; = diff -- > git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > index 9b7e51f..4ecbefc 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > @@ -66,6 +66,11 @@ struct > _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE { > // Configuration Table ID > // > UINTN ID; > + // > + // to configure the PCI feature Maximum payload size to maintain the > + data packet // size among all the PCI devices in the PCI hierarchy > + // > + UINT8 Max_Payload_Size; > }; >=20 > // > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > index 31c675d..3e9d4c5 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > @@ -81,6 +81,39 @@ IsPciExpressProtocolPresent ( > return TRUE; > } >=20 > +/** > + Routine to translate the given device-specific platform policy from > +type > + EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI > +Base Specification > + Revision 4.0; for the PCI feature Max_Payload_Size. > + > + @param MPS Input device-specific policy should be in terms of ty= pe > + EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE > + > + @retval Range values for the Max_Payload_Size as defined in t= he PCI > + Base Specification 4.0 **/ > +UINT8 > +SetDevicePolicyPciExpressMps ( > + IN UINT8 MPS > +) > +{ > + switch (MPS) { > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B: > + return PCIE_MAX_PAYLOAD_SIZE_128B; > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B: > + return PCIE_MAX_PAYLOAD_SIZE_256B; > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B: > + return PCIE_MAX_PAYLOAD_SIZE_512B; > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B: > + return PCIE_MAX_PAYLOAD_SIZE_1024B; > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B: > + return PCIE_MAX_PAYLOAD_SIZE_2048B; > + case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B: > + return PCIE_MAX_PAYLOAD_SIZE_4096B; > + default: > + return PCIE_MAX_PAYLOAD_SIZE_128B; > + } > +} >=20 > /** > Generic routine to setup the PCI features as per its predetermined de= faults. > @@ -91,6 +124,12 @@ SetupDefaultPciExpressDevicePolicy ( > ) > { >=20 > + if (mPciExpressPlatformPolicy.Mps) { > + PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO; > + } else { > + PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + > } >=20 > /** > @@ -163,6 +202,15 @@ GetPciExpressDevicePolicy ( > // platform chipset policies are returned for this PCI device > // >=20 > + // > + // set device specific policy for the Max_Payload_Size > + // > + if (mPciExpressPlatformPolicy.Mps) { > + PciDevice->SetupMPS =3D PciExpressDevicePolicy.DeviceCtlMPS; > + } else { > + PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; > + } > + >=20 > DEBUG (( > DEBUG_INFO, > @@ -257,6 +305,28 @@ PciExpressPlatformGetPolicy ( > return Status; > } >=20 > +EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE > +GetPciExpressMps ( > + IN UINT8 Mps > + ) > +{ > + switch (Mps) { > + case PCIE_MAX_PAYLOAD_SIZE_128B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B; > + case PCIE_MAX_PAYLOAD_SIZE_256B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B; > + case PCIE_MAX_PAYLOAD_SIZE_512B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B; > + case PCIE_MAX_PAYLOAD_SIZE_1024B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B; > + case PCIE_MAX_PAYLOAD_SIZE_2048B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B; > + case PCIE_MAX_PAYLOAD_SIZE_4096B: > + return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B; > + } > + return EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + >=20 > /** > Notifies the platform about the current PCI Express state of the devi= ce. > @@ -277,6 +347,16 @@ PciExpressPlatformNotifyDeviceState ( { > EFI_PCI_EXPRESS_DEVICE_CONFIGURATION PciExDeviceConfiguration; >=20 > + // > + // get the device-specific state for the PCIe Max_Payload_Size > + feature // if (mPciExpressPlatformPolicy.Mps) { > + PciExDeviceConfiguration.DeviceCtlMPS =3D GetPciExpressMps ( > + (UINT8)PciDevice- > >PciExpressCapabilityStructure.DeviceControl.Bits.MaxPayloadSize > + ); } else { > + PciExDeviceConfiguration.DeviceCtlMPS =3D > + EFI_PCI_EXPRESS_NOT_APPLICABLE; } >=20 > if (mPciExPlatformProtocol !=3D NULL) { > return mPciExPlatformProtocol->NotifyDeviceState ( diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > index 4283b81..5ae6386 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > @@ -84,4 +84,21 @@ EFI_STATUS > PciExpressPlatformNotifyDeviceState ( > IN PCI_IO_DEVICE *PciDevice > ); > + > +/** > + Routine to translate the given device-specific platform policy from > +type > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base > +Specification > + Revision 4.0; for the PCI feature Max_Payload_Size. > + > + @param MPS Input device-specific policy should be in terms of ty= pe > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > + > + @retval Range values for the Max_Payload_Size as defined in t= he PCI > + Base Specification 4.0 **/ > +UINT8 > +SetDevicePolicyPciExpressMps ( > + IN UINT8 MPS > +); > + > #endif > -- > 2.21.0.windows.1 >=20 >=20 >=20