From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.10706.1581106974828358147 for ; Fri, 07 Feb 2020 12:22:54 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:22:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="232472701" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 07 Feb 2020 12:22:53 -0800 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:22:53 -0800 Received: from bgsmsx110.gar.corp.intel.com (10.223.4.212) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 7 Feb 2020 12:22:52 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.155]) by BGSMSX110.gar.corp.intel.com ([169.254.11.43]) with mapi id 14.03.0439.000; Sat, 8 Feb 2020 01:52:49 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: New PCI Express feature No-Snoop Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: New PCI Express feature No-Snoop Thread-Index: AQHV3fITtEWOnZ+Xg0m7iQrY7tMdQ6gQLK7Q Date: Fri, 7 Feb 2020 20:22:49 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579AAFDB@BGSMSX101.gar.corp.intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> <15F1378385E00982.18602@groups.io> In-Reply-To: <15F1378385E00982.18602@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTMyMWQ5MmMtMDJjOS00YTQ5LWE4YjgtYmQxNjFiZmI4MWI4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWllsV2pIeUlGb1hQVm5rdStCU1J3NzcyOEJ0b3Yzd01CZ1lVV3YyYWJTZDR2VVRHU1ZWOXM5MkMyd3IyN2JndCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch can also be viewed in the following repo:- https://github.com/ashrafj/edk2-staging/commit/b83f0f959ba7608bd802c19f9a0= 22fad9e5d01cc Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Saturday, February 8, 2020 1:35 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A = ; > Ni, Ray > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] > PciBusDxe: New PCI Express feature No-Snoop >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 >=20 > The code changes are made; as per the PCI Express Base Specification 4 R= evision > 1; to enable the configuration of PCI Express feature No-Snoop (NS), tha= t > enables the PCI function to initiate requests if it does not require har= dware > enforced cache-coherency for its transactions. >=20 > The code changes are made to configure only those PCI devices which are > requested by platform for override through the new PCI Express Platform > protocol interface for device-specific policies. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 70 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 18 > ++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > | 5 ++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 62 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 155 insertions(+), 1 deletion(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index d3d795d..e610b52 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -293,6 +293,7 @@ struct _PCI_IO_DEVICE { > UINT8 SetupMPS; > UINT8 SetupMRRS; > PCI_FEATURE_POLICY SetupRO; > + PCI_FEATURE_POLICY SetupNS; > }; >=20 > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > index 3262b76..df85366 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > @@ -451,3 +451,73 @@ ProgramRelaxOrder ( > return Status; > } >=20 > +/** > + Overrides the PCI Device Control register No-Snoop register field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance= . > + > + @retval EFI_SUCCESS The data was read from or written to th= e PCI > device. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, > and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramNoSnoop ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ) > +{ > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > + UINT32 Offset; > + EFI_STATUS Status; > + EFI_TPL OldTpl; > + > + PcieDev.Uint16 =3D 0; > + Offset =3D PciDevice->PciExpressCapabilityOffset + > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > + Status =3D PciDevice->PciIo.Pci.Read ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + ASSERT (Status =3D=3D EFI_SUCCESS); > + > + if (PciDevice->SetupNS.Override > + && PcieDev.Bits.NoSnoop !=3D PciDevice->SetupNS.Act > + ) { > + PcieDev.Bits.NoSnoop =3D PciDevice->SetupNS.Act; > + DEBUG (( DEBUG_INFO, "NS=3D%d", PciDevice->SetupNS.Act)); > + > + // > + // Raise TPL to high level to disable timer interrupt while the wri= te operation > completes > + // > + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); > + > + Status =3D PciDevice->PciIo.Pci.Write ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + // > + // Restore TPL to its original level > + // > + gBS->RestoreTPL (OldTpl); > + > + if (!EFI_ERROR(Status)) { > + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D > PcieDev.Uint16; > + } else { > + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumbe= r, > PciDevice->FunctionNumber, Offset); > + } > + } else { > + DEBUG (( DEBUG_INFO, "No NS,", PciDevice->SetupRO.Act)); } > + > + return Status; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > index 0d17801..ee636ce 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > @@ -115,4 +115,22 @@ ProgramRelaxOrder ( > IN VOID *PciExFeatureConfiguration > ); >=20 > +/** > + Overrides the PCI Device Control register No-Snoop register field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance= . > + > + @retval EFI_SUCCESS The data was read from or written to th= e PCI > device. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, > and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramNoSnoop ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ); > + > #endif > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > index 267f570..d264d13 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > @@ -46,7 +46,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY > mPciExpressPlatformPolicy =3D { > // > // support for PCI Express feature - No-Snoop > // > - FALSE, > + TRUE, > // > // support for PCI Express feature - ASPM state > // > @@ -116,6 +116,9 @@ PCI_EXPRESS_FEATURE_INITIALIZATION_POINT > mPciExpressFeatureInitializationList[] > }, > { > PciExpressFeatureProgramPhase, PciExpressRelaxOrder, > ProgramRelaxOrder > + }, > + { > + PciExpressFeatureProgramPhase, PciExpressNoSnoop, > ProgramNoSnoop > } > }; >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > index 40eb8a3..954ce16 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > @@ -188,6 +188,46 @@ SetDevicePolicyPciExpressRo ( > } > } >=20 > +/** > + Routine to set the device-specific policy for the PCI feature > +No-Snoop enable > + or disable > + > + @param NoSnoop value corresponding to data type > EFI_PCI_EXPRESS_NO_SNOOP > + @param PciDevice A pointer to PCI_IO_DEVICE > +**/ > +VOID > +SetDevicePolicyPciExpressNs ( > + IN EFI_PCI_EXPRESS_NO_SNOOP NoSnoop, > + OUT PCI_IO_DEVICE *PciDevice > + ) > +{ > + // > + // implementation specific rules for the usage of PCI_FEATURE_POLICY > +members > + // exclusively for the PCI Feature No-Snoop > + // > + // .Override =3D 0 to skip this PCI feature No-Snoop for the PCI devi= ce > + // .Override =3D 1 to program this No-Snoop PCI feature > + // .Act =3D 1 to enable the No-Snoop in the PCI device > + // .Act =3D 0 to disable the No-Snoop in the PCI device > + // > + switch (NoSnoop) { > + case EFI_PCI_EXPRESS_NS_AUTO: > + PciDevice->SetupNS.Override =3D 0; > + break; > + case EFI_PCI_EXPRESS_NS_DISABLE: > + PciDevice->SetupNS.Override =3D 1; > + PciDevice->SetupNS.Act =3D 0; > + break; > + case EFI_PCI_EXPRESS_NS_ENABLE: > + PciDevice->SetupNS.Override =3D 1; > + PciDevice->SetupNS.Act =3D 1; > + break; > + default: > + PciDevice->SetupNS.Override =3D 0; > + break; > + } > +} > + > /** > Generic routine to setup the PCI features as per its predetermined de= faults. > **/ > @@ -211,6 +251,8 @@ SetupDefaultPciExpressDevicePolicy ( >=20 > PciDevice->SetupRO.Override =3D 0; >=20 > + PciDevice->SetupNS.Override =3D 0; > + > } >=20 > /** > @@ -309,6 +351,15 @@ GetPciExpressDevicePolicy ( > PciDevice->SetupRO.Override =3D 0; > } >=20 > + // > + // set the device specific policy for No-Snoop > + // > + if (mPciExpressPlatformPolicy.NoSnoop) { > + SetDevicePolicyPciExpressNs (PciExpressDevicePolicy.DeviceCtlNoSn= oop, > PciDevice); > + } else { > + PciDevice->SetupNS.Override =3D 0; > + } > + >=20 > DEBUG (( > DEBUG_INFO, > @@ -499,6 +550,17 @@ PciExpressPlatformNotifyDeviceState ( > PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D > EFI_PCI_EXPRESS_NOT_APPLICABLE; > } >=20 > + // > + // get the device-specific state for the PCIe NoSnoop feature // if > + (mPciExpressPlatformPolicy.NoSnoop) { > + PciExDeviceConfiguration.DeviceCtlNoSnoop =3D PciDevice- > >PciExpressCapabilityStructure.DeviceControl.Bits.NoSnoop > + ? EFI_PCI_EXPRESS_N= S_ENABLE > + : > + EFI_PCI_EXPRESS_NS_DISABLE; } else { > + PciExDeviceConfiguration.DeviceCtlNoSnoop =3D > + EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + >=20 > if (mPciExPlatformProtocol !=3D NULL) { > return mPciExPlatformProtocol->NotifyDeviceState ( > -- > 2.21.0.windows.1 >=20 >=20 >=20