From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web11.64001.1584351247170223257 for ; Mon, 16 Mar 2020 02:34:07 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: glbxasvELpaZhVZvVW+rDzHwnB2xvfzp4gZ4fcmN0vZw51gOiMfdr5fkmCLMBqQeYl/IWMrxdr UfwMTRSXlw0Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 02:34:06 -0700 IronPort-SDR: u0azbqWj1Kqi2mNj6SgebMsbNgkzcabf+Kel72BFlhqgjV+hp72ZTK8vTHWPaX1FEU80bmO6K9 CDrgCRgaeAFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,559,1574150400"; d="scan'208";a="354968082" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 16 Mar 2020 02:34:06 -0700 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 16 Mar 2020 02:34:06 -0700 Received: from bgsmsx103.gar.corp.intel.com (10.223.4.130) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 16 Mar 2020 02:33:59 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.228]) by BGSMSX103.gar.corp.intel.com ([169.254.4.56]) with mapi id 14.03.0439.000; Mon, 16 Mar 2020 15:03:56 +0530 From: "Javeed, Ashraf" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Thread-Index: AQHVkMaCz34rWzgvlUCjlXpiQanw+qe92zmAgAFQkwCAAfiR8IB5l2IAgBD+mtA= Date: Mon, 16 Mar 2020 09:33:56 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579C6B6A@BGSMSX101.gar.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127B934F51D3.12315@groups.io> <95C5C2B113DE604FB208120C742E9824579171C4@BGSMSX101.gar.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C3A05B7@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E98245797C292@BGSMSX101.gar.corp.intel.com> <15E1AFB3EABD031C.30484@groups.io> <734D49CCEBEEF84792F5B80ED585239D5C47E0CF@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C47E0CF@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ray, First of all, thank you for taking time to review and on optimizing the PC= Ie feature support in the PciBusDxe. I shall not discuss everything in detail here, just want to bring two majo= r points:- (1) commit:- MdePkg: New PCI Express Platform/Override Protocols https://github.com/niruiyu/edk2/commit/52524e9654704a7f6a30ca446f215b81fe8= f0984 PCI Express Protocol not as per the ECR draft revision 0.8, the changes ma= de has to be reviewed with updated ECR version... the global auto option introduces EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO; is u= sed for MPS, MRRS, RO, NS, AtomicOp, LTR, results in no EFI encodings requi= red for these=20 features, as it can be used with actual values from the PciXX.h definition= s. This do result in lot of code savings.=20 (2) commit:- MdeModulePkg/PciBus: Add the framework to init PCIE features https://github.com/niruiyu/edk2/commit/9fb9a3dcef06de98a76825e2fc07167446e= e6fd9 The context handling of the PCIe feature MPS has fundamental issue as it i= s set to be common for all the nodes of the parent Root Bridge instance. T= he context has to be separate to each first level nodes of a root bridge in= stance. For example, a root bridge has 1 RCiEP and two Root ports, than the= re has to be 3 separate context for each. Since Root port can have its Endp= oint device, or it can have a PCIe switch with 1 upstream and 2 or more dow= nstream ports and to each downstream port an Endpoint device can be connect= ed; the context created for Root Port of an bridge is used for all its chil= d hierarchy nodes; thus PCIe feature like Max_Payload_Size value can be spe= cific to each RCiEP, and each Root ports of the Root Bridge handle. How do = you propose to maintain separate context for just first level nodes of the = Root Bridge handle? The EnumeratePcieDevices() is recursively calls itself for every PCI node = with a level advanced by 1. Thus, the usage of level N and N+1 as parent an= d its child is wrong to me, when you have a PCIe switch below the Root Port= , and N & N+1 will not be direct relation between the upstream port and its= second downstream port...any reason why you have not used the PCI_IO_DEVIC= E.Parent pointer to form relation between the parent and the child? I liked the Pre & Post order flag that is used to processing parent-to-chi= ld vs. child-to-parent nodes. You are calling the first and last features a= s fakes, when you actually parse all the nodes for the GetDevicePolicy() an= d NotifyDeviceState(); to me it is actually an un-named phase where all the= nodes are queried or informed to the platform; that seems fine to save the= NULL on the mPcieFeatures[] table. Thanks Ashraf > -----Original Message----- > From: Ni, Ray > Sent: Thursday, March 5, 2020 7:43 PM > To: devel@edk2.groups.io; Ni, Ray ; Javeed, Ashraf > > Cc: Wang, Jian J ; Wu, Hao A > > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration >=20 > Ashraf, > I think it might be better to describe my review comments with code > implementation. > Can you please check this branch where I did some modification based on > your code? > https://github.com/niruiyu/edk2/tree/pci/pcie2 >=20 > Let's firstly align on the feature initialization framework implementati= on. > To be specific, this commit: > MdeModulePkg/PciBus: Add the framework to init PCIE features > https://github.com/niruiyu/edk2/commit/9fb9a3dcef06de98a76825e2fc0 > 7167446ee6fd9 >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Ni, > Ray > > Sent: Thursday, December 19, 2019 1:49 PM > > To: Javeed, Ashraf ; devel@edk2.groups.io > > Cc: Wang, Jian J ; Wu, Hao A > > > > Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > > 05/12] > > PciBusDxe: Setup sub-phases for PCI feature enumeration > > > > After I reviewed the patch of enabling MaxPayloadSize, MaxReadReqSize > > and more PCIE features, I can now understand the phases more than > > earlier. > > > > Your patch proposed five phases: > > // > > // initial phase in configuring the other PCI features to record the > primary > > // root ports > > // > > PciFeatureRootBridgeScan, > > // > > // get the PCI device-specific platform policies and align with devi= ce > capabilities > > // > > PciFeatureGetDevicePolicy, > > // > > // align all PCI nodes in the PCI heirarchical tree > > // > > PciFeatureSetupPhase, > > // > > // finally override to complete configuration of the PCI feature > > // > > PciFeatureConfigurationPhase, > > // > > // PCI feature configuration complete > > // > > PciFeatureConfigurationComplete > > > > > > I have several comments to the five phases. > > 1. Scan phase is not do the scanning but creates a list to hold all > > root ports under the root bridge. > > 2. Root ports collection is not required by all of the features, only > > by MPS and MRRS. > > But the collection always happens even when platform doesn't require > > PciBus to initialize MPS or MRRS. > > 3. GetDevicePolicy phase is not just call the GetDevicePolicy for each > > device. It also reads the PCIE configuration space to get the device's > > feature related capabilities, for some of the features. > > > > With that, I propose to define 4 phases: > > 1. Initialize phase > > This phase is similar to your Scan phase. > > For some features, this phase does nothing. > > For MPS and MRRS, this phase creates a list holding all root ports. > > > > 2. Scan phase > > This phase is similar to your GetDevicePolicy phase. > > For some features, this phase needs nothing do to. > > For MPS and MRRS, this phase scan all devices and get the aligned > > value of MPS or MRRS. > > > > 3. Program phase or Configuration phase This phase is similar to your > > Configuration phase. > > The Setup phase can be merged to this phase. > > > > 4. Finalize phase. > > This phase is similar to your ConfigurationComplete phase. > > This phase frees the resources occupied/allocated in Initialize phase. > > For some of the features, this phase may do nothing. > > > > Each feature needs to provide function pointers for each phase and > > NULL means the feature doesn't need to do anything in the specific > > phase. > > With that, we can define a structure: > > Typedef struct { > > BOOLEAN Enable; > > PCIE_FEATURE_INITILAIZE Initialize; > > PCIE_FEATURE_SCAN Scan; > > PCIE_FEATURE_PROGRAM Program; > > PCIE_FEATURE_FINALIZE Finalize; > > } PCIE_FEATURE_ENTRY; > > > > With that, we can define a module level global variable: > > PCIE_FEATURE_ENTRY mPcieFeatures[] =3D { > > { TRUE, MaxPayloadInitialize, MaxPayloadScan, MaxPayloadProgram, > > MaxPayloadFinalize}, > > { TRUE, MaxReadRequestInitialize, MaxReadRequestScan, > > MaxReadRequestProgram, MaxReadRequestFinalize}, > > { TRUE, NULL, NULL, RelaxOrderProgram, NULL}, > > { TRUE, NULL, CompletionTimeoutScan, CompletionTimeoutProgram, > NULL }, > > ... > > }; > > > > PCIE_FEATURE_ENTRY.Enable can be set to FALSE according to the > > platform policy. > > > > The enable of PCIE features can be written as a feature agnostic for-l= oop. > > This can make the new feature enabling code easy to add and review. > > > > > > > -----Original Message----- > > > From: Javeed, Ashraf > > > Sent: Wednesday, December 18, 2019 3:14 PM > > > To: Ni, Ray ; devel@edk2.groups.io > > > Cc: Wang, Jian J ; Wu, Hao A > > > > > > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > > > 05/12] > > > PciBusDxe: Setup sub-phases for PCI feature enumeration > > > > > > Thanks for the review, Ray! > > > My response in line > > > > > > > -----Original Message----- > > > > From: Ni, Ray > > > > Sent: Tuesday, December 17, 2019 5:26 PM > > > > To: Javeed, Ashraf ; devel@edk2.groups.io > > > > Cc: Wang, Jian J ; Wu, Hao A > > > > > > > > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > > > 05/12] > > > > PciBusDxe: Setup sub-phases for PCI feature enumeration > > > > > > > > Please check comments below. > > > > I may have more comments regarding to the four phases after I > > > > finish > > > review of > > > > further patches. > > > > > > > > Besides the comments below, I have a general comments to the debug > > > > message: can you please review the existing debug message in the > > > > PciBus > > > driver > > > > and make sure your newly added debug message aligns to existing > style. > > > And try > > > > to use less lines of debug messages with still enough debug > information. > > > Ok, will look into that. > > > > > > > > > > > > > +PRIMARY_ROOT_PORT_NODE > *mPrimaryRootPortList; > > > > > > + > > > > > > +/** > > > > > > + A global pointer to > > > PCI_FEATURE_CONFIGURATION_COMPLETION_LIST, > > > > > > which > > > > > > +stores all > > > > > > + the PCI Root Bridge instances that are enumerated for the > > > > > > +other PCI features, > > > > > > + like MaxPayloadSize & MaxReadReqSize; during the the > > > > > > +Start() interface of the > > > > > > + driver binding protocol. The records pointed by this > > > > > > +pointer would be destroyed > > > > > > + when the DXE core invokes the Stop() interface. > > > > > > +**/ > > > > > > +PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > > > > > > *mPciFeaturesConfigurationCompletionList =3D NULL; > > > > > > > > 1. Please follow existing linked list usage style. The first node > > > > in the list is an empty header node. > > > > > > > > LIST_ENTRY mPrimaryRootPortList; > > > > LIST_ENTRY mPciFeaturesConfigurationCompletionList; > > > > > > > Ok, will make the change when I incorporate the ECR 0.75 or greater > version. > > > > > > > > > +BOOLEAN > > > > > > +CheckPciFeatureConfigurationRecordExist ( > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > + OUT PCI_FEATURE_CONFIGURATION_COMPLETION_LIST > > > > > > +**PciFeatureConfigRecord > > > > > > + ) > > > > > > > > 2. Is this function to check whether the PCIE features under a > > > > root bridge is already initialized? > > > > Can you use the existing variable gFullEnumeration? > > > > The variable is set to TRUE when the enumeration is done to a host > > > > bridge > > > in the > > > > first time. > > > > By using gFullEnumeration, the entire function is not needed. > > > > > > > Ok, will look into this. > > > > > > > > > +EFI_STATUS AddRootBridgeInPciFeaturesConfigCompletionList ( > > > > > > + IN PCI_IO_DEVICE *RootBridge, > > > > > > + IN BOOLEAN ReEnumerationRequired > > > > > > + ) > > > > > > > > 3. Same question as #2. I think by using gFullEnumeration, this > > > > function is > > > not > > > > needed. > > > > > > > OK > > > > > > > > > > > > > +BOOLEAN > > > > > > +IsPciRootPortEmpty ( > > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > > + ) > > > > > > > > 4. Please use IsListEmpty() directly from callers and remove this > function. > > > > > > > Will consider this. > > > > > > > > > +**/ > > > > > > +EFI_STATUS > > > > > > +EnumerateOtherPciFeatures ( > > > > > > > > 5. Can it be "EnumeratePcieFeatures"? > > > > > > > Yes, with the change to ECR 0.75, this routine name shall be changed= . > > > > > > > > > + IN PCI_IO_DEVICE *RootBridge > > > > > > + ) > > > > > > +{ > > > > > > + EFI_STATUS Status; > > > > > > + UINTN OtherPciFeatureConfigPhase; > > > > > > + > > > > > > + // > > > > > > + // check on PCI features configuration is complete and > > > > > > + re-enumeration is required // if > > > > > > + (!CheckPciFeaturesConfigurationRequired > > > > > > + (RootBridge)) { > > > > > > + return EFI_ALREADY_STARTED; } > > > > > > + > > > > > > + CHAR16 *Str; > > > > > > + Str =3D ConvertDevicePathToText ( > > > > > > + DevicePathFromHandle (RootBridge->Handle), > > > > > > + FALSE, > > > > > > + FALSE > > > > > > + ); > > > > > > + DEBUG ((DEBUG_INFO, "Enumerating PCI features for Root > > > > > > + Bridge %s\n", Str !=3D NULL ? Str : L"")); > > > > > > > > 6. Please use DEBUG_CODE macro to include > > > > ConvertDevicePathToText() > > > and > > > > DEBUG(). > > > > Please remember to call FreePool(). > > > > > > > Ok, will can under DEBUG_CODE, and free pool is called in the end > > > > > > > > > + > > > > > > + for ( OtherPciFeatureConfigPhase =3D PciFeatureRootBridgeSc= an > > > > > > + ; OtherPciFeatureConfigPhase <=3D > > > PciFeatureConfigurationComplete > > > > > > + ; OtherPciFeatureConfigPhase++ > > > > > > + ) { > > > > > > + switch (OtherPciFeatureConfigPhase){ > > > > > > + case PciFeatureRootBridgeScan: > > > > > > + SetupPciFeaturesConfigurationDefaults (); > > > > > > + // > > > > > > + //first scan the entire root bridge heirarchy for the > > > > > > + primary PCI root > > > > > ports > > > > > > + // > > > > > > + RecordPciRootPortBridges (RootBridge); > > > > > > > > 7. How about "RecordPciRootPorts (RootBridge)"? The "Bridges" > > > > suffix is a > > > bit > > > > confusing. > > > > > > > Fine, will change. > > > > > > > > > + case PciFeatureGetDevicePolicy: > > > > > > + case PciFeatureSetupPhase: > > > > > > > > 8. In SetupPciFeatures(), why do you need to call DeviceExist()? > > > > Did you see any case that a device is detected in the beginning of > > > > PciBus > > > scan > > > > but is hidden when calling SetupPciFeatures()? > > > > > > > Yes, that is the case; device detected during the beginning of > > > PciBus scan appears to be hidden by the platform drivers, since > > > numerous legacy callbacks are initiated at different phase of PCI > > > enumeration to the PCI Host Bridge, and PciPlatform drivers. > > > This can be avoided if the PciBus driver is enhanced to check for > > > PCI device existence before the publication of the PCI IO Protocol, > > > and removal of the PCI_IO_DEVICE instance from the linked list. > > > > > > > 9. In GetPciFeaturesConfigurationTable() when checking whether a > > > > PCI > > > device > > > > belongs to a root port, we can use below simpler logic: > > > > SizeOfPciDevicePath =3D GetDevicePathSize (PciDevicePath); > > > > SizeOfRootPortDevicePath =3D GetDevicePathSize (RootPortPath); > > > > if ((SizeOfRootPortDevicePath < SizeOfPciDevicePath) && > > > > CompareMem (PciDevicePath, RootPortPath, > > > SizeOfRootPortDevicePath - > > > > END_DEVICE_PATH_LENGTH) =3D=3D 0)) { > > > > // PCI device belongs to the root port. > > > > } > > > > > > > Ok. > > > > > > > > > + Status =3D ProgramPciFeatures (RootBridge); > > > > 10. ProgramPcieFeatures()? > > > > > > > OK > > > > > > > > > + > > > > > > + if (Str !=3D NULL) { > > > > > > + FreePool (Str); > > > > > > + } > > > > > > > > 11. OK the Str is freed here because Str is needed for other debug > > > messages > > > > inside the function. > > > > > > > Yes > > > > > > > > > + // > > > > > > + // mark this root bridge as PCI features configuration > > > > > > +complete, and no new > > > > > > + // enumeration is required > > > > > > + // > > > > > > + AddRootBridgeInPciFeaturesConfigCompletionList (RootBridge, > > > > > > +FALSE); > > > > > > > > 12. Not needed. > > > > > > > ok, after incorporating the logic of gFullEnumeration it won't be > > > required > > > > > > > > > +_PRIMARY_ROOT_PORT_NODE { > > > > > > > > > > + // > > > > > > + // Signature header > > > > > > + // > > > > > > + UINT32 Signature; > > > > > > + // > > > > > > + // linked list pointers to next node > > > > > > + // > > > > > > + LIST_ENTRY NeighborRootPort; > > > > > > + // > > > > > > + // pointer to PCI_IO_DEVICE of the primary PCI Controller > > > > > > +device > > > > > > + // > > > > > > + EFI_DEVICE_PATH_PROTOCOL *RootPortDevicePa= th; > > > > > > + // > > > > > > + // pointer to the corresponding PCI feature configuration > > > > > > +Table node > > > > > > + // all the child PCI devices of the controller are aligned > > > > > > +based on this table > > > > > > + // > > > > > > + OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > > *OtherPciFeaturesConfigurationTable; > > > > > > +}; > > > > > > > > 13. Can you add the OTHER_PCI_FEATURES_CONFIGURATION_TABLE > field > > > to > > > > PCI_IO_DEVICE structure? > > > > So this structure PRIMARY_ROOT_PORT_NODE is not needed. > > > > > > > I think it is better to maintain separately as this configuration > > > table is confined to a group of PCI devices and for the RCiEP it is > > > not applicable hence not required. Moreover, I am maintaining a > > > variable for each PCIe feature in the PCI_IO_DEVICE; perhaps I can > consider having just pointer of it.... > > > > > > > > > +struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST { > > > > 14. This structure is not needed if using gFullEnumeration. > > > Yes. > > > >=20