From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web12.1013.1584431784652883288 for ; Tue, 17 Mar 2020 00:56:24 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: +YvbmXWmImnvCccc7KY0tKxOvdNA9LYxThePNMUk87gVKzmiRx/b/IUcgJ6hlJ4icvrf/mSmmK dExNcjikSG0Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2020 00:56:24 -0700 IronPort-SDR: oJc/ffXChZS6roeXzNqmWvVDLXnXz2AaAKMZJUAUY9hYKmfQyn4KZk0Hg4V094e3Cdy5h6K6/G Tuh1mFoJPA+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,563,1574150400"; d="scan'208";a="262951085" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga002.jf.intel.com with ESMTP; 17 Mar 2020 00:56:23 -0700 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 17 Mar 2020 00:56:23 -0700 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 17 Mar 2020 00:56:23 -0700 Received: from bgsmsx155.gar.corp.intel.com (10.224.48.102) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 17 Mar 2020 00:56:22 -0700 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.228]) by BGSMSX155.gar.corp.intel.com ([169.254.12.231]) with mapi id 14.03.0439.000; Tue, 17 Mar 2020 13:26:20 +0530 From: "Javeed, Ashraf" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" Subject: Re: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing Thread-Topic: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing Thread-Index: AQHV/DEEFv7MX62guk+rcxxFYhLX2ahMamJg Date: Tue, 17 Mar 2020 07:56:20 +0000 Message-ID: <95C5C2B113DE604FB208120C742E9824579C7F52@BGSMSX101.gar.corp.intel.com> References: <15FD081950A8E1F5.25941@groups.io> In-Reply-To: <15FD081950A8E1F5.25941@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Return-Path: ashraf.javeed@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Kindly ignore this as I have sent only the delta portion of previous patch. I shall send the whole patch again. Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, > Ashraf > Sent: Tuesday, March 17, 2020 1:22 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Liu, Zhiguang > Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition > missing >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2598 >=20 > All registers definition of DVSEC are defined as per the PCI Express Bas= e > Specification 4.0 chapter 7.9.6. >=20 > Signed-off-by: Ashraf Javeed > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu >=20 > V2: fixed the comment section description for DVSEC definitions > --- > MdePkg/Include/IndustryStandard/PciExpress40.h | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h > b/MdePkg/Include/IndustryStandard/PciExpress40.h > index 02c30a7757..0564d72861 100644 > --- a/MdePkg/Include/IndustryStandard/PciExpress40.h > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h > @@ -77,7 +77,11 @@ typedef struct { > UINT32 Reserve= d; >=20 > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTRO > L LaneEqualizationControl[1]; } > PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; > +///@} >=20 > +/// The Designated Vendor Specific Capability definitions /// Based on > +section 7.9.6 of PCI Express Base Specification 4.0. > +///@{ > typedef union { > struct { > UINT32 DvsecVendorId : 16; /= /bit 0..15 > -- > 2.21.0.windows.1 >=20 >=20 >=20