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From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: "Gao, Liming" <liming.gao@intel.com>,
	"Liu, Zhiguang" <zhiguang.liu@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Subject: Re: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
Date: Wed, 18 Mar 2020 04:51:10 +0000	[thread overview]
Message-ID: <95C5C2B113DE604FB208120C742E9824579C91BC@BGSMSX101.gar.corp.intel.com> (raw)
In-Reply-To: <047cc188835f4d1f84bf6e97644db6d8@intel.com>

Yes, I verified the build with this patch by directly referencing the new data types in a source file.
Thanks
Ashraf

> -----Original Message-----
> From: Gao, Liming <liming.gao@intel.com>
> Sent: Wednesday, March 18, 2020 8:11 AM
> To: Liu, Zhiguang <zhiguang.liu@intel.com>; Javeed, Ashraf
> <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> 
> Ashraf:
>   The change is good. Have you verified the build with this patch?
> 
>   Reviewed-by: Liming Gao <liming.gao@intel.com>
> 
> Thanks
> Liming
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: 2020年3月17日 16:08
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> 
> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
> 
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Tuesday, March 17, 2020 4:04 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
> 
> All registers definition of DVSEC are defined as per the PCI Express Base
> Specification 4.0 chapter 7.9.6.
> 
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> 
> V2: fixed the comment section description for DVSEC definitions
> ---
>  MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> b/MdePkg/Include/IndustryStandard/PciExpress40.h
> index 9d9b272546..0564d72861 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
>  This header file may not define all structures.  Please extend as required.
> 
>  Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -78,6 +79,33 @@ typedef struct {
>  } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
>  ///@}
> 
> +/// The Designated Vendor Specific Capability definitions /// Based on
> +section 7.9.6 of PCI Express Base Specification 4.0.
> +///@{
> +typedef union {
> +  struct {
> +    UINT32 DvsecVendorId                                        : 16; //bit 0..15
> +    UINT32 DvsecRevision                                        : 4;  //bit 16..19
> +    UINT32 DvsecLength                                          : 12; //bit 20..31
> +  }Bits;
> +  UINT32                                                        Uint32;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> +
> +typedef union {
> +  struct {
> +    UINT16 DvsecId                                              : 16; //bit 0..15
> +  }Bits;
> +  UINT16                                                        Uint16;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> +
> +typedef struct {
> +  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
> +  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> DesignatedVendorSpecificHeader1;
> +  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> DesignatedVendorSpecificHeader2;
> +  UINT8                                                         DesignatedVendorSpecific[1];
> +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> +///@}
> +
>  #pragma pack()
> 
>  #endif
> --
> 2.21.0.windows.1


  reply	other threads:[~2020-03-18  4:51 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-17  8:04 [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing Javeed, Ashraf
2020-03-17  8:08 ` Zhiguang Liu
2020-03-18  2:40   ` Liming Gao
2020-03-18  4:51     ` Javeed, Ashraf [this message]
2020-03-18 15:51       ` Liming Gao
     [not found]       ` <15FD70D8928FA969.21252@groups.io>
2020-03-19  2:02         ` [edk2-devel] " Liming Gao
2020-03-19  6:57           ` Javeed, Ashraf
2020-03-19  8:59 ` Ni, Ray
2020-03-19 10:00   ` Javeed, Ashraf
2020-03-19 15:07     ` Ni, Ray
  -- strict thread matches above, loose matches on Subject: below --
2020-03-17  7:52 [PATCH V2] MdePkg-PciExpress40.h: " Javeed, Ashraf

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