Re: [edk2-devel] [edk2-platforms][PATCH V1 1/5] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region

["Sami Mujawar" <sami.mujawar@arm.com>]

Hi Sahil,

Please see my response inline marked [SAMI].

Regards,

Sami Mujawar

On 16/11/2023 11:45 am, sahil via groups.io wrote:
> Enable SCP QSPI flash region access by adding it in the PlatformLibMem
>
> Signed-off-by: sahil <sahil@arm.com>
> ---
>   Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h              |  6 +++++-
>   Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 10 ++++++++--
>   2 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> index 097160c7e2d1..92b8c9c45775 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> @@ -1,6 +1,6 @@
>   /** @file
>
>   *
>
> -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
>
> +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
>
>   *
>
>   * SPDX-License-Identifier: BSD-2-Clause-Patent
>
>   *
>
> @@ -41,6 +41,10 @@
>   #define NEOVERSEN1SOC_EXP_PERIPH_BASE0               0x1C000000
>
>   #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ            0x1300000
>
>   
>
> +// SCP QSPI flash device
>
> +#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE              0x18000000
>
> +#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ                0x2000000

[SAMI] Can you elaborate what is meant by 'SCP', please? Does this mean 
the flash is shared by SCP and AP? It would be good to clarify that in 
the commit message.

Also, if you can add a reference to the relevant document in the file 
header it would be of great help.

[/SAMI]

>
> +
>
>   // Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
>
>   // pre-populated by a earlier boot stage
>
>   #define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE          (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> index 9e8a1efc557d..eb099953fe29 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> @@ -1,6 +1,6 @@
>   /** @file
>
>   
>
> -  Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
>
> +  Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
>
>   
>
>     SPDX-License-Identifier: BSD-2-Clause-Patent
>
>   
>
> @@ -13,7 +13,7 @@
>   #include <NeoverseN1Soc.h>
>
>   
>
>   // The total number of descriptors, including the final "end-of-table" descriptor.
>
> -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
>
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
>
>   
>
>   /**
>
>     Returns the Virtual Memory Map of the platform.
>
> @@ -184,6 +184,12 @@ ArmPlatformGetVirtualMemoryMap (
>     VirtualMemoryTable[Index].Length          = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
>
>     VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
>   
>
> +  // SCP QSPI flash device
>
> +  VirtualMemoryTable[++Index].PhysicalBase  = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
>
> +  VirtualMemoryTable[Index].VirtualBase     = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
>
> +  VirtualMemoryTable[Index].Length          = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
>
> +  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> +
>
>     if (PlatInfo->MultichipMode == 1) {
>
>       //Remote DDR (2GB)
>
>       VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdExtMemorySpace) +
>


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