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UefiCpuPkg/SmmRelocationLib: Add library instance for AMD To: Jiaxin Wu , devel@edk2.groups.io Cc: Abner Chang , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar References: <20240410135724.15344-1-jiaxin.wu@intel.com> <20240410135724.15344-5-jiaxin.wu@intel.com> From: "Abdul Lateef Attar via groups.io" In-Reply-To: <20240410135724.15344-5-jiaxin.wu@intel.com> X-ClientProxiedBy: PN2P287CA0008.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:21b::13) To IA1PR12MB6458.namprd12.prod.outlook.com (2603:10b6:208:3aa::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR12MB6458:EE_|MW4PR12MB6924:EE_ X-MS-Office365-Filtering-Correlation-Id: 61021eb0-1ca6-4d7e-973f-08dc5dfeda6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: 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--------------YjNsu9HnUSLfr8C02YGIe0bB Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Abdul Lateef Attar On 10-04-2024 19:27, Jiaxin Wu wrote: > Caution: This message originated from an External Source. Use proper caut= ion when opening attachments, clicking links, or responding. > > > Due to the definition difference of SMRAM Save State, > SmmBase config in SMRAM Save State for AMD is also different. > > This patch provides the AmdSmmRelocationLib library instance > to handle the SMRAM Save State difference. > > Cc: Abdul Lateef Attar > Cc: Abner Chang > Cc: Ray Ni > Cc: Zeng Star > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Signed-off-by: Jiaxin Wu > --- > .../SmmRelocationLib/AmdSmmRelocationLib.inf | 61 ++++++++++++ > .../SmmRelocationLib/AmdSmramSaveStateConfig.c | 109 ++++++++++++++= +++++++ > 2 files changed, 170 insertions(+) > create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocation= Lib.inf > create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStat= eConfig.c > > diff --git a/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf = b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf > new file mode 100644 > index 0000000000..710cd1948b > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf > @@ -0,0 +1,61 @@ > +## @file > +# SMM Relocation Lib for each processor. > +# > +# This Lib produces the SMM_BASE_HOB in HOB database which tells > +# the PiSmmCpuDxeSmm driver (runs at a later phase) about the new > +# SMBASE for each processor. PiSmmCpuDxeSmm driver installs the > +# SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor > +# Index. > +# > +# Copyright (c) 2024, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SmmRelocationLib > + FILE_GUID =3D 65C74DCD-0D09-494A-8BFF-A64226EB805= 4 > + MODULE_TYPE =3D PEIM > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SmmRelocationLib > + > +[Sources] > + InternalSmmRelocationLib.h > + AmdSmramSaveStateConfig.c > + SmmRelocationLib.c > + > +[Sources.Ia32] > + Ia32/Semaphore.c > + Ia32/SmmInit.nasm > + > +[Sources.X64] > + X64/Semaphore.c > + X64/SmmInit.nasm > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + CpuExceptionHandlerLib > + DebugLib > + HobLib > + LocalApicLib > + MemoryAllocationLib > + PcdLib > + PeiServicesLib > + > +[Guids] > + gSmmBaseHobGuid ## HOB ALWAYS_PRODUCED > + gEfiSmmSmramMemoryGuid ## CONSUMES > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize ## CO= NSUMES > + > +[FeaturePcd] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport = ## CONSUMES > diff --git a/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.= c b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c > new file mode 100644 > index 0000000000..fbcf347f9b > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c > @@ -0,0 +1,109 @@ > +/** @file > + Config SMRAM Save State for SmmBases Relocation. > + > + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. > + Copyright (c) 2024, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#include "InternalSmmRelocationLib.h" > +#include > + > +/** > + This function configures the SmBase on the currently executing CPU. > + > + @param[in] CpuIndex The index of the CPU. > + @param[in,out] CpuState Pointer to SMRAM Save State Map fo= r the > + currently executing CPU. On out, S= mBase is > + updated to the new value. > + > +**/ > +VOID > +EFIAPI > +ConfigureSmBase ( > + IN UINTN CpuIndex, > + IN OUT SMRAM_SAVE_STATE_MAP *CpuState > + ) > +{ > + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; > + > + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; > + > + if (mSmmSaveStateRegisterLma =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA_32B= IT) { > + AmdCpuState->x86.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; > + } else { > + AmdCpuState->x64.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; > + } > +} > + > +/** > + This function updates the SMRAM save state on the currently executing = CPU > + to resume execution at a specific address after an RSM instruction. T= his > + function must evaluate the SMRAM save state to determine the execution= mode > + the RSM instruction resumes and update the resume execution address wi= th > + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT = restart > + flag in the SMRAM save state must always be cleared. This function re= turns > + the value of the instruction pointer from the SMRAM save state that wa= s > + replaced. If this function returns 0, then the SMRAM save state was n= ot > + modified. > + > + This function is called during the very first SMI on each CPU after > + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution = mode > + to signal that the SMBASE of each CPU has been updated before the defa= ult > + SMBASE address is used for the first SMI to the next CPU. > + > + @param[in] CpuIndex The processor index for the cu= rrently > + executing CPU. > + @param[in,out] CpuState Pointer to SMRAM Save State Ma= p for the > + currently executing CPU. > + @param[in] NewInstructionPointer32 Instruction pointer to use if = resuming to > + 32-bit mode from 64-bit SMM. > + @param[in] NewInstructionPointer Instruction pointer to use if = resuming to > + same mode as SMM. > + > + @retval The value of the original instruction pointer before it was ho= oked. > + > +**/ > +UINT64 > +EFIAPI > +HookReturnFromSmm ( > + IN UINTN CpuIndex, > + IN OUT SMRAM_SAVE_STATE_MAP *CpuState, > + IN UINT64 NewInstructionPointer32, > + IN UINT64 NewInstructionPointer > + ) > +{ > + UINT64 OriginalInstructionPointer; > + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; > + > + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; > + > + if (mSmmSaveStateRegisterLma =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA_32B= IT) { > + OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP; > + AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer; > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { > + AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0; > + } > + } else { > + OriginalInstructionPointer =3D AmdCpuState->x64._RIP; > + if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { > + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; > + } else { > + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer; > + } > + > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { > + AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0; > + } > + } > + > + return OriginalInstructionPointer; > +} > -- > 2.16.2.windows.1 > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117876): https://edk2.groups.io/g/devel/message/117876 Mute This Topic: https://groups.io/mt/105441993/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --------------YjNsu9HnUSLfr8C02YGIe0bB Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

Reviewed-by: Abdul Lateef Atta= r <AbdulLateef.Attar@amd.com>

On 10-04-2024 19:27, Jiaxin Wu wrote: 
Caution: This message originat=
ed from an External Source. Use proper caution when opening attachments, cl=
icking links, or responding.


Due to the definition difference of SMRAM Save State,
SmmBase config in SMRAM Save State for AMD is also different.

This patch provides the AmdSmmRelocationLib library instance
to handle the SMRAM Save State difference.

Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
 .../SmmRelocationLib/AmdSmmRelocationLib.inf       |  61 ++++++++++++
 .../SmmRelocationLib/AmdSmramSaveStateConfig.c     | 109 +++++++++++++++++=
++++
 2 files changed, 170 insertions(+)
 create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib=
.inf
 create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateCo=
nfig.c

diff --git a/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf b/=
UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
new file mode 100644
index 0000000000..710cd1948b
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
@@ -0,0 +1,61 @@
+## @file
+# SMM Relocation Lib for each processor.
+#
+# This Lib produces the SMM_BASE_HOB in HOB database which tells
+# the PiSmmCpuDxeSmm driver (runs at a later phase) about the new
+# SMBASE for each processor. PiSmmCpuDxeSmm driver installs the
+# SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor
+# Index.
+#
+# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    =3D 0x00010005
+  BASE_NAME                      =3D SmmRelocationLib
+  FILE_GUID                      =3D 65C74DCD-0D09-494A-8BFF-A64226EB8054
+  MODULE_TYPE                    =3D PEIM
+  VERSION_STRING                 =3D 1.0
+  LIBRARY_CLASS                  =3D SmmRelocationLib
+
+[Sources]
+  InternalSmmRelocationLib.h
+  AmdSmramSaveStateConfig.c
+  SmmRelocationLib.c
+
+[Sources.Ia32]
+  Ia32/Semaphore.c
+  Ia32/SmmInit.nasm
+
+[Sources.X64]
+  X64/Semaphore.c
+  X64/SmmInit.nasm
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  CpuExceptionHandlerLib
+  DebugLib
+  HobLib
+  LocalApicLib
+  MemoryAllocationLib
+  PcdLib
+  PeiServicesLib
+
+[Guids]
+  gSmmBaseHobGuid                               ## HOB ALWAYS_PRODUCED
+  gEfiSmmSmramMemoryGuid                        ## CONSUMES
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize                     ## CONS=
UMES
+
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport                        ##=
 CONSUMES
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c =
b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
new file mode 100644
index 0000000000..fbcf347f9b
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
@@ -0,0 +1,109 @@
+/** @file
+  Config SMRAM Save State for SmmBases Relocation.
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<=
BR>
+  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "InternalSmmRelocationLib.h"
+#include <Register/Amd/SmramSaveStateMap.h>
+
+/**
+  This function configures the SmBase on the currently executing CPU.
+
+  @param[in]     CpuIndex             The index of the CPU.
+  @param[in,out] CpuState             Pointer to SMRAM Save State Map for =
the
+                                      currently executing CPU. On out, SmB=
ase is
+                                      updated to the new value.
+
+**/
+VOID
+EFIAPI
+ConfigureSmBase (
+  IN     UINTN                 CpuIndex,
+  IN OUT SMRAM_SAVE_STATE_MAP  *CpuState
+  )
+{
+  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
+
+  AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  if (mSmmSaveStateRegisterLma =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT=
) {
+    AmdCpuState->x86.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex];
+  } else {
+    AmdCpuState->x64.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex];
+  }
+}
+
+/**
+  This function updates the SMRAM save state on the currently executing CP=
U
+  to resume execution at a specific address after an RSM instruction.  Thi=
s
+  function must evaluate the SMRAM save state to determine the execution m=
ode
+  the RSM instruction resumes and update the resume execution address with
+  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT re=
start
+  flag in the SMRAM save state must always be cleared.  This function retu=
rns
+  the value of the instruction pointer from the SMRAM save state that was
+  replaced.  If this function returns 0, then the SMRAM save state was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo=
de
+  to signal that the SMBASE of each CPU has been updated before the defaul=
t
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in]     CpuIndex                 The processor index for the curr=
ently
+                                          executing CPU.
+  @param[in,out] CpuState                 Pointer to SMRAM Save State Map =
for the
+                                          currently executing CPU.
+  @param[in]     NewInstructionPointer32  Instruction pointer to use if re=
suming to
+                                          32-bit mode from 64-bit SMM.
+  @param[in]     NewInstructionPointer    Instruction pointer to use if re=
suming to
+                                          same mode as SMM.
+
+  @retval The value of the original instruction pointer before it was hook=
ed.
+
+**/
+UINT64
+EFIAPI
+HookReturnFromSmm (
+  IN     UINTN                 CpuIndex,
+  IN OUT SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN     UINT64                NewInstructionPointer32,
+  IN     UINT64                NewInstructionPointer
+  )
+{
+  UINT64                    OriginalInstructionPointer;
+  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
+
+  AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  if (mSmmSaveStateRegisterLma =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT=
) {
+    OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP;
+    AmdCpuState->x86._EIP      =3D (UINT32)NewInstructionPointer;
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) {
+      AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0;
+    }
+  } else {
+    OriginalInstructionPointer =3D AmdCpuState->x64._RIP;
+    if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) {
+      AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32;
+    } else {
+      AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer;
+    }
+
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) {
+      AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0;
+    }
+  }
+
+  return OriginalInstructionPointer;
+}
--
2.16.2.windows.1
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