From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=ankit.sinha@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D999E2194EB76 for ; Tue, 2 Apr 2019 09:57:32 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2019 09:57:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,301,1549958400"; d="scan'208";a="334334460" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by fmsmga005.fm.intel.com with ESMTP; 02 Apr 2019 09:57:31 -0700 Received: from orsmsx122.amr.corp.intel.com (10.22.225.227) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 2 Apr 2019 09:57:31 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.11]) by ORSMSX122.amr.corp.intel.com ([169.254.11.56]) with mapi id 14.03.0415.000; Tue, 2 Apr 2019 09:57:30 -0700 From: "Sinha, Ankit" To: "Kubacki, Michael A" , "edk2-devel@lists.01.org" CC: "Desimone, Nathaniel L" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" Thread-Topic: [edk2-platforms/devel-MinPlatform][PATCH v4 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash Thread-Index: AQHU6P6GPT6Do4sfeEu/3E8ODqDLUqYpGDaw Date: Tue, 2 Apr 2019 16:57:30 +0000 Message-ID: <972926FCCE2F9141BF8AD787AAA02EFF51115EE0@ORSMSX109.amr.corp.intel.com> References: <20190402024724.12224-1-michael.a.kubacki@intel.com> <20190402024724.12224-4-michael.a.kubacki@intel.com> In-Reply-To: <20190402024724.12224-4-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODgyZTNmY2MtNjY2NC00Yzk0LTkwZjUtN2MwOTc4ZmRiNDgwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWDdQUVprdmVwWkMrbzVaRSs5UGltQ1VxM3p5XC9cL0dGeWk4ZVkzODJGNmJwMVozSmZGR2RMcnREdHVTZXZielozIn0= x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Subject: Re: [edk2-platforms/devel-MinPlatform][PATCH v4 3/3] ClevoOpenBoardPkg/N1xxWU: Write PEI debug messages to SPI flash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Apr 2019 16:57:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ankit Sinha -----Original Message----- From: Kubacki, Michael A=20 Sent: Monday, April 1, 2019 7:47 PM To: edk2-devel@lists.01.org Cc: Sinha, Ankit ; Desimone, Nathaniel L ; Chiu, Chasel ; Gao, Liming ; Kinney, Michael D Subject: [edk2-platforms/devel-MinPlatform][PATCH v4 3/3] ClevoOpenBoardPkg= /N1xxWU: Write PEI debug messages to SPI flash Adds a new SerialPortLib instance to the ClevoOpenBoardPkg to support writi= ng debug messages to a dedicated area on SPI flash. This is to enable close= d chassis debug support on the system. DXE and later phases after memory initialization are expected to use USB de= bug. Cc: Ankit Sinha Cc: Nate DeSimone Cc: Chasel Chiu Cc: Liming Gao Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki --- Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 5 + .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 20 +- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 4 + .../PeiSerialPortLibSpiFlash.inf | 56 ++++ .../PeiSerialPortLibSpiFlash.c | 326 +++++++++++++++++= ++++ 5 files changed, 407 insertions(+), 4 deletions(-) create mode 100644 Pla= tform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSerialPor= tLibSpiFlash.inf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortL= ibSpiFlash/PeiSerialPortLibSpiFlash.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/I= ntel/ClevoOpenBoardPkg/OpenBoardPkg.dec index 87bbfb2240..aa457e64db 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec @@ -30,6 +30,7 @@ Features\Tbt\Include [Guids] gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} +gSpiFlashDebugHobGuid =3D {0xcaaaf418, 0x38a5, 0x4d49, {0= xbe, 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}} gTbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0= xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0= xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} =20 @@ -64,6 +65,10 @@ gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UI= NT8|0x000000110 =20 gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 =20 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|UINT32 +|0x90000030 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|UINT32 +|0x90000031 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x00000000|UINT +32|0x90000032 + [PcdsDynamic] =20 # Board GPIO Table diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 2116c48fc0..c43a30de34 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -116,10 +116,18 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc =20 +[LibraryClasses.IA32.SEC] + =20 +SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNul +l.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + =20 +TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Se +cTestPointCheckLib.inf + =20 +SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi +bNull/SecBoardInitLibNull.inf + [LibraryClasses.IA32] # # PEI phase common # + =20 + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFla + sh/PeiSerialPortLibSpiFlash.inf =20 + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDeb + ugLibReportStatusCode.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf !if $(TARGET) =3D=3D DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf @@ -138,10 +146,6 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc =20 -[LibraryClasses.IA32.SEC] - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf - SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf - [LibraryClasses.X64] # # DXE phase common @@ -185,6 +189,14 @@ # !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc =20 + # + # Core + # + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + # # FSP wrapper SEC Core # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index 95c1758ff3..7f3e965c75 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -136,6 +136,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpar= eOffset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE =20 +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardModuleTok +enSpaceGuid.PcdFlashNvDebugMessageSize +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardModuleToken +SpaceGuid.PcdFlashNvDebugMessageSize +#DEBUG_MESSAGE_AREA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize FV =3D FvAdvanced diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFl= ash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/ClevoOpenBoardPkg/Library= /PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf new file mode 100644 index 0000000000..c22201e033 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ +++ PeiSerialPortLibSpiFlash.inf @@ -0,0 +1,56 @@ +### @file +# Component description file for Serial I/O Port library to write to SPI f= lash. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +This program and the accompanying materials are licensed and made=20 +available under # the terms and conditions of the BSD License which accomp= anies this distribution. +# The full text of the license may be found at #=20 +http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=20 +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSerialPortLibFlash + FILE_GUID =3D 35A3BA89-04BE-409C-A3CA-DEF6B510F80F + VERSION_STRING =3D 1.1 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D SerialPortLib|PEIM PEI_CORE +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + HobLib + PcdLib + PeiServicesLib + SpiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeSiliconPkg/SiPkg.dec + ClevoOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSerialPortLibSpiFlash.c + +[Ppis] + gPchSpiPpiGuid + +[Guids] + gSpiFlashDebugHobGuid + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSU= MES diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFl= ash/PeiSerialPortLibSpiFlash.c b/Platform/Intel/ClevoOpenBoardPkg/Library/P= eiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c new file mode 100644 index 0000000000..e36ff8bff8 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/ +++ PeiSerialPortLibSpiFlash.c @@ -0,0 +1,326 @@ +/** @file + Serial I/O Port library implementation for output to SPI flash + +Copyright (c) 2019, Intel Corporation. All rights reserved.
This=20 +program and the accompanying materials are licensed and made available=20 +under the terms and conditions of the BSD License that accompanies this di= stribution. +The full text of the license may be found at=20 +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=20 +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + PCH_SPI_PPI *PchSpiPpi; + UINT32 CurrentWriteOffset; +} SPI_FLASH_DEBUG_CONTEXT; + +/** + Update reference to the most recent PCH SPI PPI installed + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation + @param NotifyDescriptor Address of the notification descriptor data str= ucture. + @param Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference + @retval EFI_NOT_FOUND An error occurred locating a required interface + @retval EFI_NOT_SUPPORTED + +**/ +EFI_STATUS +EFIAPI +SpiPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + PCH_SPI_PPI *PchSpiPpi; + SPI_FLASH_DEBUG_CONTEXT *Context; + + GuidHob =3D GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob =3D= =3D=20 + NULL) { + return EFI_NOT_FOUND; + } + Context =3D GET_GUID_HOB_DATA (GuidHob); + + Status =3D PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **) &PchSpiPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Context->PchSpiPpi =3D PchSpiPpi; + + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] =3D { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMI= NATE_LIST), + &gPchSpiPpiGuid, + SpiPpiNotifyCallback + } +}; + +/** + Common function to write trace data to a chosen debug interface like + UART Serial device, USB Serial device or Trace Hub device + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + SPI_FLASH_DEBUG_CONTEXT *Context; + UINT32 BytesWritten; + UINT32 SourceBufferOffset; + UINT32 NvMessageAreaSize; + UINT32 LinearOffset; + + BytesWritten =3D NumberOfBytes; + SourceBufferOffset =3D 0; + + NvMessageAreaSize =3D (UINT32) FixedPcdGet32=20 + (PcdFlashNvDebugMessageSize); + + if (NumberOfBytes =3D=3D 0 || NvMessageAreaSize =3D=3D 0) { + return 0; + } + GuidHob =3D GetFirstGuidHob (&gSpiFlashDebugHobGuid); if (GuidHob =3D= =3D=20 + NULL) { + return 0; + } + Context =3D GET_GUID_HOB_DATA (GuidHob); if (Context =3D=3D NULL ||=20 + Context->PchSpiPpi =3D=3D NULL || Context->CurrentWriteOffset >=3D NvMess= ageAreaSize) { + return 0; + } + + if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize > = 0) { + LinearOffset =3D (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase) = - FixedPcdGet32 (PcdFlashAreaBaseAddress)); + Status =3D Context->PchSpiPpi->FlashErase ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + NvMessageAreaSize + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset =3D 0; + } else { + return 0; + } + } + + if (NumberOfBytes > NvMessageAreaSize) { + BytesWritten =3D NvMessageAreaSize; + SourceBufferOffset =3D NumberOfBytes - NvMessageAreaSize; } + + LinearOffset =3D (FixedPcdGet32 (PcdFlashNvDebugMessageBase) +=20 + Context->CurrentWriteOffset) - FixedPcdGet32=20 + (PcdFlashAreaBaseAddress); + + Status =3D Context->PchSpiPpi->FlashWrite ( + Context->PchSpiPpi, + FlashRegionBios, + LinearOffset, + BytesWritten, + (UINT8 *) &Buffer[SourceBufferOffset] + ); + if (!EFI_ERROR (Status)) { + Context->CurrentWriteOffset +=3D BytesWritten; + return BytesWritten; + } + + return 0; +} + +/** + Common function to Read data from UART serial device, USB serial device = and save the datas in buffer. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed, no data is to be read. + @retval >0 Actual number of bytes read from debug device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + return 0; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable= . + + @retval RETURN_SUCCESS The new control bits were set on the seria= l device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial= device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out,=20 +parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + serial interface. A ReceiveFifoDepth value of = 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in microseconds. + This timeout applies to both the transmit and = receive side of the + interface. A Timeout value of 0 will use the d= evice's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A Parity value of + DefaultParity will use the device's default pa= rity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. A DataBits + vaule of 0 will use the device's default data = bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. A StopBits + value of DefaultStopBits will use the device's= default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SU= CCESS. + If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized= . + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + EFI_STATUS Status; + SPI_FLASH_DEBUG_CONTEXT *Context; + + Context =3D (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob=20 + (&gSpiFlashDebugHobGuid, sizeof (SPI_FLASH_DEBUG_CONTEXT)); if (Context = =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT)); + + Status =3D PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]); if (EFI_ERROR= =20 + (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // Perform silicon specific initialization required to enable write to S= PI flash. + // + Status =3D SpiServiceInit (); + if (EFI_ERROR (Status)) { + Status =3D EFI_DEVICE_ERROR; + } + + return Status; +} -- 2.16.2.windows.1