From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: ankit.sinha@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Wed, 31 Jul 2019 11:58:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jul 2019 11:58:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,331,1559545200"; d="scan'208";a="196469726" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by fmsmga004.fm.intel.com with ESMTP; 31 Jul 2019 11:58:55 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.25]) by ORSMSX103.amr.corp.intel.com ([169.254.5.44]) with mapi id 14.03.0439.000; Wed, 31 Jul 2019 11:58:44 -0700 From: "Sinha, Ankit" To: "devel@edk2.groups.io" , "Chiu, Chasel" CC: "Kubacki, Michael A" , "Desimone, Nathaniel L" , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD Thread-Topic: [edk2-devel] [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD Thread-Index: AQHVRgvIU85mem9luECGOLyqJaJ1f6blF7cg Date: Wed, 31 Jul 2019 18:58:43 +0000 Message-ID: <972926FCCE2F9141BF8AD787AAA02EFF5128EA87@ORSMSX109.amr.corp.intel.com> References: <20190729110715.2312-1-chasel.chiu@intel.com> <20190729110715.2312-2-chasel.chiu@intel.com> In-Reply-To: <20190729110715.2312-2-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmFjMjkxOTEtZjNmZS00MGJhLWE1YjEtNGM1ZWVlNjEwNmZkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibGZqWVZYT0NaUTVMc0Z5cm9kSTc0U2ZyQXZBZlFZN1JBYnFrTnk5RzZtRURadDhcL212XC90cElXNENjWHBYcXJGIn0= x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ankit Sinha -----Original Message----- From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu= , Chasel Sent: Monday, July 29, 2019 4:07 AM To: devel@edk2.groups.io Cc: Kubacki, Michael A ; Desimone, Nathaniel = L ; Gao, Liming Subject: [edk2-devel] [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseA= ddress PCD REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1863 Add python script which will rebase FSP binary without patching platform D= SC for Fsp*BaseAddress PCDs. Those base address PCD will be updated in FDF basing on flash map. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddre= ss.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py new file mode 100644 index 0000000000..a8165b08e6 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py @@ -0,0 +1,96 @@ +## @ RebaseFspBinBaseAddress.py +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
#=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # + +import os +import sys +import re +import subprocess + +if len(sys.argv) not in [5,6]: + print ("RebaseFspBinBaseAddress.py - Error in number of arguments=20 +received") + print ("Usage - RebaseFspBinBaseAddress.py =20 + \ + ") + exit(1) + +flashMapName =3D sys.argv[1] +fspBinPath =3D sys.argv[2] +fspBinFile =3D sys.argv[3] +fvOffset =3D int(sys.argv[4], 16) +fspBinFileRebased =3D "Fsp_Rebased.fd" +splitFspBinPath =3D os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFs= pBin.py") + +if len(sys.argv) =3D=3D 6: + splitFspBinPath =3D sys.argv[5] + +# +# Make sure argument passed or valid +# +if not os.path.exists(flashMapName): + print ("WARNING! " + str(flashMapName) + " is not found.") + exit(1) +fspBinFilePath =3D fspBinPath + os.sep + fspBinFile if not=20 +os.path.exists(fspBinFilePath): + print ("WARNING! " + str(fspBinFilePath) + " is not found.") + exit(1) +if not os.path.exists(splitFspBinPath): + print ("WARNING! " + str(splitFspBinPath) + " is not found.") + exit(1) + +# +# Get the FSP-S / FSP-M-T FV Base Address from Flash Map # file =3D open= =20 +(flashMapName, "r") data =3D file.read () + +# Get the Flash Base Address +flashBase =3D int(data.split("FLASH_BASE")[1].split("=3D")[1].split()[0],= = =20 +16) + +# Based on Build Target, select the section in the FlashMap file=20 +flashmap =3D data + +# Get FSP-S & FSP-M & FSP-T offset & calculate the base for line in=20 +flashmap.split("\n"): + if "PcdFlashFvFspSOffset" in line: + fspSBaseOffset =3D int(line.split("=3D")[1].split()[0], 16) + if "PcdFlashFvFspMOffset" in line: + fspMBaseOffset =3D int(line.split("=3D")[1].split()[0], 16) + if "PcdFlashFvFspTOffset" in line: + fspTBaseOffset =3D int(line.split("=3D")[1].split()[0], 16) +file.close() + +# +# Get FSP-M Size, in order to calculate the FSP-T Base. Used=20 +SplitFspBin.py script # to dump the header, and get the ImageSize in=20 +FSP-M section # pythontool =3D 'python' +if 'PYTHON_HOME' in os.environ: + pythontool =3D os.environ['PYTHON_HOME'] + os.sep + 'python' +Process =3D subprocess.Popen([pythontool, splitFspBinPath,=20 +"info","-f",fspBinFilePath], stdout=3Dsubprocess.PIPE) Output =3D=20 +Process.communicate()[0] FsptInfo =3D Output.rsplit(b"FSP_M", 1); for=20 +line in FsptInfo[1].split(b"\n"): + if b"ImageSize" in line: + fspMSize =3D int(line.split(b"=3D")[1], 16) + break + +# Calculate FSP-S/M/T base address, to which re-base has to be done=20 +fspSBaseAddress =3D flashBase + fspSBaseOffset + fvOffset fspMBaseAddress= = =20 +=3D flashBase + fspMBaseOffset fspTBaseAddress =3D flashBase +=20 +fspTBaseOffset + +# +# Re-base FSP bin file to new address and save it as fspBinFileRebased=20 +using SplitFspBin.py # rebaseArguments =3D fspBinFilePath + " -c s m t -b= = =20 +" + str(hex(fspSBaseAddress).rstrip("L")) + " " +=20 +str(hex(fspMBaseAddress).rstrip("L")) + " " +=20 +str(hex(fspTBaseAddress).rstrip("L")) + " -o" + fspBinPath + " -n " +=20 +fspBinFileRebased os.system(pythontool + " " + splitFspBinPath + "=20 +rebase -f" + rebaseArguments) + +# +# Split FSP bin to FSP-S/M/T segments +# +splitArguments =3D fspBinPath + os.sep + fspBinFileRebased + " -o " + fsp= BinPath + " -n Fsp_Rebased.fd" +os.system(pythontool + " " + splitFspBinPath + " split -f" +=20 +splitArguments) + +exit(0) -- 2.13.3.windows.1