From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ankit.sinha@intel.com) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Wed, 31 Jul 2019 11:59:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jul 2019 11:59:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,331,1559545200"; d="scan'208";a="180365685" Received: from orsmsx107.amr.corp.intel.com ([10.22.240.5]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2019 11:59:32 -0700 Received: from orsmsx125.amr.corp.intel.com (10.22.240.125) by ORSMSX107.amr.corp.intel.com (10.22.240.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 31 Jul 2019 11:59:32 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.25]) by ORSMSX125.amr.corp.intel.com ([169.254.3.92]) with mapi id 14.03.0439.000; Wed, 31 Jul 2019 11:59:31 -0700 From: "Sinha, Ankit" To: "devel@edk2.groups.io" , "Chiu, Chasel" CC: "Kubacki, Michael A" , "Desimone, Nathaniel L" , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD Thread-Topic: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD Thread-Index: AQHVRg53xq/hCtylNEm61h/1otfUnqblGAbg Date: Wed, 31 Jul 2019 18:59:30 +0000 Message-ID: <972926FCCE2F9141BF8AD787AAA02EFF5128EAB4@ORSMSX109.amr.corp.intel.com> References: <20190729110715.2312-1-chasel.chiu@intel.com> <20190729110715.2312-4-chasel.chiu@intel.com> In-Reply-To: <20190729110715.2312-4-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTJjZDU5MzItZThkOC00MWRkLTg3YzItMzY3MjUzYjVkNGNiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZjBONitBUEtUbmJvbWQwZ0xiWG0ybjF4cjkwa2ZXdnRjVlBMMXR3NDZUVktmalhyNWhhRVM1UEsxZU40dngrRyJ9 x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: ankit.sinha@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ankit Sinha -----Original Message----- From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu= , Chasel Sent: Monday, July 29, 2019 4:07 AM To: devel@edk2.groups.io Cc: Kubacki, Michael A ; Desimone, Nathaniel = L ; Gao, Liming Subject: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp= *BaseAddress PCD REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1863 PcdFsp*BaseAddress now will be updated in FDF basing on flash map. DSC will only define types of those PCDs and always having 0 as default. Test: interanl platform booted with this patch. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3= +++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12= +++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg= .fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index abafd8e44d..7267d478ad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSiz= e =3D gSiPkgTokenSpaceG SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTo= kenSpaceGuid.PcdFlashAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTo= kenSpaceGuid.PcdFlashAreaSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkg= TokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkg= TokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkg= TokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspSOffset) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTo= kenSpaceGuid.PcdFlashAreaBaseAddress SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTo= kenSpaceGuid.PcdFlashAreaSize #########################################################################= ####### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg= Pcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.= dsc index c22e91af12..55ae9f47ac 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d +++ sc @@ -144,8 +144,11 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 !endif =20 - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 =20 ## Specifies timeout value in microseconds for the BSP to detect all AP= s for the first time. # @Prompt Timeout for the BSP to detect all APs for the first time. @@ -252,7 +255,10 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 !endif =20 [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 # Platform will pre-allocate UPD buffer and pass it to FspWrapper # Those dummy address will be patched before FspWrapper executing gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF -- 2.13.3.windows.1