From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ankit.sinha@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Mon, 19 Aug 2019 11:09:42 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Aug 2019 11:09:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,405,1559545200"; d="scan'208";a="189606514" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2019 11:09:40 -0700 Received: from orsmsx121.amr.corp.intel.com (10.22.225.226) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 19 Aug 2019 11:09:40 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.25]) by ORSMSX121.amr.corp.intel.com ([169.254.10.173]) with mapi id 14.03.0439.000; Mon, 19 Aug 2019 11:09:40 -0700 From: "Sinha, Ankit" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Desimone, Nathaniel L" , "Kinney, Michael D" Subject: Re: [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Thread-Topic: [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Thread-Index: AQHVVJEbw7CIn8rVf0ii06tPfWVChKcCySnw Date: Mon, 19 Aug 2019 18:09:39 +0000 Message-ID: <972926FCCE2F9141BF8AD787AAA02EFF512B875E@ORSMSX109.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-32-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-32-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNmY3NzMwODMtNDg3YS00MWE5LWExOGUtZjg2ZTkxZWJlNWI1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidnB2aE5NSmJcL3lLNlhpUVJxc3c3eHNaaGV4SGRmRDVLbjY5eURGMUYwR3Z4dVwvTzhZVnR0M1ZJWnVFZ3pFNVhGIn0= x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: ankit.sinha@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ankit Sinha -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Gao, Liming ; Desimone, Nathanie= l L ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add pack= age and headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Create the WhiskeylakeOpenBoardPkg to provide board support code. The package may support Coffee Lake (CFL) and Whiskey Lake (WHL) boards. The package serves as a board support package in the EDK II Minimum Platform design. Silicon support for this package is provided in CoffeeLakeFspBinPkg in the FSP repository and CoffeelakeSiliconPkg in the edk2-platforms repository. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec = | 565 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeChe= ckIommuSupportLib.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt= PolicyLib.h | 49 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt= SecurityLib.h | 131 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiChe= ckIommuSupportLib.h | 21 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbt= PolicyLib.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbt= TaskDispatchLib.h | 61 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCom= monLib.h | 261 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPoli= cy.h | 31 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/Librar= y/PeiDTbtInitLib.h | 130 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/Librar= y/PeiTbtCommonInitLib.h | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/Disab= leBmeProtocol.h | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTb= tPolicy.h | 137 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNv= sArea.h | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h= | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaDef.= h | 68 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommo= nDefinition.h | 84 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h = | 118 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h = | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h = | 57 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigurations.h = | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h = | 1766 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h = | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h = | 68 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpdateL= ib.h | 75 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePolicyUpdateLi= b.h | 27 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchPolicyUpdateL= ib.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePolicyBoardConfi= gLib.h | 30 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdateLi= b.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h = | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioCheckConflictLi= b.h | 46 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExpanderLib.h = | 123 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h = | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessLib.h = | 34 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatformLib.h = | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfi= gLib.h | 141 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h = | 38 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PlatformInitLib.h = | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h = | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h = | 106 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h = | 33 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h = | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h = | 47 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h = | 144 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h = | 157 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl = | 112 ++ 46 files changed, 5288 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..9d56f0e841 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,565 @@ +## @file +# Module describe the entire platform configuration. +# +# The DEC files are used by the utilities that parse DSC and +# INF files to generate AutoGen.c and AutoGen.h files +# for the build infrastructure. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D OpenBoardPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E + +[Includes] +Include +WhiskeylakeURvp\Include +Features\Tbt\Include + +[Guids] + +gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} + +gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} + +gTbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0= xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} + +gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0= xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} + +gMeInfoSetupGuid =3D {0x78259433, 0x7b6d, 0x4db3, {0= x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}} +gRealModeFileGuid =3D {0xdf84ed23, 0x5d53, 0x423f, {0= xaa, 0x81, 0x0f, 0x0e, 0x6f, 0x55, 0xc6, 0x9b}} +gVirtualKeyboardDriverImageGuid =3D {0xe4735aac, 0x9c27, 0x493f, {0= x86, 0xea, 0x9e, 0xff, 0x43, 0xd7, 0xad, 0xcd}} +gPegConfigVariableGuid =3D {0xb414caf8, 0x8225, 0x4d6f, {0= xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}} +gSaSetupVariableGuid =3D {0x72c5e28c, 0x7783, 0x43a1, {0= x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}} +gMeSetupVariableGuid =3D {0x5432122d, 0xd034, 0x49d2, {0= xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}} +gCpuSetupVariableGuid =3D {0xb08f97ff, 0xe6e8, 0x4193, {0= xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}} +gCpuSmmGuid =3D {0x90d93e09, 0x4e91, 0x4b3d, {0= x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81}} +gPchSetupVariableGuid =3D {0x4570b7f1, 0xade8, 0x4943, {0= x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}} +gSiSetupVariableGuid =3D {0xAAF8E719, 0x48F8, 0x4099, {0= xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}} +gDebugConfigVariableGuid =3D {0xDE0A5E74, 0x4E3E, 0x3D96, {0= xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}} +gDebugConfigHobGuid =3D {0x2f6a6bb7, 0x9dc7, 0x4bf6, {0= x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}} +gChassisIntrudeDetHobGuid =3D {0xdea43de2, 0x756b, 0x4b3b, {0= x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}} + +gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0= xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}} + +gAttemptUsbFirstHotkeyInfoHobGuid =3D {0x38b8e214, 0x1468, 0x4bb7, {0= x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}} +gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} +## +## ChipsetInitBinary +## +gCnlPchLpChipsetInitTableDxGuid =3D {0xc9505bc0, 0xaa3d, 0x4056,= {0x99, 0x95, 0x87, 0x0c, 0x8d, 0xe8, 0x59, 0x4e}} + + +[Protocols] +gTbtNvsAreaProtocolGuid =3D {0x4d6a54d1, 0xcd56, 0x47f3, {0= x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}} +gDxeTbtPolicyProtocolGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0= x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}} + +[Ppis] +gPeiTbtPolicyPpiGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0= xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}} +gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c60, 0x8547, 0x49d7, { = 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}} + +[LibraryClasses] + +[PcdsFixedAtBuild, PcdsPatchableInModule] + +[PcdsFixedAtBuild] + +gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004 +gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005 + +gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x900000= 03 +gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004 +gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x9000000= 5 +gPlatformModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006 +gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress|0xFED84000|UINT64|0x90000= 007 +gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize|0x1000|UINT32|0x90000008 +gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9000= 0009 +gPlatformModuleTokenSpaceGuid.PcdEdramMmioSize|0x4000|UINT32|0x9000000A +gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000= 000B +gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize|0x1000|UINT32|0x9000000= C +gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000= D +gPlatformModuleTokenSpaceGuid.PcdApicIoMmioSize|0x1000|UINT32|0x9000000E +gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xCF000000|UINT64|0x9000000F +gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xD0000000|UINT64|0x90000010 +gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 +gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 +gPlatformModuleTokenSpaceGuid.PcdPcieDockBridgeResourcePatchSmi|0x4D|UINT8= |0x90000014 +gPlatformModuleTokenSpaceGuid.PcdCmosFastBootDefaultValue|0x01|UINT8|0x900= 00016 +gPlatformModuleTokenSpaceGuid.PcdCmosDebugPrintErrorLevelDefaultValue|0x80= 000046|UINT32|0x90000017 +gPlatformModuleTokenSpaceGuid.PcdOverClockingInterfaceSwSmi|0x72|UINT8|0x9= 0000019 +gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|= 0x9000001A +gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16= |0x9000001B +gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E +gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48|UINT8|0x= 90000020 +gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505 +gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001= 003 + +gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 +gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 +gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000= 001C +gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D +gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F +gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000= 021 +gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x900000= 22 + +[PcdsDynamic] +# Board GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x00000011= 4 + +# Board Expander GPIO Table +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047 + +# TouchPanel & SDHC CD GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048 + +# PCH-LP HSIO PTSS Table +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x000000= 4C +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x000000= 4D +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x0000= 0050 +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x0000= 0051 + +# PCH-H HSIO PTSS Table +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x0000005= 4 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x0000005= 5 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000= 058 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000= 059 + +# HDA Verb Table +gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A +gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B +gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F +gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060 + +# SA Misc Configuration +gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 +gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 +gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 + +# DRAM Configuration +gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 +gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 +gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A +gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B +gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C +gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D +gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x= 0000006E +gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006= F +gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 +gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 + +# PEG RESET GPIO +gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072 +gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073 +gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007= F + +# SPD Address Table +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099 +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C + +# CA Vref Configuration +gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D + +# USB 2.0 Port AFE +gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF +gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 +gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 +gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 +gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 +gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 +gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 +gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 +gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 +gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 +gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 +gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA +gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB +gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC +gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD +gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE + +# USB 2.0 Port Over Current Pin +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE + +# USB 3.0 Port Over Current Pin +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8 + +# Misc +gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC + +# TBT +gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 +gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4 +gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5 +gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA +gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB +gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC +gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD +gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE +gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 +gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF +gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 +gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A +gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107 +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108 +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109 + +# UCMC GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111 +gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112 + +gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 +gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 +gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 +gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 +gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006 +gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009 +gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A +gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B +gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C + +# 0: Type-C +# 1: Stacked-Jack +gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 + +gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 + +# gIntelPeiGraphicsVbtGuid =3D {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, = 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}} +gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xe= b, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|= 0x40000014 +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +# +# The PCD which indicates the Memory Slot Population. +# +gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x= 00101027 +gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x0000= 0010 + +# Board GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x0= 01000115 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16= |0x001000116 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x= 001000117 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT1= 6|0x001000118 +gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x001002= 0C +gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E +gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F +gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230 +gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231 +gBoardModuleTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234 +gBoardModuleTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235 +gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236 + +# UCMC GPIO Table +gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033 +gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034 + +# PEG RESET GPIO +gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074 +gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075 +gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105 +gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106 + +# PCIE RTD3 GPIO +gBoardModuleTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076 +gBoardModuleTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077 +gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104 +gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078 + +gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080 +gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x0000008= 7 + +gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088 +gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089 +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008= F +gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130 +gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x0000013= 7 + +# Root Port Clock Info +gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E +gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F +gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 +gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 +gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 +gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 +gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 +gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 +gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 +gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 +gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 +gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 +gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA +gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB +gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC +gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD + +# GPIO Group Tier +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9 +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB + +# Board related PCH PmConfig +gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000= F6 +gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7 +gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8 + +# Misc +gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED +gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE +gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF +gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0 +gBoardModuleTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1 +gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2 +gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9 +#gBoardModuleTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC + +#PlatformInfoPcd +gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101= 000 +gBoardModuleTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001 +gBoardModuleTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002 +gBoardModuleTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003 +gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004 +gBoardModuleTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005 +gBoardModuleTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF= "|VOID*|0x00101007 +gBoardModuleTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008 +gBoardModuleTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009 +gBoardModuleTokenSpaceGuid.PcdBiosVersion|L"012345678901234567890123456789= 0123456789"|VOID*|0x0010100E +gBoardModuleTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x= 0010100F +gBoardModuleTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x= 00101010 +gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011 +gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012 +gBoardModuleTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013 +gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014 +gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015 +gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016 +gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017 +gBoardModuleTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018 +gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019 +gBoardModuleTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A + +# PCH Misc Configuration +gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061 +gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065 +gBoardModuleTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102 +gBoardModuleTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103 +gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110 + +# Control PCD to dump default silicon policy +gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x= 00010064 + +# Pch SerialIo I2c Pads Termination +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x0= 0000020 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x0= 0000021 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x0= 0000022 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x0= 0000023 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x0= 0000030 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x0= 0000031 +# +# The PCD which holds the pointer of Smbios Platform Info table +# +gBoardModuleTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B +# +# The PCD which used to enable / disable the code to use RVP Smbios Board = Info +# +gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x001010= 1C +# +# The PCD which holds the pointer of RVP Smbios Board Info +# +gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D +# +# CoEngineering Custom Defaults PCD +# +gBoardModuleTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x001002= 27 +# +# The PCD which is defined to enable/disable the SMBus Alert function. +# +gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E +# +# The PCD which is defined to enable/disable the SATA LED function. +# +gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F +# +# The PCD which is defined to enable/disable the VR Alert function. +# +gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020 +# +# The PCD which is defined to enable/disable the PCH thermal hot threshold= function. +# +gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021 +# +# The PCD which is defined to enable/disable the memory thermal sensor GPI= O C/D function. +# +gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BO= OLEAN|0x00101022 +gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BO= OLEAN|0x00101023 +# +# The PCD defines the I2C bus number to which PSS chip connected. +# +gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024 +gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025 +gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026 +# +# The PCD defines the USB port number to which BLE connected. +# +gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber |0x0|UI= NT8|0x00101028 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support |0x00|U= INT8|0x00100113 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support |0x00|U= INT8|0x00100114 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support |0x00|U= INT8|0x00100115 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support |0x00|U= INT8|0x00100116 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support |0x00|U= INT8|0x00100117 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support |0x00|U= INT8|0x00100118 +gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|= BOOLEAN|0x00100119 +gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|= BOOLEAN|0x0010011A +gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|= BOOLEAN|0x0010011B +gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|= BOOLEAN|0x0010011C +gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|= BOOLEAN|0x0010011D +gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport |FALSE|= BOOLEAN|0x0010011F +gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|U= INT32|0x00100120 +gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|= BOOLEAN|0x00100121 +gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|= BOOLEAN|0x00100122 +gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature |FALSE|= BOOLEAN|0x00100123 +gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UI= NT8|0x00100124 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213 +gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204 +gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205 +gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209 +gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A +gBoardModuleTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B +gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F +gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210 + +gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio |0x0|UI= NT32|0x00100126 +gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber |0x0|UI= NT8|0x00100127 +gBoardModuleTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200 +gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio |0x0|UI= NT32|0x00100125 +gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201 +gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202 +gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203 +gBoardModuleTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215 +gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A +gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D +gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040 +gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043 +gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046 +gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049 +gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A +gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed |0x0|UI= NT8|0x00100128 +gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed |0x0|UI= NT8|0x00100129 +gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed |0x0|UI= NT8|0x0010012A +gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed |0x0|UI= NT8|0x0010012B + +# Super IO Pcd +gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100 +gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104 +gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105 +gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport |FALSE|= BOOLEAN|0x00100112 +gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|U= INT32|0x00100111 +gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|U= INT8|0x00100103 +gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|U= INT8|0x00100104 + +gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221 +gBoardModuleTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E +gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D +gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOLEAN|0x001002= 2C +gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B +gBoardModuleTokenSpaceGuid.PcdMipiCamSensor |FALSE|= BOOLEAN|0x00100105 +gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|= BOOLEAN|0x0010010A +gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|= BOOLEAN|0x00100107 +gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|= BOOLEAN|0x00100108 +gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|= BOOLEAN|0x00100109 + +[PcdsDynamicEx] + +[PcdsDynamic, PcdsDynamicEx] + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] +gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062 +gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF0000000 +gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x0000001= 15 + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeCheckIommuSupportLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Include/Library/DxeCheckIommuSupportLib.h new file mode 100644 index 0000000000..4aae18cac4 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeCheckIommuSupportLib.h @@ -0,0 +1,43 @@ +/** @file + Header file for the DxeCheckIommuSupport library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ +#define _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + +/** + Detect ME FW and Board Type and return the result via IommuSkuCheck. + + IommuSkuCheck + BIT0: Indicate system has a Corporate CSME firmware + BIT1: Indicate BIOS is running on a WHL RVP + BIT2: Indicate BIOS is running on a CFL-H RVP + BIT3: Indicate BIOS is running on a CFL-S 8+2 RVP + + @retval Return 0 means not support, otherwise value is defined by IommuS= kuCheck +**/ +UINT8 +DetectMeAndBoard ( + VOID + ); + +/** + DxeCheckIommuSupport + + Only WHL/CFL-H/CFL-S 8+2 Crop SKUs support Iommu. + This function will save sku information to PcdIommuSkuCheck. + BIOS will use PcdIommuSkuCheck and other factors to set PcdVTdPolicyProp= ertyMask on the next boot in PEI phase + + This function might perform a system reset. +**/ +EFI_STATUS +EFIAPI +DxeCheckIommuSupport ( + VOID + ); +#endif // _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeTbtPolicyLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/T= bt/Include/Library/DxeTbtPolicyLib.h new file mode 100644 index 0000000000..167cc8af83 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeTbtPolicyLib.h @@ -0,0 +1,49 @@ +/** @file + Prototype of the DxeTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_LIB_H_ +#define _DXE_TBT_POLICY_LIB_H_ + + +/** + Install TBT Policy. + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallTbtPolicy ( + IN EFI_HANDLE ImageHandle + ); + +/** + Update Tbt Policy Callback. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateTbtPolicyCallback ( + VOID + ); + +/** + Print DXE TBT Policy +**/ +VOID +TbtPrintDxePolicyConfig ( + VOID + ); +#endif // _DXE_TBT_POLICY_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeTbtSecurityLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features= /Tbt/Include/Library/DxeTbtSecurityLib.h new file mode 100644 index 0000000000..17337ceb0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeTbtSecurityLib.h @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_SECURITY_LIB_H_ +#define _TBT_SECURITY_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TBT_SECURITY_EVENT_STRING "DMA Protection Disabled= " +#define TBT_SECURITY_EVENT_STRING_LEN (sizeof (TBT_SECURITY_EV= ENT_STRING) - 1) + +#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING "Security Level is Downg= raded to 0" +#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN (sizeof (TBT_SECURITY_LE= VEL_DOWNGRADED_STRING) - 1) + +#define GET_TBT_SECURITY_MODE 0 +#define SET_TBT_SECURITY_MODE 1 + +typedef struct { + UINT8 EnableVtd; + BOOLEAN SLDowngrade; +} PCR7_DATA; + +/** + TBT Security ExtendPCR7 CallBackFunction + If the firmware/BIOS has an option to enable and disable DMA protections= via a VT-d switch in BIOS options, then the shipping configuration must be= with VT-d protection enabled. + On every boot where VT-d/DMA protection is disabled, or will be disabled= , or configured to a lower security state, and a platform has a TPM enabled= , then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before = enabling external DMA. + The event string SHALL be "DMA Protection Disabled". The platform firmwa= re MUST log this measurement in the event log using the string "DMA Protect= ion Disabled" for the Event Data. + Measure and log launch of TBT Security, and extend the measurement resul= t into a specific PCR. + Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. = The event string SHALL be "DMA Protection Disabled". The platform firmware = MUST log this measurement in the event log using the string "DMA Protection= Disabled" for the Event Data. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +ExtendPCR7CallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + TBT Security DisableBme CallBackFunction + + BIOS will disable BME and tear down the Thunderbolt DMAR tables at ExitB= ootServices + in order to hand off security of TBT hierarchies to the OS. + The BIOS is expected to either: Disable BME from power on till the OS st= arts configuring the devices and enabling BME Enable BME only for devices t= hat can be protected by VT-d in preboot environment, + but disable BME and tear down any Thunderbolt DMAR tables at ExitBootSer= vices() + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +TbtDisableBmeCallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + TBT Security SetDmarOptIn CallBackFunction + + A new security feature will be supported to protect against Physical DMA= attacks over Thunderbolt connects. + In order to do this, they need a new flag added to the DMAR tables that = a DMA is only permitted into RMRR at ExitBootServices(). With this flag av= ailable, OS can then Bug Check if any DMA is requested outside of the RMRR = before OS supported device drivers are started. + ReadyToBoot callback routine to update DMAR BIT2 + Bit definition: DMA_CONTROL_GUARANTEE + If Set, the platform supports blocking all DMA outside of the regions de= fined in the RMRR structures from ExitBootServices() until OS supported dev= ice drivers are started. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +SetDmarOptInCallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + The function install DisableBme protocol for TBT Shell validation +**/ +VOID +InstallDisableBmeProtocol ( + VOID + ); + +/** + Get or set Thunderbolt(TM) security mode + + @param[in] DelayTime - The delay time after do ForcePwr + @param[in] SecurityMode - TBT Security Level + @param[in] Gpio3ForcePwrEn - Force GPIO to power on or not + @param[in] DTbtController - Enable/Disable DTbtController + @param[in] MaxControllerNumber - Number of contorller + @param[in] Action - 0 =3D get, 1 =3D set + + @retval - Return security level +**/ +UINT8 +EFIAPI +GetSetSecurityMode ( + IN UINTN DelayTime, + IN UINT8 SecurityMode, + IN UINT8 Gpio3ForcePwrEn, + IN UINT8 *DTbtController, + IN UINT8 MaxControllerNumber, + IN UINT8 Action +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiCheckIommuSupportLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Include/Library/PeiCheckIommuSupportLib.h new file mode 100644 index 0000000000..9afb36f011 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiCheckIommuSupportLib.h @@ -0,0 +1,21 @@ +/** @file + Header file for the PeiCheckIommuSupport library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ +#define _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + +/** + Check Iommu Ability base on SKU type, CSME FW type, Vtd and setup option= s. +**/ +VOID +PeiCheckIommuSupport ( + VOID + ); + +#endif // _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiTbtPolicyLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/T= bt/Include/Library/PeiTbtPolicyLib.h new file mode 100644 index 0000000000..45bd8f38ed --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiTbtPolicyLib.h @@ -0,0 +1,43 @@ +/** @file + Prototype of the PeiTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_LIB_H_ +#define _PEI_TBT_POLICY_LIB_H_ + +/** + Install Tbt Policy + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallPeiTbtPolicy ( + VOID + ); + +/** + Update PEI TBT Policy Callback +**/ +VOID +EFIAPI +UpdatePeiTbtPolicyCallback ( + VOID + ); + +/** + Print PEI TBT Policy +**/ +VOID +EFIAPI +TbtPrintPeiPolicyConfig ( + VOID + ); +#endif // _DXE_TBT_POLICY_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiTbtTaskDispatchLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Feat= ures/Tbt/Include/Library/PeiTbtTaskDispatchLib.h new file mode 100644 index 0000000000..44ae01a3f7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiTbtTaskDispatchLib.h @@ -0,0 +1,61 @@ +/** @file + PEI TBT Task Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__ +#define __PEI_TBT_TASK_DISPATCH_LIB_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef +EFI_STATUS +(EFIAPI *TBT_TASK) ( + PEI_TBT_POLICY *PeiTbtConfig +); + +typedef enum { + TBT_NULL, ///< All policy flags turned off. + TBT_NORMAL =3D (1 << 0), ///< Execute TBT function on cold reset. + TBT_S3 =3D (1 << 1), ///< Execute TBT function on S3 exit. + TBT_S4 =3D (1 << 2), ///< Execute TBT function on S4 exit. + TBT_ALL =3D MAX_UINTN ///< Execute TBT function always. +} TBT_BOOT_MODE; + +typedef struct { + TBT_TASK TbtTask; ///< Ptr to function to execute, with par= ameter list. + TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on TbtBootModeFlag + CHAR8 *String; ///< Output string describing this task. +} TBT_CALL_TABLE_ENTRY; + +/** + Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE +**/ +TBT_BOOT_MODE +TbtGetBootMode ( + VOID +); + +/** + TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTR= Y + + @param[in] TBT_CALL_TABLE_ENTRY TbtCallTable + +**/ +VOID +TbtTaskDistpach ( + IN TBT_CALL_TABLE_ENTRY *TbtCallTable +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/TbtCommonLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/= Include/Library/TbtCommonLib.h new file mode 100644 index 0000000000..3e9e7c4b76 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/T= btCommonLib.h @@ -0,0 +1,261 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_COMMON_LIB_H_ +#define _TBT_COMMON_LIB_H_ + +#include +#include + +#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP 0 // @todo : Update when on= ce finalized +#define DEFAULT_PCI_BUS_NUMBER_ITBT_RP 0 +#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP 0x07 + +#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0 +#define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0 +#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D +#define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02 + +#define DTBT_CONTROLLER 0x00 +#define DTBT_TYPE_PCH 0x01 +#define DTBT_TYPE_PEG 0x02 +#define ITBT_CONTROLLER 0x80 +#define TBT2PCIE_ITBT_R 0xEC +#define PCIE2TBT_ITBT_R 0xF0 +#define TBT2PCIE_DTBT_R 0x548 +#define PCIE2TBT_DTBT_R 0x54C + +#define INVALID_RP_CONTROLLER_TYPE 0xFF + +// +// Thunderbolt FW OS capability +// +#define NO_OS_NATIVE_SUPPORT 0 +#define OS_NATIVE_SUPPORT_ONLY 1 +#define OS_NATIVE_SUPPORT_RTD3 2 + +#define ITBT_SAVE_STATE_OFFSET BIT4 // Bits 4-7 is for ITBT (HIA0/1/2/Res= erved) +#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 i= s in use) +/** +Get Tbt2Pcie Register Offset + +@param[in] Type ITBT (0x80) or DTBT (0x00) +@retval Register Register Variable +**/ + +#define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function= , RegisterAddress) \ + if (Type =3D=3D ITBT_CONTROLLER) { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, TBT2PCIE_ITBT_R); \ + } else { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, TBT2PCIE_DTBT_R); \ + } + +/** +Get Pcie2Tbt Register Offset + +@param[in] Type ITBT (0x80) or DTBT (0x00) +@retval Register Register Variable +**/ + +#define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function= , RegisterAddress) \ + if (Type =3D=3D ITBT_CONTROLLER) { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, PCIE2TBT_ITBT_R); \ + } else { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, PCIE2TBT_DTBT_R); \ + } + +#define PCIE2TBT_VLD_B BIT0 +#define TBT2PCIE_DON_R BIT0 +#define TBT_MAIL_BOX_DELAY (100*1000) +#define TBT_5S_TIMEOUT 50 +#define TBT_1S_TIMEOUT 10 +#define TBT_3S_TIMEOUT 30 + +#define PCIE2TBT_GO2SX (0x02 << 1) +#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1) +#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1) +#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1) +#define PCIE2TBT_OS_UP (0x06 << 1) +#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1) +#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1) +#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1) +#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1) +#define PCIE2TBT_BOOT_ON (0x18 << 1) +#define PCIE2TBT_BOOT_OFF (0x19 << 1) +#define PCIE2TBT_USB_ON (0x19 << 1) +#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1) +#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1) +#define PCIE2TBT_POWER_CYCLE (0x1C << 1) +#define PCIE2TBT_PREBOOTACL (0x1E << 1) +#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1) + +#define RESET_HR_BIT BIT0 +#define ENUMERATE_HR_BIT BIT1 +#ifndef AUTO +#define AUTO 0x0 +#endif + +// +//Thunder Bolt Device IDs +// + +// +// Alpine Ridge HR device IDs +// +#define AR_HR_2C 0x1576 +#define AR_HR_4C 0x1578 +#define AR_XHC 0x15B5 +#define AR_XHC_4C 0x15B6 +#define AR_HR_LP 0x15C0 +// +// Alpine Ridge C0 HR device IDs +// +#define AR_HR_C0_2C 0x15DA +#define AR_HR_C0_4C 0x15D3 +// +// Titan Ridge HR device IDs +// +#define TR_HR_2C 0x15E7 +#define TR_HR_4C 0x15EA +// +//End of Thunderbolt(TM) Device IDs +// + +typedef struct _DEV_ID { + UINT8 Segment; + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; +} DEV_ID; + +//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf +//@todo should refactor this to only be present in that driver +//@todo also definitions like this should never be in a .h file anyway +//@todo this is a quick hack to get things compiling for now +#ifdef __GNUC__ +#pragma GCC diagnostic warning "-Wunused-variable" +#endif + +/** +Based on the Security Mode Selection, BIOS drives FORCE_PWR. + +@param[in] GpioNumber +@param[in] Value +**/ +VOID +ForceDtbtPower( + IN UINT32 GpioNumber, + IN BOOLEAN Value +); + +/** + Get Security Level. + @param[in] Type ITBT (0x80) or DTBT (0x00) + @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) + @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) + @param[in] Function Function number for HIA (ITBT) or Host Router (DTB= T) + @param[in] Timeout Time out with 100 ms garnularity +**/ +UINT8 +GetSecLevel ( + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ); + +/** + Set Security Level. + @param[in] Data Security State + @param[in] Type ITBT (0x80) or DTBT (0x00) + @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) + @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) + @param[in] Function Function number for HIA (ITBT) or Host Router (DTB= T) + @param[in] Timeout Time out with 100 ms garnularity +**/ +BOOLEAN +SetSecLevel ( + IN UINT8 Data, + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ); + +/** +Execute TBT Mail Box Command + +@param[in] Command TBT Command +@param[in] Type ITBT (0x80) or DTBT (0x00) +@param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) +@param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) +@param[in] Function Function number for HIA (ITBT) or Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtCommand( + IN UINT8 Command, + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +); +/** + Check connected TBT controller is supported or not by DeviceID + + @param[in] DeviceID DeviceID of of TBT controller + + + @retval TRUE Valid DeviceID + @retval FALSE Invalid DeviceID +**/ + +BOOLEAN +IsTbtHostRouter ( + IN UINT16 DeviceID + ); + +/** + Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved +**/ +EFI_STATUS +EFIAPI +GetDTbtRpDevFun( + IN BOOLEAN Type, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFunc + ); + +/** + Internal function to Wait for Tbt2PcieDone Bit.to Set or clear + @param[in] CommandOffsetAddress Tbt2Pcie Register Address + @param[in] TimeOut Time out with 100 ms garnularity + @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) + @param[out] *Tbt2PcieValue Function Register value +**/ +BOOLEAN +InternalWaitforCommandCompletion ( + IN UINT64 CommandOffsetAddress, + IN UINT32 TimeOut, + IN BOOLEAN Tbt2PcieDone, + OUT UINT32 *Tbt2PcieValue + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pp= i/PeiTbtPolicy.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Incl= ude/Ppi/PeiTbtPolicy.h new file mode 100644 index 0000000000..17d8a62f66 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTb= tPolicy.h @@ -0,0 +1,31 @@ +/** @file +TBT PEI Policy + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_H_ +#define _PEI_TBT_POLICY_H_ + +#include + +#pragma pack(push, 1) + +#define PEI_TBT_POLICY_REVISION 1 + +/** + TBT PEI configuration\n + Revision 1: + - Initial version. +**/ +typedef struct _PEI_TBT_POLICY { + DTBT_COMMON_CONFIG DTbtCommonConfig; = ///< dTbt Common Configuration + DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]= ; ///< dTbt Controller Configuration +} PEI_TBT_POLICY; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= ivate/Library/PeiDTbtInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fea= tures/Tbt/Include/Private/Library/PeiDTbtInitLib.h new file mode 100644 index 0000000000..bb30c2c0ec --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/L= ibrary/PeiDTbtInitLib.h @@ -0,0 +1,130 @@ +/** @file + PEI DTBT Init Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_DTBT_INIT_LIB_H__ +#define __PEI_DTBT_INIT_LIB_H__ + +#include +#include + +extern TBT_CALL_TABLE_ENTRY DTbtCallTable[]; + +/** + Get Thunderbolt(TM) (TBT) PEI Policy Data. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtGetPeiTbtPolicyData ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Toggle related GPIO pin for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtToggleGPIO ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + set tPCH25 Timing to 10 ms for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSetTPch25Timing ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Do ForcePower for DTBT Controller + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtForcePower ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Clear VGA Registers for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtClearVgaRegisters ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "Boot On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtBootOn ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "USB On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtUsbOn ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "Sx Exit". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSxExitFlow ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= ivate/Library/PeiTbtCommonInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h new file mode 100644 index 0000000000..0ed13fd300 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/L= ibrary/PeiTbtCommonInitLib.h @@ -0,0 +1,51 @@ +/** @file + PEI TBT Common Init Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_TBT_COMMON_INIT_LIB_H__ +#define __PEI_TBT_COMMON_INIT_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +BOOLEAN +IsHostRouterPresentBeforeSleep( +IN UINT8 ControllerType, +IN UINT8 Controller +); + +VOID +TbtSetSxMode( +IN BOOLEAN Type, +IN UINT8 Bus, +IN UINT8 Device, +IN UINT8 Function, +IN UINT8 TbtBootOn +); + +VOID +TbtClearVgaRegisters( +IN UINTN Segment, +IN UINTN Bus, +IN UINTN Device, +IN UINTN Function +); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/DisableBmeProtocol.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Featur= es/Tbt/Include/Protocol/DisableBmeProtocol.h new file mode 100644 index 0000000000..1948c252f0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= DisableBmeProtocol.h @@ -0,0 +1,36 @@ +/** @file + Definitions for DisableBmeProtocol + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DISABLE_TBT_BME_PROTOCOL_H_ +#define _DISABLE_TBT_BME_PROTOCOL_H_ + +typedef struct EFI_DISABLE_BME_PROTOCOL EFI_DISABLE_TBT_BME_PROTOCOL; + +/** + This is for disable TBT BME bit under shell environment + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +typedef +VOID +(EFIAPI *DISABLE_BUS_MASTER_ENABLE) ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +struct EFI_DISABLE_BME_PROTOCOL { + DISABLE_BUS_MASTER_ENABLE DisableBme; +}; + +extern EFI_GUID gDxeDisableTbtBmeProtocolGuid; + + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/DxeTbtPolicy.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt= /Include/Protocol/DxeTbtPolicy.h new file mode 100644 index 0000000000..437f6a8401 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= DxeTbtPolicy.h @@ -0,0 +1,137 @@ +/** @file +TBT DXE Policy + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_H_ +#define _DXE_TBT_POLICY_H_ + +#include + +#pragma pack(push, 1) + +#define DXE_TBT_POLICY_REVISION 1 + +// +// TBT Common Data Structure +// +typedef struct _TBT_COMMON_CONFIG{ + /** + TBT Security Level + 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Co= nnect, 3: SL3 Display Port and USB + **/ + UINT32 SecurityMode : 3; + /** + BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH= GPIOs + 0: Disabled, 1: Enabled + **/ + UINT32 Gpio5Filter : 1; + /** + WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping + 0: Disabled, 1: Enabled + **/ + UINT32 TrA0OsupWa : 1; + /** + Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport + 0: Disabled, 1: Enabled + **/ + UINT32 TbtWakeupSupport : 1; + /** + SMI TBT enumeration + 0: Disabled, 1: Enabled + **/ + UINT32 TbtHotSMI : 1; + /** + Notify PCIe RP after Hot-Plug/Hot-Unplug occurred. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtHotNotify : 1; + /** + CLK REQ for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtSetClkReq : 1; + /** + ASPM setting for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: L0s, 2: L1, 3: L0sL1 + **/ + UINT32 TbtAspm : 2; + /** + L1 SubState for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: L1.1, 2: L1.1 & L1.2 + **/ + UINT32 TbtL1SubStates : 2; + /** + LTR for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtLtr : 1; + /** + PTM for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtPtm : 1; + /** + TBT Dynamic AC/DC L1. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtAcDcSwitch : 1; + /** + TBT RTD3 Support. + 0: Disabled, 1: Enabled + **/ + UINT32 Rtd3Tbt : 1; + /** + TBT ClkReq for RTD3 Flow. + 0: Disabled, 1: Enabled + **/ + UINT32 Rtd3TbtClkReq : 1; + /** + TBT Win10support for Tbt FW execution mode. + 0: Disabled, 1: Native, 2: Native + RTD3 + **/ + UINT32 Win10Support : 2; + /** + TbtVtdBaseSecurity + 0: Disabled, 1: Enabled + **/ + UINT32 TbtVtdBaseSecurity: 1; + /** + Control Iommu behavior in pre-boot + 0: Disabled Iommu, 1: Enable Iommu, Disable exception list, 2: = Enable Iommu, Enable exception list + **/ + UINT32 ControlIommu : 3; + UINT32 Rsvd0 : 8; ///< Reserved bits + UINT16 Rtd3TbtClkReqDelay; + UINT16 Rtd3TbtOffDelay; +} TBT_COMMON_CONFIG; + +// +// dTBT Resource Data Structure +// +typedef struct _DTBT_RESOURCE_CONFIG{ + UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP = that connect to dTBT Host Router + UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP = that connect to dTBT Host Router + UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource= for PCIe RP that connect to dTBT Host Router + UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP= that connect to dTBT Host Router + UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resourc= e for PCIe RP that connect to dTBT Host Router + UINT8 Reserved[1]; ///< Reserved for DWORD alignment +} DTBT_RESOURCE_CONFIG; + +/** + TBT DXE configuration\n + Revision 1: + - Initial version. +**/ +typedef struct _DXE_TBT_POLICY_PROTOCOL { + TBT_COMMON_CONFIG TbtCommonConfig; = ///< Tbt Common Information + DTBT_RESOURCE_CONFIG DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER]; = ///< dTbt Resource Configuration +} DXE_TBT_POLICY_PROTOCOL; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/TbtNvsArea.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/I= nclude/Protocol/TbtNvsArea.h new file mode 100644 index 0000000000..e6654b4094 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= TbtNvsArea.h @@ -0,0 +1,50 @@ +/** @file + This file defines the TBT NVS Area Protocol. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_NVS_AREA_H_ +#define _TBT_NVS_AREA_H_ + +// +// Platform NVS Area definition +// +#include + +// +// Includes +// +#define TBT_NVS_DEVICE_ENABLE 1 +#define TBT_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// +typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL; + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gTbtNvsAreaProtocolGuid; + +/** + Making any TBT_NVS_AREA structure change after code frozen + will need to maintain backward compatibility, bump up + structure revision and update below history table\n + Revision 1: - Initial version.\n + Revision 2: - Adding TBT NVS AREA Revision, Deprecated DTbtCont= rollerEn0, DTbtControllerEn1.\n +**/ +#define TBT_NVS_AREA_REVISION 2 + +// +// Platform NVS Area Protocol +// +typedef struct _TBT_NVS_AREA_PROTOCOL { + TBT_NVS_AREA *Area; +} TBT_NVS_AREA_PROTOCOL; + +#endif // _TBT_NVS_AREA_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tBoardInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/= TbtBoardInfo.h new file mode 100644 index 0000000000..bd5e577fbe --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtBoardI= nfo.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_INFO_GUID_H_ +#define _TBT_INFO_GUID_H_ +#include + +#pragma pack(1) +// +// TBT Info HOB +// +typedef struct _TBT_INFO_HOB { + EFI_HOB_GUID_TYPE EfiHobGuidType; + DTBT_COMMON_CONFIG DTbtCommonConfig; = ///< dTbt Common Configuration + DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]= ; ///< dTbt Controller Configuration +} TBT_INFO_HOB; +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tNvsAreaDef.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include= /TbtNvsAreaDef.h new file mode 100644 index 0000000000..21e17b4609 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAre= aDef.h @@ -0,0 +1,68 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define TBT NVS Area operation region. + // + +#ifndef _TBT_NVS_AREA_DEF_H_ +#define _TBT_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT8 ThunderboltSmiFunction; ///< Offset 0 Th= underbolt(TM) SMI Function Number + UINT8 ThunderboltHotSmi; ///< Offset 1 SM= I on Hot Plug for TBT devices + UINT8 TbtWin10Support; ///< Offset 2 Tb= tWin10Support + UINT8 TbtGpioFilter; ///< Offset 3 Gp= io filter to detect USB Hotplug event + UINT8 ThunderboltHotNotify; ///< Offset 4 No= tify on Hot Plug for TBT devices + UINT8 TbtSelector; ///< Offset 5 Th= underbolt(TM) Root port selector + UINT8 WAKFinished; ///< Offset 6 WA= K Finished + UINT8 DiscreteTbtSupport; ///< Offset 7 Th= underbolt(TM) support + UINT8 TbtAcpiRemovalSupport; ///< Offset 8 Tb= tAcpiRemovalSupport + UINT32 TbtFrcPwrEn; ///< Offset 9 Tb= tFrcPwrEn + UINT32 TbtFrcPwrGpioNo0; ///< Offset 13 Tb= tFrcPwrGpioNo + UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17 Tb= tFrcPwrGpioLevel + UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18 Tb= tCioPlugEventGpioNo + UINT32 TbtPcieRstGpioNo0; ///< Offset 22 Tb= tPcieRstGpioNo + UINT8 TbtPcieRstGpioLevel0; ///< Offset 26 Tb= tPcieRstGpioLevel + UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27 Cu= rrent Port that has plug event + UINT8 RootportSelected0; ///< Offset 28 Ro= ot port Selected by the User + UINT8 RootportSelected0Type; ///< Offset 29 Ro= ot port Type + UINT8 RootportSelected1; ///< Offset 30 Ro= ot port Selected by the User + UINT8 RootportSelected1Type; ///< Offset 31 Ro= ot port Type + UINT8 RootportEnabled0; ///< Offset 32 Ro= ot port Enabled by the User + UINT8 RootportEnabled1; ///< Offset 33 Ro= ot port Enabled by the User + UINT32 TbtFrcPwrGpioNo1; ///< Offset 34 Tb= tFrcPwrGpioNo + UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38 Tb= tFrcPwrGpioLevel + UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39 Tb= tCioPlugEventGpioNo + UINT32 TbtPcieRstGpioNo1; ///< Offset 43 Tb= tPcieRstGpioNo + UINT8 TbtPcieRstGpioLevel1; ///< Offset 47 Tb= tPcieRstGpioLevel + UINT8 TBtCommonGpioSupport; ///< Offset 48 Se= t if Single GPIO is used for Multi/Different Controller Hot plug support + UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49 Ro= ot Port type for which SCI Triggered + UINT8 TrOsup; ///< Offset 50 Ti= tan Ridge Osup command + UINT8 TbtAcDcSwitch; ///< Offset 51 TB= T Dynamic AcDc L1 + UINT8 DTbtControllerEn0; ///< Offset 52 DT= btController0 is enabled or not. @deprecated since revision 2 + UINT8 DTbtControllerEn1; ///< Offset 53 DT= btController1 is enabled or not. @deprecated since revision 2 + UINT8 TbtAspm; ///< Offset 54 AS= PM setting for all the PCIe device in TBT daisy chain. + UINT8 TbtL1SubStates; ///< Offset 55 L1= SubState for for all the PCIe device in TBT daisy chain. + UINT8 TbtSetClkReq; ///< Offset 56 CL= K REQ for all the PCIe device in TBT daisy chain. + UINT8 TbtLtr; ///< Offset 57 LT= R for for all the PCIe device in TBT daisy chain. + UINT8 TbtPtm; ///< Offset 58 PT= M for for all the PCIe device in TBT daisy chain. + UINT8 TbtWakeupSupport; ///< Offset 59 Se= nd Go2SxNoWake or GoSxWake according to TbtWakeupSupport + UINT16 Rtd3TbtOffDelay; ///< Offset 60 Rt= d3TbtOffDelay TBT RTD3 Off Delay + UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62 Tb= tSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB= at Sx entry point. HW logic is required. + UINT8 Rtd3TbtSupport; ///< Offset 63 En= able Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup. + UINT8 Rtd3TbtClkReq; ///< Offset 64 En= able TBT RTD3 CLKREQ mask. + UINT16 Rtd3TbtClkReqDelay; ///< Offset 65 TB= T RTD3 CLKREQ mask delay. + // + // Revision Field: + // + UINT8 TbtRevision; ///< Offset 67 Re= vison of TbtNvsArea +} TBT_NVS_AREA; + +#pragma pack(pop) +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tPolicyCommonDefinition.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features= /Tbt/Include/TbtPolicyCommonDefinition.h new file mode 100644 index 0000000000..7771fc7a95 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtPolicy= CommonDefinition.h @@ -0,0 +1,84 @@ +/** @file +TBT Policy Common definition. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_POLICY_COMMON_H_ +#define _TBT_POLICY_COMMON_H_ + +#include +#include + +#define MAX_DTBT_CONTROLLER_NUMBER 2 + +#define TYPE_PCIE 0x01 +#define TYPE_PEG 0x02 + +#pragma pack(push, 1) + +// +// dTBT Force Power GPIO Data Structure +// +typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High + UINT8 Reserved[3]; ///< Reserved for DWORD alignmen= t +} DTBT_FORCE_POWER_GPIO_CONFIG; + +// +// dTBT CIO Plug Event GPIO Data Structure +// +typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will ch= ange the XTBT method to the _Lxx or _Exx that we assign in this item. + BOOLEAN AcpiGpeSignaturePorting; ///< 0 =3D No porting required(f= or 2-tier GPI GPE event architecture), 1 =3D Porting required(for 1-tier GP= I GPE event architecture) + UINT8 Reserved[3]; ///< Reserved for DWORD alignmen= t +} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG; + +// +// dTBT PCIE Reset GPIO Data Structure +// +typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High + UINT8 Reserved[3]; ///< Reserved for DWORD alignmen= t +} DTBT_PCIE_RESET_GPIO_CONFIG; + +// +// dTBT Controller Data Structure +// +typedef struct _DTBT_CONTROLLER_CONFIG { + UINT8 DTbtControllerEn; ///< Enable/Disable DT= btController. + UINT8 Type; ///< 01-Pcie RP, 02- P= EG,Reserved. + UINT8 PcieRpNumber; ///< RP Number/ PEG Po= rt (0,1,2) that connecet to dTBT controller. + DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that= can force dTBT Power On. + DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that= can generate Hot-Plug event. + DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that= is use to perform Reset when platform enters to Sx, it is required for pla= tforms where PCI_RST pin connected to Tbt is controlled with GPIO + GPIO_PAD PdResetGpioPad; ///< PD HRESET GPIO Pa= d Number + GPIO_PAD PdSxEntryGpioPad; ///< PD SX Entry GPIO = Pad Number + GPIO_PAD PdSxAckGpioPad; ///< PD SX Ack GPIO Pa= d Number + UINT8 Reserved[1]; ///< Reserved for DWOR= D alignment +} DTBT_CONTROLLER_CONFIG; + +// +// dTBT Controller Data Structure +// +typedef struct _DTBT_COMMON_CONFIG { + UINT8 TbtBootOn; ///< Send BootOn Mailbox = command when TbtBootOn is enabled. + UINT8 TbtUsbOn; ///< Send UsbOn Mailbox c= ommand when TbtBootOn is enabled. + UINT8 Gpio3ForcePwr; ///< Force GPIO to power = on or not + UINT16 Gpio3ForcePwrDly; ///< The delay time after= do ForcePwr + BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT contro= llers share the same GPIO pin + BOOLEAN PcieRstSupport; ///< 0 =3D Not Support, 1= =3D Supported. it is required for platforms where PCI_RST pin connected to= Tbt is controlled with GPIO + UINT8 SecurityMode; ///< 0: SL0 No Security, = 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and U= SB + UINT8 ControlIommu; ///< Control Iommu behavi= or in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list,= 2: Enable Iommu, Enable exception list + UINT8 Reserved[3]; ///< Reserved for DWORD a= lignment +} DTBT_COMMON_CONFIG; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsA= reaDef.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAre= aDef.h new file mode 100644 index 0000000000..d8021e8c22 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.= h @@ -0,0 +1,118 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + +#ifndef _GLOBAL_NVS_AREA_DEF_H_ +#define _GLOBAL_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + // + // Miscellaneous Dynamic Registers: + // + UINT16 OperatingSystem; ///< Offset 0 Op= erating System + UINT8 SmiFunction; ///< Offset 2 SM= I Function Call (ASL to SMI via I/O Trap) + UINT32 Port80DebugValue; ///< Offset 3 Po= rt 80 Debug Port Value + UINT8 PowerState; ///< Offset 7 Po= wer State (AC Mode =3D 1) + // + // Thermal Policy Registers: + // + UINT8 EnableDigitalThermalSensor; ///< Offset 8 Di= gital Thermal Sensor Enable + UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DT= S SMI Function Call + // + // CPU Identification Registers: + // + UINT8 ApicEnable; ///< Offset 10 AP= IC Enabled by SBIOS (APIC Enabled =3D 1) + UINT8 ThreadCount; ///< Offset 11 Nu= mber of Enabled Threads + // + // PCIe Hot Plug + // + UINT8 PcieOSCControl; ///< Offset 12 PC= IE OSC Control + UINT8 NativePCIESupport; ///< Offset 13 Na= tive PCIE Setup Value + // + // Global Variables + // + UINT8 DisplaySupportFlag; ///< Offset 14 _D= OS Display Support Flag. + UINT8 InterruptModeFlag; ///< Offset 15 Gl= obal IOAPIC/8259 Interrupt Mode Flag. + UINT8 L01Counter; ///< Offset 16 Gl= obal L01 Counter. + UINT8 LtrEnable[24]; ///< Offset 17 La= tency Tolerance Reporting Enable + ///< Offset 18 La= tency Tolerance Reporting Enable + ///< Offset 19 La= tency Tolerance Reporting Enable + ///< Offset 20 La= tency Tolerance Reporting Enable + ///< Offset 21 La= tency Tolerance Reporting Enable + ///< Offset 22 La= tency Tolerance Reporting Enable + ///< Offset 23 La= tency Tolerance Reporting Enable + ///< Offset 24 La= tency Tolerance Reporting Enable + ///< Offset 25 La= tency Tolerance Reporting Enable + ///< Offset 26 La= tency Tolerance Reporting Enable + ///< Offset 27 La= tency Tolerance Reporting Enable + ///< Offset 28 La= tency Tolerance Reporting Enable + ///< Offset 29 La= tency Tolerance Reporting Enable + ///< Offset 30 La= tency Tolerance Reporting Enable + ///< Offset 31 La= tency Tolerance Reporting Enable + ///< Offset 32 La= tency Tolerance Reporting Enable + ///< Offset 33 La= tency Tolerance Reporting Enable + ///< Offset 34 La= tency Tolerance Reporting Enable + ///< Offset 35 La= tency Tolerance Reporting Enable + ///< Offset 36 La= tency Tolerance Reporting Enable + ///< Offset 37 La= tency Tolerance Reporting Enable + ///< Offset 38 La= tency Tolerance Reporting Enable + ///< Offset 39 La= tency Tolerance Reporting Enable + ///< Offset 40 La= tency Tolerance Reporting Enable + UINT8 ObffEnable[24]; ///< Offset 41 Op= timized Buffer Flush and Fill + ///< Offset 42 Op= timized Buffer Flush and Fill + ///< Offset 43 Op= timized Buffer Flush and Fill + ///< Offset 44 Op= timized Buffer Flush and Fill + ///< Offset 45 Op= timized Buffer Flush and Fill + ///< Offset 46 Op= timized Buffer Flush and Fill + ///< Offset 47 Op= timized Buffer Flush and Fill + ///< Offset 48 Op= timized Buffer Flush and Fill + ///< Offset 49 Op= timized Buffer Flush and Fill + ///< Offset 50 Op= timized Buffer Flush and Fill + ///< Offset 51 Op= timized Buffer Flush and Fill + ///< Offset 52 Op= timized Buffer Flush and Fill + ///< Offset 53 Op= timized Buffer Flush and Fill + ///< Offset 54 Op= timized Buffer Flush and Fill + ///< Offset 55 Op= timized Buffer Flush and Fill + ///< Offset 56 Op= timized Buffer Flush and Fill + ///< Offset 57 Op= timized Buffer Flush and Fill + ///< Offset 58 Op= timized Buffer Flush and Fill + ///< Offset 59 Op= timized Buffer Flush and Fill + ///< Offset 60 Op= timized Buffer Flush and Fill + ///< Offset 61 Op= timized Buffer Flush and Fill + ///< Offset 62 Op= timized Buffer Flush and Fill + ///< Offset 63 Op= timized Buffer Flush and Fill + ///< Offset 64 Op= timized Buffer Flush and Fill + UINT8 Rtd3Support; ///< Offset 65 Ru= ntime D3 support. + UINT8 LowPowerS0Idle; ///< Offset 66 Lo= w Power S0 Idle Enable + UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Vi= rtual GPIO button Notify Sleep State Change + UINT8 PstateCapping; ///< Offset 68 P-= state Capping + UINT8 Ps2MouseEnable; ///< Offset 69 Ps= 2 Mouse Enable + UINT8 Ps2KbMsEnable; ///< Offset 70 Ps= 2 Keyboard and Mouse Enable + // + // Driver Mode + // + UINT32 GpioIrqRoute; ///< Offset 71 GP= IO IRQ + UINT8 PL1LimitCS; ///< Offset 75 se= t PL1 limit when entering CS + UINT16 PL1LimitCSValue; ///< Offset 76 PL= 1 limit value + UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10= sec Power button support + UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pc= i Delay Optimization Ecr + UINT8 TbtSupport; ///< Offset 80 Th= underbolt(TM) support + UINT8 TbtNativeOsHotPlug; ///< Offset 81 Tb= tNativeOsHotPlug + UINT8 TbtSelector; ///< Offset 82 Th= underbolt(TM) Root port selector + UINT8 TbtSelector1; ///< Offset 83 Th= underbolt(TM) Root port selector +} EFI_GLOBAL_NVS_AREA; + +#pragma pack(pop) +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst= .h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h new file mode 100644 index 0000000000..bbdeb71da5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h @@ -0,0 +1,51 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ATTEMPT_USB_FIRST_H_ +#define _ATTEMPT_USB_FIRST_H_ + +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO { + UINT8 RevisonId; // Structure Revision ID + UINT8 HotkeyTriggered; // Hot key status +} ATTEMPT_USB_FIRST_HOTKEY_INFO; +#pragma pack() + +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_VARIABLE { + UINT8 UsbBootPrior; +} ATTEMPT_USB_FIRST_VARIABLE; +#pragma pack() + +// +// Volatile variable definition for Attempt USB first features +// +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE { + UINT8 RevisonId; // Structure Revision ID + UINT8 UsbFirstEnable; // Attempt USB First is enabled or not +} ATTEMPT_USB_FIRST_RUNTIME_VARIABLE; +#pragma pack() + +// +// Volatile variable definition for third party Default Enabling via UEFI = Variable. +// +#pragma pack(1) +typedef struct _ENABLE_CUSTOM_DEFAULTS{ + UINT32 EnableCustomDefaults; +} ENABLE_CUSTOM_DEFAULTS; +#pragma pack() + +#define COENG_DEFAULTS_UNKNOWN 0 +#define COENG_DEFAULTS_SUPPORTED 1 +#define COENG_DEFAULTS_VAR_EXITS 2 +#define COENG_DEFAULTS_VAR_SET 4 +#define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULT= S_VAR_EXITS |COENG_DEFAULTS_VAR_SET) + +extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid; +extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid; +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h new file mode 100644 index 0000000000..17ccd56373 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPUSMM_H_ +#define _CPUSMM_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, { 0x8c, 0x77, 0xc8, 0x2f= , 0xf1, 0xe, 0x3c, 0x81 }} +#define CPUSMM_SETUP_NAME L"CpuSmm" + +#pragma pack(1) +typedef struct { + UINT8 CpuSmmMsrSaveStateEnable; + UINT8 CpuSmmCodeAccessCheckEnable; + UINT8 CpuSmmUseDelayIndication; + UINT8 CpuSmmUseBlockIndication; + UINT8 CpuSmmUseSmmEnableIndication; + UINT8 CpuSmmProcTraceEnable; +} CPU_SMM; +#pragma pack() + +#ifndef OFFSET_OF +#ifdef __GNUC__ +#if __GNUC__ >=3D 4 +#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field)) +#endif +#endif +#endif + +#ifndef OFFSET_OF +#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) +#endif + +#define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYP= E##Field[(OFFSET_OF(TYPE, Field) =3D=3D Offset) / (OFFSET_OF(TYPE, Field) = =3D=3D Offset)] + +// +// If TpmSupport/MorStae isn't in this offset, build failure (0 size array= or divided by 0) will be generated. +// Platform DSC file maps the two field to HII PCD so the offset value is = critical. +// +VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0); +VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4); +VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigu= rations.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigur= ations.h new file mode 100644 index 0000000000..b7202a6b4a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigurations= .h @@ -0,0 +1,20 @@ +/** @file + This header file provides definitions of firmware configuration. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FIRMWARE_CONFIGURATION_H_ +#define _FIRMWARE_CONFIGURATION_H_ + +typedef enum { + FwConfigDefault =3D 0, + FwConfigProduction, + FwConfigTest, + FwConfigMax +} FW_CONFIG; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h = b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h new file mode 100644 index 0000000000..ed63b28adf --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h @@ -0,0 +1,1766 @@ +/** @file +Header file for GOP Configuration Library + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_CONFIG_LIB_H_ +#define _GOP_CONFIG_LIB_H_ + +#include +#include +#pragma pack(1) +#define GOP_CONFIG_VBT_REVISION 0xC1 + +#define ChildStruct_MAX 8 ///< Maximum numbe= r of child structures in VBT +#define CompressionStruct_MAX 2 ///< Maximum numbe= r of compression parameter structures in VBT. +#define NO_DEVICE 0x00 ///< Defines a nul= l display class. +#define DISPLAY_PORT_ONLY 0x68C6 ///< Defines a dis= play class of Integrated Display Port Only +#define DISPLAY_PORT_HDMI_DVI_COMPATIBLE 0x60D6 ///< Defines a dis= play class of Integrated DisplayPort with HDMI/DVI Compatible +#define DISPLAY_PORT_DVI_COMPATIBLE 0x68D6 ///< Defines a dis= play class of Integrated DisplayPort with DVI Compatible +#define HDMI_DVI 0x60D2 ///< Defines a dis= play class of Integrated HDMI/DVI +#define DVI_ONLY 0x68D2 ///< Defines a dis= play class of Integrated DVI Only +#define MIPI_ONLY 0x1400 +#define eDP_ONLY 0x1806 ///< Defines a dis= play class of eDP only +#define AUX_CHANNEL_A 0x40 +#define AUX_CHANNEL_B 0x10 +#define AUX_CHANNEL_C 0x20 +#define AUX_CHANNEL_D 0x30 +#define NO_PORT 0x00 ///< Defines a out= put port NA +#define HDMI_B 0x01 ///< Defines a out= put port HDMI-B +#define HDMI_C 0x02 ///< Defines a out= put port HDMI-C +#define HDMI_D 0x03 ///< Defines a out= put port HDMI-D +#define HDMI_F 0x0E ///< Defines a out= put port HDMI-D +#define DISPLAY_PORT_A 0x0A ///< Defines a out= put port DisplayPort A +#define DISPLAY_PORT_B 0x07 ///< Defines a out= put port DisplayPort B +#define DISPLAY_PORT_C 0x08 ///< Defines a out= put port DisplayPort C +#define DISPLAY_PORT_D 0x09 ///< Defines a out= put port DisplayPort D +#define DISPLAY_PORT_E 0x0B ///< Defines a out= put port DisplayPort E +#define DISPLAY_PORT_F 0x0D ///< Defines a out= put port DisplayPort F +#define PORT_MIPI_A 0x15 ///< Mipi Port A +#define PORT_MIPI_C 0x17 ///< Mipi Port C + +typedef struct { + UINT16 Dclk; // DClk in 10 KHz + UINT8 HActive; // HActive [7:0] + UINT8 HBlank; // HBlank [7:0] + UINT8 HA_HB_UpperNibble; // Upper nibble =3D HActive [11:8] + UINT8 VActive; // VActive [7:0] + UINT8 VBlank; // VBlank [7:0] + UINT8 VA_VB_UpperNibble; // Upper nibble =3D VActive [11:8] + UINT8 HSyncOffset; // HSync offset from blank start L= SB + UINT8 HPulseWidth; // HSync Pulse Width, LSB + UINT8 VsyncOffset_VpulseWidth_LSB; // Bits 7:4 =3D VSync offset [3:0] + UINT8 HSO_HSPW_V_High; // Bits 7:6 =3D HSync Offset [9:8] + UINT8 HorImageSize; // Horizontal Image Size + UINT8 VerImageSize; // Vertical Image Size + UINT8 HIS_VIS_High; // UpperLmtH_V Upper limits of H. = and V. image size + UINT8 HBorder; // Horizontal Border + UINT8 VBorder; // Vertical Border + UINT8 Flags; // Flags +} DTD_STRUCTURE; // 18 Bytes + +typedef struct { + UINT16 XRes; + UINT16 YRes; + UINT32 SerialNo; + UINT8 Week; + UINT8 Year; +} PID_DATA; // 10 Bytes + +// +// VBT Header +// +/** + This structure defines the VBT Header. +**/ +typedef struct { + UINT8 Product_String[20]; ///< "$VBT_Cannonlake" is the product string + UINT16 Version_Num; ///< Defines the VBT Header version number. + UINT16 Header_Size; ///< Defines the size of VBT Header. + UINT16 Table_Size; ///< Defines the size of complete VBT. + UINT8 Checksum; ///< Defines the checksum of entire VBT + UINT8 Reserved1; ///< Reserved field 1 of 1 byte. + UINT32 Bios_Data_Offset; ///< Defines the offset of VBT Data block. + UINT32 Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks. +} VBT_HEADER; + +/** + This structure defines the VBT BIOS Data Block Header +**/ +typedef struct { + UINT8 BDB_Signature[16]; ///< Defines the Bios Data Block signature "= BIOS_DATA_BLOCK". + UINT16 BDB_Version; ///< Defines the VBT (data) version. + UINT16 BDB_Header_Size; ///< Defines the size of VBT Bios data block= header. + UINT16 BDB_Size; ///< Defines the size of Bios data block. +} VBT_BIOS_DATA_HEADER; + +/** + This structure defines the BMP Signon Message and Copyright Message Stru= cture +**/ +typedef struct { + UINT8 BlockId; ///< Defines Block ID : 254 + UINT16 BlockSize; ///< Defines the size of BMP Signon block. + + UINT16 Bmp_BIOS_Size; ///< Defines the BIOS size 32k/48k/64k. + UINT8 BIOS_Type; ///< Defines the type of BIOS desktop or mob= ile. + UINT8 RelStatus; ///< Defines the release status of the curre= nt GOP driver. + UINT8 BIOS_HW; ///< Defines the Hardware i.e. Cannonlake. + UINT8 INT_HW; ///< Defines the integrated hardware support= ed eDP/HDMI/DP. + UINT8 Build_Number[4]; ///< Defines the build number string. + UINT8 SignOn[155]; ///< Defines the sign on message. + UINT8 CopyRight[61]; ///< Defines the copyright message. +} BMP_STRUCTURE_SIGNON; + +/** + This structure defines the BMP General Bits +**/ +typedef struct { + UINT16 bmp_BIOS_CS; ///< Defines the start of BIOS code segmen= t + UINT8 bmp_DOS_Boot_Mode; ///< Defines the mode number to set when D= OS is boot + UINT8 bmp_BW_Percent; ///< Set percentage of total memory BW + UINT8 bmp_Popup_Mem_Size; ///< Default Popup memory size in KB + UINT8 bmp_Resize_PCI_BIOS; ///< BIOS size granularity in 0.5 KB + UINT8 Switch_CRT_To_DDC2; ///< Obsolete field: Is the CRT already sw= itched to DDC2 + UINT8 bmp_Allow_Config; ///< Bit 1 : 1, Enable aspect ratio for DO= S + ///< Bit 0 : 1, Allow boot to DVI even if = it is not attached. +} BMPGEN; + +/** + This structure defines Block 254 (BMP structure) +**/ +typedef struct { + BMP_STRUCTURE_SIGNON bmp_Signon_Message; ///< Instance of signon an= d copyright message structure + BMPGEN bmp_General_Bytes; ///< Instance of BMP Gener= al Bits structure. +} BLOCK254_BMP_Structure; + +/** + This structure defines Block 1 (General Bytes Definitions) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID (1) + UINT16 BlockSize; ///< Defines the size of General bytes definitio= n block. + + /** + BMP General Bit Definitions 1\n + Bit 7 =3D DVO A color flip bit + =3D 0, No DVO A color flip + =3D 1, Flip DVO A color + Bits 6:4 =3D Clear screen (CLS) after Signon + =3D 000, No CLS + =3D 001, 0.5 sec pause and then CLS + =3D 010, 1.0 sec pause and then CLS + =3D 011, 1.5 sec pause and then CLS + =3D 100, 2.0 sec pause and then CLS + =3D 101, 2.5 sec pause and then CLS + =3D 110, 3.0 sec pause and then CLS + =3D 111, 3.5 sec pause and then CLS + Bit 3 =3D 1 Enable Display Signon + Bit 2 =3D 1 Enable Flex-aim Support + Bits 1:0 =3D Flat panel fitting enabling + =3D 00, Centering + =3D 01, Reserved + =3D 10, Aspect scaling + =3D 11, Fullscreen + **/ + union { + UINT8 Value; + struct { + UINT8 PanelFitterEnabling:2; + UINT8 FlexAimSupportEnable:1; + UINT8 DisplaySignonEnable:1; + UINT8 ClearScreenTime:3; + UINT8 DvoAColorFlipEnable:1; + } Bits; + } bmp_Bits_1; + + /** + BMP General Bit Definitions\n + Bit 7 =3D Hot plug support + =3D 0, Hot plug disabled + =3D 1, Hot plug enabled + Bit 6 =3D Dynamic CD clock feature + =3D 0, Dynamic CD clock feature is disabled + =3D 1, Dynamic CD clock feature is enabled + Bit 5 =3D Underscan support for VGA timings + Bit 4 =3D Disable SSC in Dual Display Twin Mode. (This field is obsolete= now. Kept for VBIOS only.) + =3D 0, No + =3D 1, Yes + Bit 3 =3D LFP power state on override by 5f64h,08h + =3D 0, No Override + =3D 1, Override + Bit 2 =3D Internal LVDS SSC frequency. (This field is obsolete now. Kept= for VBIOS only.) + =3D 0, 96/120MHz + =3D 1, 100MHz + Bit 1 =3D internal LVDS SSC (Spread Spectrum Clock) (This field is obsol= ete now. Kept for VBIOS only.) + =3D 0, Disabled + =3D 1, Enabled + Bit 0 =3D KvmrSessionEnable. + =3D 0, Disabled + =3D 1, Enabled + **/ + union { + UINT8 Value; + struct { + UINT8 KvmrSessionEnable:1; + UINT8 Reserved_1:5; + UINT8 DynamicCdClockEnable:1; + UINT8 HotPlugEnable:1; + } Bits; + } bmp_Bits_2; + + /** + BMP General Bit Definitions 3\n + Bit 7 =3D Ignore strap status + =3D 0 Do not ignore + =3D 1 Ignore + Bit 6 =3D Panel Timing algorithm + =3D 0 Preferred timings + =3D 1 Best fit timings + Bit 5 Copy iLFP DTD to SDVO LVDS DTD + =3D 0 Don't copy DTD + =3D 1 Copy DTD to + Bit 4 =3D VBIOS normal/extd. DT mode + =3D 0 Normal mode + =3D 1 DUAL mode + Bit 3 =3D FDI RX Polarity + =3D 0 Normal + =3D 1 Inverted + Bit 2 =3D Enable 180 Degree Rotation + =3D 0 Disable + =3D 1 Enable + Bit 1 =3D Single DVI-I connector for CRT and DVI display: Obsolete field + =3D 0 Disabled + =3D 1 Enabled + Bit 0 =3D Smooth Vision + =3D 0 Disabled + =3D 1 Enabled + **/ + union { + UINT8 Value; + struct { + UINT8 Reserved1:1; + UINT8 SingleDviiCrtConnector:1; + UINT8 Enable180DegRotation:1; + UINT8 FdiRxPolarity:1; + UINT8 Reserved2:4; + } Bits; + } bmp_Bits_3; + + UINT8 Reserved; ///< Reserved field. It was Legacy_Monitor_Detect = in previous platforms. + + /** + Integrated display device support\n + Bits 7:6 =3D Reserved + Bit 5 =3D DP SSC Dongle Enable/Disable + Bit 4 =3D DP SSC Frequency. (This field is obsolete now. Kept for VBIOS = only.) + =3D 0, 96 MHz + =3D 1, 100 MHz + Bit 3 =3D DP SSC Enable + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Integrated EFP support + =3D 0, Disable + =3D 1, Enable + Bit 1 =3D Integrated TV support. (This field is obsolete now. Kept for V= BIOS only.) + =3D 0, Disable + =3D 1, Enable + Bit 0 =3D Integrated CRT support: Obsolete field + =3D 0, Disable + =3D 1, Enable + **/ + union { + UINT8 Value; + struct { + UINT8 CrtSupported:1; + UINT8 TvSupported:1; + UINT8 EfpSupported:1; + UINT8 DpSscEnable:1; + UINT8 DpSscFrequency:1; + UINT8 DpDongleSscEnable:1; + UINT8 Reserved1:2; + } Bits; + } Int_Displays_Support; +} VBT_GENERAL1_INFO; + +/** + This defines the Structure of PRD Boot Table Entry +**/ +typedef struct { + UINT8 AttachBits; ///< Bitmap representing the displays attached cur= rently. + UINT8 BootDev_PipeA; ///< Bitmap representing the display to boot on Pi= pe A. + UINT8 BootDev_PipeB; ///< Bitmap representing the display to boot on Pi= pe B. +} PRD_TABLE; + +/** + This defines the structure of Block 254 (PRD Boot Table/Child Device Lis= t) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID (254) + UINT16 BlockSize; ///< Defines the size of Block 254 + + PRD_TABLE PRDTable[16]; ///< Defines the Child devic= e list for enumerating child handles. + UINT16 PRD_Boot_Table_Number_Of_Entries; ///< Number of entries in ch= ild device list. +} PRD_BOOT_TABLE; + +/** + This defines the Structure for a CHILD_STRUCT (used for all the displays= ). +**/ +typedef struct { + UINT16 DeviceHandle; ///< Unique ID indicating the group of dis= play device (LFP/EFP1/EFP2/EFP3/EFP4). + UINT16 DeviceClass; ///< Indicates the class of display device= . + UINT8 I2CSpeed; ///< Defines the I2C speed to be used for = I2C transaction. + /** + Defines the DP on board redriver configuration. + BIT[7] : Reserved + BIT[6] : Is On Board DP Redriver Present + 0 : No + 1 : Yes + BIT[5:3] : On Board Redriver VSwing Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + BIT[2:0] : On Board Redriver PreEmph Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + **/ + union{ + UINT8 Value; + struct { + UINT8 OnBoardPreEmphLevel:3; + UINT8 OnBoardVSwingLevel:3; + UINT8 OnBoardRedriverPresent:1; + UINT8 Reserved:1; + } Bits; + } DpOnBoardRedriver; + + /** + Defines the DP on dock redriver configuration. + BIT[7] : Reserved + BIT[6] : Is On Dock DP Redriver Present + 0 : No + 1 : Yes + BIT[5:3] : On Dock Redriver VSwing Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + BIT[2:0] : On Dock Redriver PreEmph Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + **/ + union { + UINT8 Value; + struct { + UINT8 OnDockPreEmphLevel:3; + UINT8 OnDockVSwingLevel:3; + UINT8 OnDockRedriverPresent:1; + UINT8 Reserved:1; + } Bits; + } DpOnDockRedriver; + + /** + + Defines the HDMI level shifter configuration. + BIT[7:5] : Hdmi Maximum data rate + BIT[4:0] : Hdmi Level shifter value + + **/ + union{ + UINT8 Value; + struct { + UINT8 HdmiLevelShifterValue:5; + UINT8 HdmiMaxDataRateBits:3; + } Bits; + } HdmiLevelShifterConfig; + + UINT16 EFPDTDBufferPointer; ///< Pointer to the DTD timing to be used = in case of edidless EFP. + + /** + Defines the first set of flags. + BIT[7-4] : Reserved + BIT[3] : Dual pipe ganged display support + 0 : Display uses a single pipe/port + 1 : Display uses two distinct pipes/ports. + BIT[2] : Compression Method Select + 0 : Compression using picture parameter set (PPS) + 1 : Compression using Capability parameter set (CPS) + BIT[1] : Compression enable/disable for this display. + 0 : Disabled + 1 : Enabled + BIT[0] : EDID less EFP Enable + 0 : Enable support for EDID less EFP. + 1 : Disable support for EDID less EFP. + **/ + union { + UINT8 Value; + struct { + UINT8 EdidlessEfpEnable:1; + UINT8 CompressionEnable:1; + UINT8 CompressionMethod:1; + UINT8 IsDualPortEnabled:1; + UINT8 Reserved:4; + } Bits; + } Flags0; + + /** + Defines the compression index field for the display. + BITS[7-4] : Reserved + BITS[3-0] : Compression Structure index in the block 55. + 0x0 : Index 0 in block 55 + 0x1 : Index 1 in block 55 + 0xF : Not Applicable. + Others : Reserved + **/ + union { + UINT8 Value; + struct { + UINT8 IndexInBlock55:4; + UINT8 Reserved:4; + } Bits; + } CompressionStructureIndex; + + UINT8 SlaveDdiPort; ///< The DVO port number of slave DDI to b= e used in case Flags0[3] =3D 1. + + UINT8 Reserved_1; ///< Reserved and might be used in other p= latforms. + UINT16 AddInOffset; ///< Obsolete field. + UINT8 DVOPort; ///< Specifies the port number of the disp= lay device represented in the device class. + UINT8 I2CBus; ///< Specifies the GMBUS or I2C pin pair f= or add in card. + UINT8 SlaveAddr; ///< Specifies the I2C address of the add = in card. + UINT8 DDCBus; ///< Specifies the GMBUS pin pair for EDID= read. + UINT16 TimingInfoPtr; ///< Pointer to the buffer where VBIOS sto= res the EDID of device. + UINT8 DVOCfg; ///< Obsolete field. + + /** + Flags 1\n + Bits 7:5 : Reserved + Bit 4 : HPD Sense Invert + 0 : Invert not required (default) + 1 : Invert required + Bit 3 : IBoost feature enable/disable. + 0 : IBoost feature is disabled. + 1 : IBoost feature is enabled. + Bit 2 : Hdmi 2.0 Motherboard Downsuppotred options + 0 : Motherboard Down chip not supported + 1 : Motherboard Down Chip Supported on the Board + Bit 1 : Lane Reversal feature. + 0 : Disable + 1 : Enable + Bit 0 : DP/HDMI routed to dock. + 0 : Disable + 1 : Enable + **/ + union { + UINT8 Value; + struct { + UINT8 DockablePort:1; + UINT8 EnableLaneReversal:1; + UINT8 OnBoardLsPconDonglePresent:1; + UINT8 IBoostEnable:1; + UINT8 IsHpdInverted:1; + UINT8 Reserved:3; + } Bits; + } Flags_1; + + UINT8 Compatibility; ///< Compatibility is used in VBIOS only. = It was used before device class was defined. + UINT8 AUX_Channel; ///< Specifies the aux channel to be used = for display port devices. + UINT8 Dongle_Detect; ///< Indicates whether dongle detect is en= abled or not. + UINT8 Capabilities; ///< Bits 1-0 indicate pipe capabilities w= hether display can be used on one pipe or both the pipes. + UINT8 DVOWiring; ///< Obsolete field. + UINT8 MipiBridgeType; ///< MIPI bridge type + UINT16 DeviceClassExtension; ///< Obsolete. + UINT8 DVOFunction; ///< Obsolete. + + /** + Flags 2 + Bits 7:4 : DP Port trace length from silicon to output port on the boar= d + 0 : Default RVP length + 1 : Short trace length + 2 : Long trace length + Bits 3:2 : Reserved + Bit 1 : Indicates whether this port is Thunderbolt port or not. + 0 : No + 1 : Yes + Bit 0 : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP displ= ay + 0 : Disable + 1 : Enable + **/ + union { + UINT8 Value; + struct { + UINT8 UsbTypeCDongleEnabled:1; ///< Indicates whether this port i= s USB type C. + UINT8 IsThunderboltPort:1; ///< Indicates whether this port i= s Thunderbolt. (ICL+) + UINT8 Reserved:2; ///< Reserved for future use. + UINT8 DpPortTraceLength:4; ///< Dp port trace length from sil= icon to port. + } Bits; + } Flags_2; + UINT8 DP2XGpioIndex; ///< GPIO index number for the USB type C. + UINT16 DP2XGpioNumber; ///< GPIO number for USB type C. + + /** + IBoost magnitude field. + Bits 7:4 : DP Boost magnitude + 0 : 1 + 1 : 3 + 2 : 7 + Others : Reserved for WHL. + Bits 3:0 : HDMI Boost magnitude + 0 : 1 + 1 : 3 + 2 : 7 + Others : Reserved. + **/ + union { + UINT8 Value; + struct { + UINT8 DpEdpBoostMagnitude:4; + UINT8 HdmiBoostMagnitude:4; + } Bits; + } BoostMagnitude; +} CHILD_STRUCT; + +/** + This structure defines Block 2 (General Bytes Definitions) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 2. + UINT16 BlockSize; ///< Defines the size of VBT General Inf= o 2 Block. + + UINT8 bmp_CRT_DDC_GMBUS_Pin; ///< Obsolete field: Selects the C= RT DDC GMBUS pin pair. + UINT8 bmp_DPMS_Bits; ///< BMP DPMS Bit Definitions. + UINT16 bmp_Boot_Dev_Bits; ///< BMP Boot Device Bit Definitio= ns. + UINT8 SizeChild_Struct; ///< Size of the ChildStruc struct= ure. + + CHILD_STRUCT Child_Struct[ChildStruct_MAX]; ///< This array defines al= l the supported child structures. +} VBT_GENERAL2_INFO; + +/** + This defines the structure of Block 3 (Original Display Toggle List) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 3 + UINT16 BlockSize; ///< Defines the size of Original Displa= y Toggle List Block + UINT8 bmp_Display_Detect; ///< Display must be attached or not +} BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST; + +/** + This defines structure of a pointer table. +**/ +typedef struct { + UINT16 Offset; ///< Defines the offset of the table from start of= BIOS Data block. + UINT16 Size; ///< Defines the size of an entry of the table. +} BMP_TABLE_PTR; + +/** + This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers). +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 252. + UINT16 BlockSize; ///< Defines the size of SBIOS Hooks b= lock. + UINT8 SbiosHooks[18]; ///< This array defines a series of SB= IOS hooks. Each entry represents one hook. + BMP_TABLE_PTR BmpTablePtr[26]; ///< This array defines pointers to al= l the important tables in the VBT. +} BLOCK252_SBIOS_Hook; + +/** + This defines the structure of MMIO boot table entry +**/ +typedef struct { + UINT32 Register; ///< Defines the MMIO offset of the register. + UINT32 Value; ///< Defines the default value of the register. +} MMIO_BOOT_TABLE; + +/** + This structure defines Block 6 (MMIO Register Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 6 + UINT16 BlockSize; ///< Defines the size of MMIO Regi= ster Table block. + UINT16 RegTableId; ///< Defines the ID for MMIO regis= ter table (0xFFFC). + UINT8 AccessFlag; ///< Defines the flag for data acc= ess size (02 for 4 byte read/write). + MMIO_BOOT_TABLE MMIOBootTable[14]; ///< Array containing the MMIO reg= ister table. + UINT16 TableEnd; ///< Special value describing End = of table (0xFFFF). +} BLOCK06_MMIO_REG_TABLE; + +/** + This structure defines Block 7 (IO SW Flag Register Table) +**/ +typedef struct { + UINT8 BlockId; ///< Defines Block ID (7). + UINT16 BlockSize; ///< Defines the size of IO SW Flag register t= able block. + UINT16 RegTableId; ///< Defines the ID for IO SW Flag register ta= ble (0xFFFE). + UINT8 GRIndexRegLsb; ///< Defines the read/write size. Value is 0xC= E meaning 1 byte without mask. + UINT8 IOSWFlagReg; ///< Defines the offset for the IO SW Flag reg= ister. + UINT8 Value; ///< Defines the data/value for the register. + UINT16 TableEnd; ///< Special value describing the end of table= (0xFFFF). +} BLOCK07_IOSWFLAG_REG_TABLE; + +/** + This structure defines the entry of SWF table. +**/ +typedef struct { + UINT32 Register; ///< Defines the MMIO offset of the SWF register. + UINT32 Value; ///< Defines the default value for the SWF register. +} SWF_TABLE; + +/** + This defines the structure of Block 8 (MMIO SW Flag Block). +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 8. + UINT16 BlockSize; ///< Defines the size of MMIO SWF register table= block. + UINT16 RegTableId; ///< Defines the ID for MMIO SWF register table = (0xFFFC). + UINT8 AccessFlag; ///< Defines the data access size. Value is 0x02= meaning 4 bytes read/write. + SWF_TABLE SWFTable[7]; ///< Array containing the MMIO SWF register tabl= e. + UINT16 TableEnd; ///< Special value describing end of table (0xFF= FF). +} BLOCK08_MMIOSWFLAG_REG_TABLE; + +/** + This structure defines the PSR feature table entry. +**/ +typedef struct { + UINT8 SRD_Enables; ///< Defines PSR features such as full link = enable/disable and whether aux is required to wake up. + UINT8 SRD_WaitTimes; ///< Defines lines to wait before link stand= by and idle frames to wait before SRD enable. + UINT16 SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of 100. + UINT16 SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples of 10= 0 +} PSR_FEATURE_TABLE; + +/** + This defines the structure of Block 9 (PSR Features Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the block ID : 9 + UINT16 BlockSize; ///< Defines the size of PSR Fea= ture block. + PSR_FEATURE_TABLE PSRFeatureTable[16]; ///< Array containing the PSR Fe= ature table. +} BLOCK09_PSR_FEATURE; + +/** + This structure defines an entry of Mode Removal table. +**/ +typedef struct { + UINT16 XRes; ///< X resolution of the mode. + UINT16 YRes; ///< Y resolution of the mode. + UINT8 Bpp; ///< Bits per pixel of the mode. + UINT16 RRate; ///< Refresh rate of the mode. + UINT8 RFlags; ///< Flags specifying display type and functional = area where the mode is to be removed. + UINT16 PanelFlags; ///< Applicable to LFP only. Indicates which LFP p= anels the mode is to be removed. +} MODE_REMOVAL_TABLE_ENTRY; + +/** + This defines the structure of Block 10 (Mode Removal Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block I= D : 10. + UINT16 BlockSize; ///< Defines the size of= Mode Removal table block. + UINT8 EntrySize; ///< Defines the size of= one entry of mode removal table. + MODE_REMOVAL_TABLE_ENTRY ModeRemovalTable[20]; ///< Array containing th= e mode removal table. + UINT16 Terminator; ///< Special value indic= ating end of mode removal table (0xFFFF). +} BLOCK10_MODE_REMOVAL_TABLE; + +/** + This defines the structure of Block 12 (Driver Features Data Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 12 + UINT16 BlockSize; ///< Defines the size of Driver featur= es block. + + /** + This field defines the various driver related bits:\n + Bit 7 =3D Use 00000110h ID for Primary LFP + =3D 0, No + =3D 1, Yes + Bit 6 =3D Enable/Disable Sprite in Clone Mode + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Driver INT 15h hook + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Dual View Zoom + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D Hot Plug DVO + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Allow display switching when in Full Screen DOS. + =3D 0, Block Display Switching + =3D 1, Allow Display Switching + Bit 1 =3D Block display switching when DVD active + =3D 0, No Block Display Switching + =3D 1, Block Display Switching + Bit 0 =3D Boot device algorithm + =3D 0, OS Default + =3D 1, Driver Default + **/ + UINT8 bmp_Driver_Bits; + UINT16 bmp_Driver_Boot_Mode_X; ///< X resolution of driver boot mode. + UINT16 bmp_Driver_Boot_Mode_Y; ///< Y resolution of driver boot mode. + UINT8 bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot mod= e. + UINT8 bmp_Driver_Boot_Mode_RR; ///< Refresh rate of driver boot mode. + + /** + This field defines the extended driver bits 1.\n + Bits [15:14] =3D Integrated HDMI configuration + =3D 00b, No Integrated HDMI + =3D 01b, Port-B Only + =3D 10b, Port-C Only + =3D 11b, Both Port-B and Port-C + Bits 13 =3D TV Hotplug + Bits [12:11] =3D LFP configuration + =3D 00b, No LVDS + =3D 01b, Integrated LVDS + =3D 10b, SDVO LVDS + =3D 11b, eDP + Bit 10 =3D Obsolete field: CRT hotplug + =3D 0, Disabled + =3D 1, Enabled (Default) + Bit 9 =3D SDVO device power down + =3D 0, Disabled (Default) + =3D 1, Enabled + Bit 8 =3D Preserve Aspect Ratio + =3D 0, Disabled (Default) + =3D 1, Enabled + Bit 7 =3D Display "Maintain Aspect Scaling" via CUI + =3D 0, No + =3D 1, Yes (Default) + Bit 6 =3D Sprite Display Assignment when Overlay is Active in Clone Mode= : + =3D 0, Secondary + =3D 1, Primary + Bit 5 =3D Default Power Scheme user interface + =3D 0, CUI + =3D 1, 3rd Party Application + Bit 4 =3D NT 4.0 Dual Display Clone Support + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D Default Render Clock Frequency + =3D 0, High Frequency + =3D 1, Low Frequency + Bit 2 =3D Dual-Frequency Graphics Technology + =3D 0, No + =3D 1, Yes + Bit 1 =3D Selective Mode Pruning + =3D 0, No + =3D 1, Yes + Bit 0 =3D Enable LFP as primary + =3D 0, Disable + =3D 1, Enable +**/ + UINT16 bmp_Ext_Driver_Bits; + + /** + This defines the driver flags related to CUI Hot key.\n + Bits [7:3] - Reserved + Bit 2 =3D Display Subsystem Enable/Disable + =3D 0, Enable (default Value) + =3D 1, Disable + Bit 1 =3D Embedded Platform + =3D 0, False + =3D 1, True + Bit 0 =3D Define CUI HotK Displays Statically + =3D 0, No + =3D 1, Yes + **/ + UINT8 bmp_Display_Detect_CUIHotK; + + UINT16 bmp_Legacy_CRT_Max_X; ///< Obsolete field: Defines the l= egacy CRT X resolution for driver boot mode. + UINT16 bmp_Legacy_CRT_Max_Y; ///< Obsolete field: Defines the l= egacy CRT Y resolution for driver boot mode. + UINT8 bmp_Legacy_CRT_Max_RR; ///< Obsolete field: Defines the l= egacy CRT refresh rate for driver boot mode. + + /** + This field defines the extended driver bits 2.\n + Bits [7:1] - Reserved + Bit 0 =3D Enable Internal Source Termination for HDMI + =3D 0, External Termination + =3D 1, Internal Termination + **/ + UINT8 bmp_Ext2_Driver_Bits; + + UINT8 bmp_VBT_Customization_Version; ///< Defines the customized VBT = version number. + + /** + This field defines all the driver feature flags.\n + Bit 15 =3D PC Features Field's Validity + =3D 0, Invalid + =3D 1, Valid + Bit 14 =3D Hpd_wake - HPD events are routed to display driver when syste= m is in S0ix/DC9 + =3D 0, Disable + =3D 1, Enable + Bit 13 =3D Assertive Display Technology (ADT) + =3D 0, Disable + =3D 1, Enable + Bit 12 =3D Dynamic Media Refresh Rate Switching (DMRRS) + =3D 0, Disable + =3D 1, Enable + Bit 11 =3D Dynamic Frames Per Second (DFPS) + =3D 0, Disable + =3D 1, Enable + Bit 10 =3D Intermediate Pixel Storage (IPS) + =3D 0, Disable + =3D 1, Enable + Bit 9 =3D Panel Self Refresh (PSR) + =3D 0, Disable + =3D 1, Enable + Bit 8 =3D Intel Turbo Boost Technology + =3D 0, Disable + =3D 1, Enable + Bit 7 =3D Graphics Power Modulation Technology (GPMT) + =3D 0, Disable + =3D 1, Enable + Bit 6 =3D Graphics Render Standby (RS) + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Intel Display Refresh Rate Switching (DRRS) + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Intel Automatic Display Brightness (ADB) + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D DxgkDDI Backlight Control (DxgkDdiBLC) + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Intel Display Power Saving Technology (DPST) + =3D 0, Disable + =3D 1, Enable + Bit 1 =3D Intel Smart 2D Display Technology (S2DDT) + =3D 0, Disable + =3D 1, Enable + Bit 0 =3D Intel Rapid Memory Power Management (RMPM) + =3D 0, Disable + =3D 1, Enable + **/ + UINT16 bmp_Driver_Feature_Flags; +} BLOCK12_DRIVER_FEATURES; + +/** + This defines the structure of Block 13 (Driver Persistence Options) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 13 + UINT16 BlockSize; ///< Defines the size of Driver Persiste= nce options block. + + /** + Defines the various persistence options.\n + Bits [15:10] - Reserved + Bit 9 =3D Docking Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 8 =3D DVO Hot Plug Persistence on Mode + Bit 7 =3D EDID Persistence on Mode + Bit 6 =3D Hot Key Persistence on Mode + =3D 0, No + =3D 1, Yes + Bit 5 =3D Hot Key Persistence on RestorePipe + =3D 0, No + =3D 1, Yes + Bit 4 =3D Hot Key Persistence on RefreshRate + =3D 0, No + =3D 1, Yes + Bit 3 =3D Hot Key Persistence on MDS/Twin + =3D 0, No + =3D 1, Yes + Bit 2 =3D Power Management Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 1 =3D Lid Switch Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 0 =3D Hot Key Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + **/ + UINT16 PersistenceAlgorithm; + + UINT8 PersistMaxconfig; ///< Maximum mode persistence configurat= ions (10-200) +} BLOCK13_DRIVER_PERSISTENCE; + +/** + This defines the structure of Block 17 (SV Bits) +**/ +typedef struct { + UINT8 BlockId; ///< Defnies the unique Block ID : 17 + UINT16 BlockSize; ///< Defines the size of SV Bits block. + + /** + Bits [7:4] =3D Reserved + Bit3 =3D Allow VBlank/VblankScanline timeout hang + =3D 0, Disable + =3D 1, Enable + Bit2 =3D Special GMBus support + =3D 0, Disable + =3D 1, Enable + Bit1 =3D Skip program pipe timings when set VGA modes + =3D 0, Setmode skip DVO Update + =3D 1, Setmode updates DVO + Bit0 =3D Disable VGA fast arbiter + =3D 0, Enabled + =3D 1, Disabled + **/ + UINT8 SvBits1; + UINT8 SvBits2; ///< Reserved for future use. + UINT8 SvBits3; ///< Reserved for future use. + UINT8 SvBits4; ///< Reserved for future use. + UINT8 SvBits5; ///< Reserved for future use. + UINT8 SvBits6; ///< Reserved for future use. + UINT8 SvBits7; ///< Reserved for future use. + UINT8 SvBits8; ///< Reserved for future use. +} BLOCK17_SV_BITS; + +/** + This defines the structure of Block 18 (Driver Rotation) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 1= 8 + UINT16 BlockSize; ///< Defines the size of Driver Rota= tion block. + UINT8 RotationFeatureSupport; ///< Rotation feature support field = used by driver. + UINT8 Reserved1; ///< Reserved for future use. + UINT16 Reserved2; ///< Reserved for future use. + UINT32 Reserved3; ///< Reserved for future use. + UINT32 Reserved4; ///< Reserved for future use. +} BLOCK18_DRIVER_ROTATION; + +/** + This structure defines an entry of OEM mode table. +**/ +typedef struct { + /** + Mode Flags: + Bits[7:3] =3D Reserved + Bit 2 =3D Enable/disable this OEM mode in GOP driver. + Bit 1 =3D Enable/disable this mode in Driver + Bit 0 =3D Enable/disable this mode in VBIOS + **/ + UINT8 ModeFlags; + + /** + Display Device Flags: + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D Rsvd + Bit 0 =3D Rsvd + **/ + UINT8 DisplayFlags; + UINT16 XRes; ///< Defines the X resolution of the mode. + UINT16 YRes; ///< Defines the Y resolution of the mode. + + /** + Defines the bits per pixel of the mode. + Bit 7:3 =3D Reserved + Bit 2 =3D 32 BPP + Bit 1 =3D 16 BPP + Bit 0 =3D 8 BPP + **/ + UINT8 Bpp; + UINT8 RRate; ///< Defines the refresh rate of the mode. + DTD_STRUCTURE Dtd; ///< Defines the 18 byte timing config for the mod= e. +} OEM_MODE_ENTRY; + +/** + This defines the structure of Block 20 (OEM Mode Customization Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID : 20 + UINT16 BlockSize; ///< Defines the size of OEM customiza= tion block. + UINT8 NumOfEntry; ///< Defines the number of entries in = OEM Mode table. + UINT8 EntrySize; ///< Defines the size of one entry of = OEM Mode table. + OEM_MODE_ENTRY OemModeTable[6]; ///< Array defining the OEM mode table= . +} BLOCK20_OEM_CUSTOMIZATION; + +/** + This defines the structure of Block 26 (TV options) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 26 + UINT16 BlockSize; ///< Defines the size of TV Options bl= ock. + + /** + Defines the TV options: + Bit 15 =3D D-Conector Support + =3D 0, Disable + =3D 1, Enable + Bit 14 =3D Add 1776x1000 when 1080i is selected and add 1184x666 when = 720p is selected + =3D 0, Disable + =3D 1, Enable + Bit 13:12 Underscan/overscan for HDTV via DVI + =3D 00b, Enable Underscan and Overscan modes (Default) + =3D 01b, Enable only overscan modes + =3D 10b, Enable only underscan modes + Bits 11:2 =3D Reserved + Bit 1:0 =3D Underscan/overscan for HDTV via Component (YPrPb) + =3D 00b, Enable Underscan and Overscan modes (Default) + =3D 01b, Enable only overscan modes + =3D 10b, Enable only underscan modes + **/ + UINT16 bmp_TV_Options_1; +} BLOCK26_TV_OPTIONS; + +/** + This structure defines the eDP panel power sequencing parameters. +**/ +typedef struct { + UINT16 T3; ///< Panel Power-Up Delay. + UINT16 T8; ///< Panel Power-On to backlight Enable Delay. + UINT16 T9; ///< Backlight-Off to Power-Down Delay. + UINT16 T10; ///< Power-Down Delay. + UINT16 T12; ///< Power Cycle Delay. +} EDP_PWR_SEQ; + +/** + This structure defines the PWM<-->Backlight delays for a single eDP pane= l. +**/ +typedef struct { + UINT16 PwmOnToBacklightEnableDelay; ///< PWM on to backight enable= delay. + UINT16 BacklightDisableToPwmOffDelay; ///< Backlight disable to PWM = off delay. +} EDP_PWM_BACKLIGHT_DELAYS; + +/** + This defines FLT parameters for a single eDP panel. + Bits[15:12] : VSwing level + 0 : 0.4V (default) + 1 : 0.6V + 2 : 0.8V + 3 : 1.2V + Others : Reserved + Bits[11:8] : Pre-emphasis level + 0 : no pre-emphasis (default) + 1 : 3.5dB + 2 : 6dB + 3 : 9.5dB + Others : Reserved + Bits[7:4] : Lane count (port width) + 0 : x1 mode (default) + 1 : x2 mode + 2 : Reserved + 3 : x4 mode + Others : Reserved + Bits[3:0] : data rate + 0 : 1.62 Gbps + 1 : 2.7 Gbps + 2 : 5.4 Gbps + Others : Reserved +**/ +typedef union { + UINT16 Value; + struct { + UINT16 DataRate:4; + UINT16 LaneCount:4; + UINT16 PreEmphasisLevel:4; + UINT16 VSwingLevel:4; + } Bits; +} EDP_FAST_LINK_TRAINING_PARAMS; + +/** + This defines Full link training parameters for a single eDP panel. + Bits[7:4] : VSwing level + 0 : 0.4V (default) + 1 : 0.6V + 2 : 0.8V + 3 : 1.2V + Others : Reserved + Bits[3:0] : Pre-emphasis level + 0 : no pre-emphasis (default) + 1 : 3.5dB + 2 : 6dB + 3 : 9.5dB + Others : Reserved +**/ +typedef union { + UINT8 Value; + struct { + UINT8 PreEmphasisLevel:4; + UINT8 VSwingLevel:4; + } Bits; +} EDP_FULL_LINK_TRAINING_PARAMS; + +/** + This defines the structure of Apical Parameters for a single eDP panel. +**/ +typedef struct { + UINT32 PanelOui; ///< Apical IP specific field for Pane= l OUI + UINT32 DPCDBaseAddress; ///< Apical IP specific field for DPCD= Base address + UINT32 DPCDIrdidixControl0; ///< Apical IP specific field for DPCD= Idridix Control 0 + UINT32 DPCDOptionSelect; ///< Apical IP specific field for DPCD= option select + UINT32 DPCDBacklight; ///< Apical IP specific field for DPCD= backlight + UINT32 AmbientLight; ///< Apical IP specific field for Ambi= ent light + UINT32 BacklightScale; ///< Apical IP specific field for back= light scale +} EDP_APICAL_PARAMS; + +/** + This defines the structure of Block 27 (eDP Display Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 27 + UINT16 BlockSize; ///< Defines the size of eDP display VBT= block. + + EDP_PWR_SEQ eDP_PWR_SEQ[16]; ///< Array defining the panel power sequ= encing for all 16 eDP panels. + + /** + Defines the panel color depth in bits per pixel. 2 Bits for each Panel. + Bits[1:0] Panel color depth for Panel #1 + =3D 00, 18bpp + =3D 01, 24bpp + =3D 10, 30bpp + =3D 11, 36bpp + **/ + UINT32 eDP_Panel_Color_Depth; + + /** + Array containing the FLT parameters of 16 eDP panels. + **/ + EDP_FAST_LINK_TRAINING_PARAMS eDP_Fast_Link_Training_Params[16]; + + /** + This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels.= 2 Bits for Each Panel. + Bits[1:0] for Panel #1 + =3D 00, Line 1 + =3D 01, Line 2 + =3D 10, Line 3 + =3D 11, Line 4 + **/ + UINT32 eDP_sDRRS_MSA_Delay; + + /** + Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for = Each Panel. + Bits[0] for Panel #1 + =3D 0, S3D disabled for this panel + =3D 1, S3D enabled for this panel + **/ + UINT16 eDP_S3D_Feature; + + /** + Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for = each panel. + Bits[0] =3D Panel #1 + =3D 0, T3 optimization disabled for this panel + =3D 1, T3 optimization enabled for this panel + **/ + UINT16 eDP_T3_Optmization; + + /** + Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Ea= ch Panel + Bits[3:0] =3D Panel #1 + =3D 0, Use table 1 for this panel. + =3D 1, Use table 2 for this panel. + **/ + UINT64 VswingPreEmphasisTableNum; + + /** + Defines the Edp fast link training support on all 16 panels. 1 Bit for E= ach Panel + Bits[0] =3D Panel #1 + =3D 0, FastLinkTraining feature is disabled for this panel + =3D 1, FastLinkTraining feature is enabled for this panel + **/ + UINT16 EdpFastLinkTrainingSupportOnPanel; + + /** + Defines whether the Set power state at DPCD 600h is to be done in eDP en= able/disable sequence. + Bits[0] =3D Panel #1 + =3D 0, Set power state at DPCD 600h feature is disabled for this panel + =3D 1, Set power state at DPCD 600h feature is enabled for this panel + **/ + UINT16 SetPowerStateAtDPCD600h; //This is not used currently + + /** + Array defining the PWM <--> Backlight related delays for 16 panels. + **/ + EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16]; + + /** + Defines the Edp full link training support on all 16 panels. 1 Bit for E= ach Panel. + \verbatim + Bits[0] : Panel #1 + 0 : Initial vswing and pre-emphasis levels are not provided for Fu= ll link training + 1 : Initial vswing and pre-emphasis levels are provided for Full l= ink training + Bits 1 to 15 are for panel # 2 to 16. + \endverbatim + **/ + UINT16 InitialFullLinkTrainingParamsProvidedInVbt; + + /** + Array containing the initial Vswing and Pre-emphasis parameters for Fu= ll link training. + **/ + EDP_FULL_LINK_TRAINING_PARAMS eDP_Full_Link_Training_Params[16]; + + /** + Defines the Edp Apical assertive display IP support on all 16 panels. 1 = Bit for Each Panel. + Bit 0 : Panel #1 + 0 : Apical assertive display IP is disabled for this panel. + 1 : Apical assertive display IP is enabled for this panel. + Bits 1 to 15 are for panel # 2 to 16. + **/ + UINT16 IsApicalAssertiveDisplayIpEnable; + + /** + Array containing the Apical parameters for all 16 panels + **/ + EDP_APICAL_PARAMS eDP_Apcial_Params[16]; +} BLOCK27_EDP_FEATURES; + +/** + This defines the structure of Block 28 (Edidless EFP support DTD timings= ) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the uniqu= e Block ID : 28 + UINT16 BlockSize; ///< Defines the size = of Edidless EFP support block. + DTD_STRUCTURE Edidless_EFP_DTD_Struc[4]; ///< Array defining th= e DTD timing for 3 EFP devices. +} BLOCK28_EDIDLESS_EFP; + +/** +This defines the structure of toggle list entry. +**/ +typedef struct { + /** + Defines the display device selection for toggling + Bit 15 =3D EFP4.3 (Reserved for WHL) + Bit 14 =3D EFP3.3 + Bit 13 =3D EFP2.3 + Bit 12 =3D EFP1.3 + Bit 11 =3D EFP4.2 (Reserved for WHL) + Bit 10 =3D EFP3.2 + Bit 9 =3D EFP2.2 + Bit 8 =3D EFP1.2 + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D TV + Bit 0 =3D CRT + **/ + UINT16 DisplayDevice; +} CNL_TOGGLE_LIST_ENTRY; + +/** + This defines the structure of Block 31 (Toggle Lists for Cannonlake) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bl= ock ID : 31 + UINT16 BlockSize; ///< Defines the size of T= oggle List Block. + UINT16 NumOfEntry1; ///< Defines the number of= entries in toggle list 1. + UINT8 EntrySize1; ///< Defines the size of t= oggle list entry present in list 1. + CNL_TOGGLE_LIST_ENTRY ToggleList1Entry[16]; ///< Array defining the to= ggle list 1. + UINT16 NumOfEntry2; ///< Defines the number of= entries in toggle list 2. + UINT8 EntrySize2; ///< Defines the size of t= oggle list entry present in list 2. + CNL_TOGGLE_LIST_ENTRY ToggleList2Entry[8]; ///< Array defining the to= ggle list 2. + UINT16 NumOfEntry3; ///< Defines the number of= entries in toggle list 3. + UINT8 EntrySize3; ///< Defines the size of t= oggle list entry present in list 3. + CNL_TOGGLE_LIST_ENTRY ToggleList3Entry[8]; ///< Array defining the to= ggle list 3. + UINT16 NumOfEntry4; ///< Defines the number of= entries in toggle list 4. + UINT8 EntrySize4; ///< Defines the size of t= oggle list entry present in list 4. + CNL_TOGGLE_LIST_ENTRY ToggleList4Entry[8]; ///< Array defining the to= ggle list 4. +} BLOCK31_TOGGLE_LIST; + +/** + This defines the structure of Display device removal configuration entry= . +**/ +typedef struct { + /** + Defines the display device configuration to be removed. + Bit 15 =3D EFP4.3 (Reserved for WHL) + Bit 14 =3D EFP3.3 + Bit 13 =3D EFP2.3 + Bit 12 =3D EFP1.3 + Bit 11 =3D EFP4.2 (Reserved for WHL) + Bit 10 =3D EFP3.2 + Bit 9 =3D EFP2.2 + Bit 8 =3D EFP1.2 + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D TV + Bit 0 =3D CRT + **/ + UINT16 DisplayDeviceConfiguration; +} CNL_DISPLAY_CONFIGURATION_ENTRY; + +/** + This defines the structure of Block 32 (Display removal configuration Bl= ock) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the uni= que Block ID =3D 32 + UINT16 BlockSize; ///< Defines the siz= e of Display removal configuration block. + UINT8 NumOfEntry; ///< Defines the num= ber of entries in display removal configuraion table. + UINT8 EntrySize; ///< Defines the siz= e of 1 entry in display removal configuration table. + CNL_DISPLAY_CONFIGURATION_ENTRY RemoveDisplayConfiguration[15]; = ///< Array defining the display removal configuration table. +}BLOCK32_DISPLAY_CONFIGURATION_REMOVAL; + +/** + This defines the Local Flat panel basic details such as resolution and t= he various registers. +**/ +typedef struct { + UINT16 XRes; ///< X resolution of the panel. + UINT16 YRes; ///< Y resolution of the panel. + UINT32 LVDSDigDisReg; ///< MMIO offset of LFP digital display = port register. + UINT32 LVDSDigDisVal; ///< Value of LFP digital display port r= egister. + UINT32 OnSeqDelayReg; ///< MMIO offset of Panel power on seque= ncing delay register. + UINT32 OnSeqDelayVal; ///< Value of Panel power on sequencing = delay register. + UINT32 OffSeqDelayReg; ///< MMIO offset of Panel power off sequ= encing delay register. + UINT32 OffSeqDelayVal; ///< Value of Panel power off sequencing= delay register. + UINT32 CycleDelay_RefDivReg; ///< MMIO offset of Panel power cycle de= lay and reference divider register. + UINT32 CycleDelay_RefDivVal; ///< Value of Panel power cycle delay an= d reference divider register. + UINT16 Terminate; ///< Special value 0xFFFF indicating end= of data. +} FP_DATA; + +/** + This defines the structure consisting of all details for a single Local = Flat panel. +**/ +typedef struct { + FP_DATA FP_Data; ///< Instance of ::FP_DATA structure. + DTD_STRUCTURE DTD_Data; ///< Instance of ::DTD_STRUCTURE which conta= ins the DTD timings for the panel. + PID_DATA PID_Data; ///< Instance of ::PID_DATA structure which = contains panel related information used by driver. +} LVDS_FP_TABLE; + +/** + This structure defines all the details regarding Backlight control for L= FP. +**/ +typedef struct { + /** + Defines the backlight features for the panel. + Bits 7:6 =3D GMBus Speed: + =3D 00, 100 KHz + =3D 01, 50 KHz + =3D 10, 400 KHz + =3D 11, 1 MHz + Bits 5:3 =3D Inverter GPIO Pins + =3D 0, None + =3D 1, I2C GPIO pins + =3D 2, Analog CRT DDC pins + =3D 3, DVI/LVDS DDC GPIO pins + =3D 5, sDVO I2C GPIO pins + Bit 2 =3D Inverter Polarity (i2c & PWM) + =3D 0, Normal (0 =3D Minimum brightness) + =3D 1, Inverted (0 =3D Maximum brightness) + Bits 1:0 =3D BLC Inverter Type + =3D 00, None/External + =3D 01, i2c + =3D 10, PWM + =3D 11, Reserved + **/ + UINT8 BLC_Ftr; + + UINT16 PWM_Freq; ///< PWM inverter frequency in KHz + UINT8 Min_Brightness; ///< Minimum brightness in the range 0-255 + UINT8 I2C_Add; ///< I2C Inverter Slave Address + UINT8 I2C_Command; ///< I2C Inverter command code +} BLC; + +/** + This defines the structure of Block 40 (LFP Features) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 40 + UINT16 BlockSize; ///< Defines the size of LFP Features block. + + UINT8 bmp_Panel_type; ///< Defines the panel type of LFP. + UINT8 Skip1; ///< Obsoleted. + + /** + Capabilities byte: + Bit 15:7 =3D SW Workaround bits + Bit 6 =3D Panel EDID support + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Pixel dithering + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Panel Fitting ratio calc. + =3D 0 - Manual + =3D 1 - Automatic + Bit 3 =3D Panel Fitting Graphics mode + =3D 0, Bilinear + =3D 1, Enhanced + Bit 2 =3D Panel Fitting Text mode + =3D 0, Bilinear + =3D 1, Enhanced + Bit 1:0 =3D Panel Fitting Support + =3D 00, No panel fitting + =3D 01, Text panel fitting + =3D 10, GFX panel fitting + =3D 11, Text+GFX panel fitting + **/ + UINT16 bmp_LVDS_Capabilities; + + /** + Defines the channel type of LFP. 2 Bits for each Panel. + Bits [0:1] for Panel #1 + =3D 00, Automatic (algorithm) + =3D 01, Single Channel + =3D 10, Dual Channel + =3D 11, Reserved + **/ + UINT32 INT_LVDS_Panel_Channel_Bits; + + UINT16 Enable_SSC_Bit; ///< LVDS Spread Spectrum Clock + UINT16 SSC_Freq_Bit; ///< LVDS Spread Spectrum Clock Frequenc= y + UINT16 Disable_SSC_DDT_Bit; ///< Disable SSC in Dual Display Twin + + /** + Defines the panel color depth. 1 Bits for each Panel. + Bits[0] for Panel #01 + =3D 0, 18bpp + =3D 1, 24bpp + **/ + UINT16 INT_Panel_Color_Depth; + + /** + Defines the Panel type. 2 Bits for each Panel. + Bits [0:1] for Panel #1 + =3D 00, Static DRRS + =3D 01, D2PO + =3D 10, Seamless + =3D 11, Reserved + **/ + UINT32 DPS_Panel_Type_Bits; + + /** + Defines the type of backlight control for the LFP. 2 bits for each Panel= . + Bits [0:1] for Panel #1 + =3D 00, Default + =3D 01, CCFL backlight + =3D 10, LED backlight + =3D 11, Reserved + **/ + UINT32 BLT_Control_Type_Bits; + /** + Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit f= or Each Panel. + Bits[0] : Panel #1 + 0 : Do not keep LCDVCC on during S0 state. + 1 : Keep LCDVCC on during S0 state. + Bits 1 to 15 are for panel # 2 to 16. + **/ + UINT16 LcdvccOnDuringS0State; +} BLOCK40_LVDS_FEATURES; + +/** + This structure defines the second type of BMP table pointers. + This is used to store pointers to LFP Flat panel data, DTD and PID infor= mation. +**/ +typedef struct { + UINT16 Offset; ///< Offset of the table. + UINT8 Size; ///< Size of the table. +} BMP_TABLE_TYPE2_PTR; + +/** + This structure defines a set of 3 pointers for LFP display. + These pointers point to FP data, DTD and PID information respectively. +**/ +typedef struct { + BMP_TABLE_TYPE2_PTR FpTablePtr; ///< Pointer to FP Data of the LFP p= anel. + BMP_TABLE_TYPE2_PTR DtdTablePtr; ///< Pointer to DTD of the LFP panel= . + BMP_TABLE_TYPE2_PTR PidTablePtr; ///< Pointer to the PID data of the = LFP panel. +} LFP_TABLE_POINTERS; + +/** + This defines the structure of Block 41 (LFP Table Pointers for FPDATA, D= TD and PID) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bl= ock ID:41 + UINT16 BlockSize; ///< Defines the size of L= FP Table Pointer Block. + UINT8 NumOfEntries; ///< Defines the number of= entries in the Table. + LFP_TABLE_POINTERS LfpTablePointers[16]; ///< Array of ::LFP_TABLE_= POINTERS for all 16 panels. + UINT16 LfpPanelNameTableOffset; ///< Offset of LFP panel n= ames table. + UINT8 LfpPanelNameLength; ///< Length of a single LF= P panel's name. +} BLOCK41_LFP_TABLE_POINTERS; + +/** + This defines the structure of Block 42 (Complete LFP Panel Information) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID := 42 + UINT16 BlockSize; ///< Defines the size of Complete = LFP panel information for all 16 panels. + LVDS_FP_TABLE LVDS_FP_Table[16]; ///< Array of ::LVDS_FP_TABLE cont= aining data of 16 panels. + UINT8 LFP_PANEL_NAMES[16][13];///< Array defining the panel name= s for all 16 panels. + + /** + 1 Bit for Each Panel + Bit0 =3D Scaling feature for panel 1. + =3D 0, Scaling feature is disabled for this panel. + =3D 1, Scaling feature is enabled for this panel. + **/ + UINT16 EnableScaling; //This is not used currently + + /** + Array defining DRRS minimum refresh rate. 1 Byte for Each Panel. + **/ + UINT8 Seamless_DRRS_Min_RR[16]; + + /** + Array defining Pixel Overlap Count. 1 Byte for Each Panel. + **/ + UINT8 PixelOverlapCount[16]; +} BLOCK42_LVDS_PANEL_INFO; + +typedef union { + /** + Backlight control parameters.\n + Bits 7:4 : PWM Controller Selection + 0 : Controller 0 + 1 : Controller 1 + 2 : Controller 2 + 3 : Controller 3 + Others : Reserved. + Bits 3:0 : PWM Source Selection + 0 : PMIC PWM + 1 : LPSS PWM + 2 : DISPLAY PWM + 3 : CABC PWM + Others : Reserved. + **/ + UINT8 Value; + struct { + UINT8 PwmSourceSelection:4; + UINT8 PwmControllerSelection:4; + } Bits; +} BKLT_CTRL_PARAMS; + +/** + This defines the structure of Block 43 (LFP Brightness Control) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block = ID : 43 + UINT16 BlockSize; ///< Defines the size of Brigh= tness control block. + + UINT8 SIZE_BLCStruc; ///< Defines the size of singl= e entry in Backlight control table for LFP. + BLC BLC_Struct[16]; ///< Array defining the backli= ght control for 16 LFP panels. + UINT8 Post_Brightness[16]; ///< Array defining the initia= l brightness for all 16 panels. + BKLT_CTRL_PARAMS Brightness_Control[16]; ///< Array defining the bright= ness control method for all 16 panels +} BLOCK43_LVDS_BLC; + +/** + This defines the structure of Block 44 (LFP Power Conservation Features) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID : 44 + UINT16 BlockSize; ///< Defines the size of LFP Power Conservation = Features block. + union { + /** + Bit[7] : ALS Enable/Disable + 0 - Disable + 1 - Enable + Bit[6] : Display LACE support + 0 - Not supported + 1 - Supported + Bit[5] : Default Display LACE enabled status + 0 - Disabled + 1 - Enabled + Bit[4] : Reserved + Bit[3:1] : Power conservation preference level. + 4 is default in a range of 1 to 6. + Bit[0] : Reserved + **/ + UINT8 Value; + struct { + UINT8 Reserved:1; + UINT8 PwrConservation:3; + UINT8 Reserved_1:1; + UINT8 DefalutDisplayLaceEnable:1; + UINT8 DisplayLaceSupport:1; + UINT8 AlsEnable:1; + } Bits; + } LfpFeatureBits; + + UINT16 AlsData[10]; ///< Defines the main ALS data. + + union { + /** + Bit[7:3] : Reserved + Bit[2:0] : Aggressiveness Level Profile. + 000 - Minimum + 001 - Moderate + 010 - High + **/ + UINT8 Value; + struct { + UINT8 AggressionProfileLevel:3; + UINT8 Reserved:5; + } Bits; + } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profil= e +} BLOCK44_ALS; + +/** + This defines the structure of Black Frame Insertion table entry. +**/ +typedef struct { + /** + BFI Features\n + Bit[7-2] : Reserved\n + Bit[1] : Enable Brightness control in CUI\n + Bit[0] : Enable BFI in driver + **/ + UINT8 EnableBits; + UINT8 BrightnessNonBFI; ///< Brightness percentage in non BFI = mode +} BFI; + +/** + This defines the structure of Block 45 (Black Frame insertion Support fo= r LFP) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 4= 5 + UINT16 BlockSize; ///< Defines the size of Black frame= insertion support block. + UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of = black frame data. + BFI BFI_Struct[16]; ///< Array defining the data of blac= k frame insertion for all 16 panels. +} BLOCK45_BFI_SUPPORT; + +/** + This structure defines the chromaticity information for a single LFP pan= el. +**/ +typedef struct { + /** + Defines the chromaticity feature enable bits + Bits 7:2 =3D Reserved + Bit 1 =3D Override EDID values for chromaticity if enabled, Instead = Use VBT values + =3D 0, Disable, Use the EDID values + =3D 1, Enable, Use the values from the VBT + Bit 0 =3D Enable chromaticity feature. EDID values will be used when= this feature is enabled. + =3D 0, Disable + =3D 1, Enable + **/ + UINT8 EnableBits; + + UINT8 Red_Green_1; ///< Red/green chormaticity coordinates at E= DID offset 19h + UINT8 Blue_White_1; ///< Blue/white chromatiity coordinates at E= DID offset 1Ah + UINT8 Red_X1; ///< Red x coordinate at EDID offset 1Bh + UINT8 Red_Y1; ///< Red x coordinate at EDID offset 1Ch + UINT8 Green_X1; ///< Green x coordinate at EDID offset 1Dh + UINT8 Green_Y1; ///< Green x coordinate at EDID offset 1Eh + UINT8 Blue_X1; ///< Blue x coordinate at EDID offset 1Fh + UINT8 Blue_Y1; ///< Blue x coordinate at EDID offset 20h + UINT8 White_X1; ///< White x coordinate at EDID offset 21h + UINT8 White_Y1; ///< White x coordinate at EDID offset 22h +} CHROMATICITY; + +/** + This structure defines the Luminance information for a single LFP panel. +**/ +typedef struct { + /** + Defines the chromaticity feature enable bits + Bits 7:2 : Reserved + Bit 1 : Enable Gamma feature. + : if enabled, use gamma values from this block. + 0 : Disable + 1 : Enable + Bit 0 : Enable Luminance feature. + : if enabled, use values from this block. + 0 : Disable + 1 : Enable + **/ + UINT8 EnableBits; + /** + Luminance info (refer DisplayID 2.0) + 2 byte value, encoded in IEEE 754 half-precision binary floating point= format + **/ + UINT16 MinLuminance; ///< Native minimum luminance + UINT16 MaxFullFrameLuminance; ///< Native maximum luminance (Full = Frame) + UINT16 MaxLuminance; ///< Native Maximum Luminance (1% Re= ctangular Coverage) + /** + Gamma EOTF + Gamma values range from 00h through FFh which will come from VBT. + Value shall define the gamma range, from 1.00 to 3.54. + Field Value =3D (Gamma (value from VBT) + 100) / 100 + + FFh =3D No gamma information shall be provided + **/ + UINT8 Gamma; + +}LUMINANCE_AND_GAMMA; + +/** + This defines the structure of Block 46 (Chromaticity Support) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bloc= k ID : 46 + UINT16 BlockSize; ///< Defines the size of Chr= omaticity Block. + CHROMATICITY Chromaticity_Struct[16]; ///< Defines the chromaticit= y information for all 16 panels. + LUMINANCE_AND_GAMMA Luminance_Gamma_Struct[16]; ///< Defines the lum= ianance information for all 16 panels. +} BLOCK46_CHROMATICITY_SUPPORT; + +/** + This defines the structure of Block 51 (Fixed Mode Set) +**/ +typedef struct{ + UINT8 BlockId; ///< Defines the unique block ID : 51. + UINT16 BlockSize; ///< Defines the size of Fixed mode set feat= ure block. + UINT8 FeatureEnable; ///< Whether the fixed mode set feature is e= nabled/disabled. + UINT32 XRes; ///< X resolution of the fixed mode. + UINT32 YRes; ///< Y resolution of the fixed mode. +} BLOCK51_FIXED_MODE_SET; + +/** + This defines the Complete VBT Structure for generation purpose +**/ +typedef struct { + VBT_HEADER VbtHeader; + VBT_BIOS_DATA_HEADER VbtBdbHeader; + BLOCK254_BMP_Structure Block254BMPStructure; + VBT_GENERAL1_INFO VbtGen1Info; + PRD_BOOT_TABLE PrdBootTable; + VBT_GENERAL2_INFO VbtGen2Info; + BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST Block03OriginalDisplayToggleLi= st; + BLOCK252_SBIOS_Hook Block252SbiosHook; + BLOCK06_MMIO_REG_TABLE Block06MmioRegTable; + BLOCK07_IOSWFLAG_REG_TABLE Block07IoswflagRegTable; + BLOCK08_MMIOSWFLAG_REG_TABLE Block08MmioswflagRegTable; + BLOCK09_PSR_FEATURE Block09PsrFeature; + BLOCK10_MODE_REMOVAL_TABLE Block10ModeRemovalTable; + BLOCK12_DRIVER_FEATURES Block12DriverFeatures; + BLOCK13_DRIVER_PERSISTENCE Block13DriverPersistence; + BLOCK17_SV_BITS Block17SvBits; + BLOCK18_DRIVER_ROTATION Block18DriverRotation; + BLOCK20_OEM_CUSTOMIZATION Block20OemCustomization; + BLOCK26_TV_OPTIONS Block26TVOptions; + BLOCK27_EDP_FEATURES Block27EDPFeatures; + BLOCK28_EDIDLESS_EFP Block28EdidlessEFP; + BLOCK31_TOGGLE_LIST Block31ToggleList; + BLOCK32_DISPLAY_CONFIGURATION_REMOVAL Block32DisplayConfigurationRem= oval; + BLOCK40_LVDS_FEATURES Block40LVDSFeatures; + BLOCK41_LFP_TABLE_POINTERS Block41LfpTablePointers; + BLOCK42_LVDS_PANEL_INFO Block42LvdsPanelInfo; + BLOCK43_LVDS_BLC Block43LVDSBlc; + BLOCK44_ALS Block44Als; + BLOCK46_CHROMATICITY_SUPPORT Block46ChromaticitySupport; + BLOCK51_FIXED_MODE_SET Block51FixedModeSet; +} VBT_TABLE_DATA; + +#pragma pack() + +/** + This function will update the VBT checksum. + + @param[in out] VbtPtr - Pointer to VBT table + + @retval none +**/ +VOID +UpdateVbtChecksum( + VBT_TABLE_DATA *VbtPtr +); + +/** + This function will update the VBT. + + @param[in] VbtPtr - Pointer to VBT Table + + @retval none +**/ +VOID +UpdateGopVbt ( + IN VBT_TABLE_DATA *VbtPtr +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.= h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h new file mode 100644 index 0000000000..5bf2527963 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __TCO_WDT_HOB_H__ +#define __TCO_WDT_HOB_H__ + +#define TCO_WDT_HOB_GUID \ + { \ + 0x3e405418, 0xd8c, 0x4f1a, { 0xb0, 0x55, 0xbe, 0xf9, 0x8, 0x41, 0x46, = 0x8d } \ + } + +#ifndef _PEI_HOB_H_ +#ifndef __HOB__H__ +#ifndef __PI_HOB_H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + // + // Guid specific data goes here + // +} EFI_HOB_GUID_TYPE; +#endif +#endif +#endif + +typedef struct { + EFI_HOB_GUID_TYPE Header; + UINT8 TcoRebootHappened; +} TCO_WDT_HOB; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h b/= Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h new file mode 100644 index 0000000000..671e3c5cde --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h @@ -0,0 +1,68 @@ +/** @file + GPIO definition table for WhiskeylakeURvp + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IO_EXPANDER_H_ +#define _IO_EXPANDER_H_ + +typedef struct { + UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1) + UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23) + UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output) + UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low) + UINT32 GpioInversion : 1; // GPIO Pin Inversion (Enabled/Disabled) + UINT32 Reserved : 23; // Reserved +} IO_EXPANDER_GPIO_CONFIG; + +//WHL PCH LP GPIO Expander Number +#define IO_EXPANDER_0 0 +#define IO_EXPANDER_1 1 + +//WHL PCH LP GPIO Pin Mapping +#define IO_EXPANDER_GPIO_0 0 // P00 +#define IO_EXPANDER_GPIO_1 1 // P01 +#define IO_EXPANDER_GPIO_2 2 // P02 +#define IO_EXPANDER_GPIO_3 3 // P03 +#define IO_EXPANDER_GPIO_4 4 // P04 +#define IO_EXPANDER_GPIO_5 5 // P05 +#define IO_EXPANDER_GPIO_6 6 // P06 +#define IO_EXPANDER_GPIO_7 7 // P07 +#define IO_EXPANDER_GPIO_8 8 // P10 +#define IO_EXPANDER_GPIO_9 9 // P11 +#define IO_EXPANDER_GPIO_10 10 // P12 +#define IO_EXPANDER_GPIO_11 11 // P13 +#define IO_EXPANDER_GPIO_12 12 // P14 +#define IO_EXPANDER_GPIO_13 13 // P15 +#define IO_EXPANDER_GPIO_14 14 // P16 +#define IO_EXPANDER_GPIO_15 15 // P17 +#define IO_EXPANDER_GPIO_16 16 // P20 +#define IO_EXPANDER_GPIO_17 17 // P21 +#define IO_EXPANDER_GPIO_18 18 // P22 +#define IO_EXPANDER_GPIO_19 19 // P23 +#define IO_EXPANDER_GPIO_20 20 // P24 +#define IO_EXPANDER_GPIO_21 21 // P25 +#define IO_EXPANDER_GPIO_22 22 // P26 +#define IO_EXPANDER_GPIO_23 23 // P27 + +//WHL PCH LP GPIO Expander GPIO Direction +#define IO_EXPANDER_GPIO_OUTPUT 0 +#define IO_EXPANDER_GPIO_INPUT 1 + +//WHL PCH LP GPIO Expaner GPIO Output Level +#define IO_EXPANDER_GPO_LEVEL_LOW 0 +#define IO_EXPANDER_GPO_LEVEL_HIGH 1 + +//WHL PCH LP GPIO Expaner GPIO Inversion Status +#define IO_EXPANDER_GPI_INV_DISABLED 0 +#define IO_EXPANDER_GPI_INV_ENABLED 1 +#define IO_EXPANDER_GPIO_RESERVED 0x00 + +//GPIO Table Terminator +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuP= olicyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/D= xeCpuPolicyUpdateLib.h new file mode 100644 index 0000000000..5d5fba47ad --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuPolicyUp= dateLib.h @@ -0,0 +1,75 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_ +#define _DXE_CPU_POLICY_UPDATE_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +/** + + This function prints the CPU DXE phase policy. + + @param[in] DxeCpuPolicy - CPU DXE Policy protocol + +**/ +VOID +CpuDxePrintPolicyProtocol ( + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +/** + +Routine Description: + + This function updates Dxe Cpu Policy Protocol + +Arguments: + + @param[in] DxeCpuPolicy The Cpu Policy protocol instance + +Returns: + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by th= is driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to = initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnor= mally. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSiCpuPolicy ( + IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +/** + + CpuInstallPolicyProtocol installs CPU Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol= instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +CpuInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePo= licyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Dx= eMePolicyUpdateLib.h new file mode 100644 index 0000000000..9b960159ba --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePolicyUpd= ateLib.h @@ -0,0 +1,27 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_ME_POLICY_UPDATE_LIB_H_ +#define _DXE_ME_POLICY_UPDATE_LIB_H_ + +/** + Update the ME Policy Library + + @param[in] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this= driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in= itialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnorma= lly. + +**/ +EFI_STATUS +UpdateDxeMePolicy ( + IN OUT ME_POLICY_PROTOCOL *DxeMePolicy + ); + +#endif // _DXE_ME_POLICY_UPDATE_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchP= olicyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/D= xePchPolicyUpdateLib.h new file mode 100644 index 0000000000..84db68e65c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchPolicyUp= dateLib.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_ +#define _DXE_PCH_POLICY_UPDATE_LIB_H_ + +/** + Get data for platform policy from setup options. + + @param[in] PchPolicy The pointer to get PCH Policy protoco= l instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxePchPolicy ( + IN OUT PCH_POLICY_PROTOCOL *PchPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePoli= cyBoardConfigLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library= /DxePolicyBoardConfigLib.h new file mode 100644 index 0000000000..3bb941235c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePolicyBoard= ConfigLib.h @@ -0,0 +1,30 @@ +/** @file + Header file for the DxePolicyBoardConfig Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_ +#define _DXE_POLICY_BOARD_CONFIG_LIB_H_ + +#include +#include + +/** + This function performs DXE SA Policy update by board configuration. + + @param[in, out] DxeSaPolicy DXE SA Policy + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicyBoardConfig ( + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPo= licyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Dx= eSaPolicyUpdateLib.h new file mode 100644 index 0000000000..4279c0c6f1 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPolicyUpd= ateLib.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_UPDATE_LIB_H_ +#define _DXE_SA_POLICY_UPDATE_LIB_H_ + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol = instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPoli= cyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPol= icyInitLib.h new file mode 100644 index 0000000000..4709179ac6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPolicyInitL= ib.h @@ -0,0 +1,29 @@ +/** @file + Function prototype of FspPolicyInitLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FSP_POLICY_INIT_LIB_H_ +#define _FSP_POLICY_INIT_LIB_H_ + +#include +#include +#include + +VOID +EFIAPI +FspPolicyInitPreMem ( + IN FSPM_UPD *FspmUpdDataPtr + ); + +VOID +EFIAPI +FspPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +#endif // _FSP_POLICY_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioChe= ckConflictLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Gp= ioCheckConflictLib.h new file mode 100644 index 0000000000..ba73cad63b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioCheckConfl= ictLib.h @@ -0,0 +1,46 @@ +/** @file + Header file for check Gpio PadMode conflict. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_CHECK_CONFLICT_LIB_H_ +#define _GPIO_CHECK_CONFLICT_LIB_H_ + +#include +#include +#include + +extern EFI_GUID gGpioCheckConflictHobGuid; + +typedef struct { + GPIO_PAD GpioPad; + UINT32 GpioPadMode:5; + UINT32 Reserved:27; +} GPIO_PAD_MODE_INFO; + +/** + Check Gpio PadMode conflict and report it. +**/ +VOID +GpioCheckConflict ( + VOID + ); + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ); + +#endif // _GPIO_CHECK_CONFLICT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExp= anderLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExp= anderLib.h new file mode 100644 index 0000000000..40ea4abc3d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExpanderLi= b.h @@ -0,0 +1,123 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_EXPANDER_LIB_H_ +#define _GPIO_EXPANDER_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +/** + Set the Direction value for the given Expander Gpio pin. + + This function is to Set the direction value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none +**/ +VOID +GpioExpSetDirection ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Direction + ); +/** + Set the input value for the given Expander Gpio pin. + + This function is to get the input value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + +**/ +VOID +GpioExpSetPolarity ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Polarity + ); +/** + Set the Output value for the given Expander Gpio pin. + + This function is to Set the Output value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + +**/ +VOID +GpioExpSetOutput ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Value + ); +/** + Returns the data from register value giving in the input. + + This function is to get the data from the Expander + Registers by following the I2C Protocol communication + + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + + @retval UINT8 Value returned from the register +**/ +UINT8 +GpioExpGetInput ( + IN UINT8 Expander, + IN UINT8 Pin + ); + +/** + Configures all registers of a single IO Expander in one go. + + @param[in] Expander Expander number (0/1) + @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, = etc. 0=3Doutput, 1=3Dinput + @param[in] Polarity Bit-encoded input inversion values. BIT0 is for = pin0, etc. 0=3Dnormal, 1=3Dinversion + @param[in] Output Bit-encoded output state, ignores polarity, only= applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh + +**/ +VOID +GpioExpBulkConfig ( + IN UINT8 Expander, + IN UINT32 Direction, + IN UINT32 Polarity, + IN UINT32 Output + ); + +/** + Returns the Controller on which GPIO expander is present. + + This function returns the Controller value + + @param[out] Controller Pointer to a Controller value on + which I2C expander is configured. + + @retval EFI_SUCCESS non. +**/ +EFI_STATUS +GpioExpGetController ( + OUT UINT8 *Controller + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerb= TableLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerb= TableLib.h new file mode 100644 index 0000000000..f08c88f114 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerbTableLi= b.h @@ -0,0 +1,48 @@ +/** @file + + Header file for the Intel HD Audio Verb Table library. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _HDA_VERB_TABLE_LIB_H_ +#define _HDA_VERB_TABLE_LIB_H_ + +#include +#include + +enum HDAUDIO_CODEC_SELECT { + PchHdaCodecPlatformOnboard =3D 0, + PchHdaCodecExternalKit =3D 1 +}; + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HD Audio config block + @param[out] VerbTableEntryNum Number of verb table entries + @param[out] HdaVerbTablePtr Pointer to the verb table +**/ +VOID +AddPlatformVerbTables ( + IN UINT8 CodecType, + OUT UINT8 *VerbTableEntryNum, + OUT UINT32 *HdaVerbTablePtr + ); + +/** + HDA VerbTable init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +HdaVerbTableInit( + IN UINT16 BoardId + ); + +#endif \ No newline at end of file diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAcce= ssLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessL= ib.h new file mode 100644 index 0000000000..cec045091b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessLib.h @@ -0,0 +1,34 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _I2C_ACCESS_LIB_H_ +#define _I2C_ACCESS_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define WAIT_1_SECOND 1600000000 //1.6 * 10^9 + +EFI_STATUS +I2cWriteRead ( + IN UINTN MmioBase, + IN UINT8 SlaveAddress, + IN UINT8 WriteLength, + IN UINT8 *WriteBuffer, + IN UINT8 ReadLength, + IN UINT8 *ReadBuffer, + IN UINT64 TimeBudget + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlat= formLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatf= ormLib.h new file mode 100644 index 0000000000..d65586dbb9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatformLib= .h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_LIB_H_ +#define _PEI_PLATFORM_LIB_H_ + + + +#define PEI_DEVICE_DISABLED 0 +#define PEI_DEVICE_ENABLED 1 + +typedef struct { + UINT8 Register; + UINT32 Value; +} PCH_GPIO_DEV; + +// +// GPIO Initialization Data Structure +// +typedef struct{ + PCH_GPIO_DEV Use_Sel; + PCH_GPIO_DEV Use_Sel2; + PCH_GPIO_DEV Use_Sel3; + PCH_GPIO_DEV Io_Sel; + PCH_GPIO_DEV Io_Sel2; + PCH_GPIO_DEV Io_Sel3; + PCH_GPIO_DEV Lvl; + PCH_GPIO_DEV Lvl2; + PCH_GPIO_DEV Lvl3; + PCH_GPIO_DEV Inv; + PCH_GPIO_DEV Blink; + PCH_GPIO_DEV Rst_Sel; + PCH_GPIO_DEV Rst_Sel2; +} GPIO_INIT_STRUCT; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPoli= cyBoardConfigLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library= /PeiPolicyBoardConfigLib.h new file mode 100644 index 0000000000..fe947482dc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyBoard= ConfigLib.h @@ -0,0 +1,141 @@ +/** @file + Header file for the PeiPolicyBoardConfig Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_ +#define _PEI_POLICY_BOARD_CONFIG_LIB_H_ + +#include + +/** + This function performs PEI CPU Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI ME Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI PCH Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI SA Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI CPU Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI ME Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI PCH Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI SA Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI SI Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPoli= cyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPol= icyInitLib.h new file mode 100644 index 0000000000..15db1f1fbc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyInitL= ib.h @@ -0,0 +1,38 @@ +/** @file + Header file for the PolicyInitPei Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _POLICY_INIT_PEI_LIB_H_ +#define _POLICY_INIT_PEI_LIB_H_ + +/** + Initialize Intel PEI Platform Policy + + @param[in] FirmwareConfiguration It uses to skip specific policy init = that depends + on the 'FirmwareConfiguration' varaib= le. +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + IN UINT8 FirmwareConfiguration + ); + +/** + Initialize Intel PEI Platform Policy + + @param[in] PeiServices General purpose services available to = every PEIM. + @param[in] FirmwareConfiguration It uses to skip specific policy init t= hat depends + on the 'FirmwareConfiguration' varaibl= e. +**/ +VOID +EFIAPI +PeiPolicyInit ( +// IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT8 FirmwareConfiguration + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Platfor= mInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Platfor= mInitLib.h new file mode 100644 index 0000000000..f0da2db968 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PlatformInitLi= b.h @@ -0,0 +1,23 @@ +/** @file + Function prototype of PlatformInitLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INIT_LIB_H_ +#define _PLATFORM_INIT_LIB_H_ + +VOID +PlatformLateInit ( + VOID + ); + +VOID +InitSerialPort ( + VOID + ); + +#endif // _PLATFORM_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTabl= es.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h new file mode 100644 index 0000000000..8bf7deaa0c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h @@ -0,0 +1,51 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PCH_HSIO_PTSSTABLES_H_ +#define PCH_HSIO_PTSSTABLES_H_ + +#include + +/// +/// SATA PTSS Topology Types +/// +typedef enum { + PchSataTopoUnknown =3D 0x00, + PchSataTopoIsata, + PchSataTopoDirectConnect, + PchSataTopoFlex, + PchSataTopoM2 +} PCH_SATA_TOPOLOGY; + +/// +/// PCIe PTSS Topology Types +/// +typedef enum { + PchPcieTopoUnknown =3D 0x00, + PchPcieTopox1, + PchPcieTopox4, + PchPcieTopoSataE, + PchPcieTopoM2 +} PCH_PCIE_TOPOLOGY; + +/// +/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH= . +/// +typedef struct { + UINT8 LaneNum; + UINT8 PhyMode; + UINT16 Offset; + UINT32 Value; + UINT32 BitMask; +} PCH_SBI_PTSS_HSIO_TABLE; + +typedef struct { + PCH_SBI_PTSS_HSIO_TABLE PtssTable; + UINT16 Topology; +} HSIO_PTSS_TABLES; + +#endif // PCH_HSIO_PTSSTABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h new file mode 100644 index 0000000000..395d08779c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl= e.h @@ -0,0 +1,106 @@ +/** @file + PCIe Device Override Table + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_ +#define _PCIE_DEVICE_OVERRIDE_TABLE_H_ + +#include +#include + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +#endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h b/Pl= atform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h new file mode 100644 index 0000000000..ea96227e3d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h @@ -0,0 +1,33 @@ +/** @file + This header file provides platform specific definitions used + by other modules for platform specific initialization. + This is not suitable for consumption by ASL or VRF files. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +//#include "CommonDefinitions.h" +#include "PchAccess.h" +#include "SaAccess.h" + +// +// Need minimum of 48MB during PEI phase for IAG and some buffer for boot. +// +#define PEI_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) = // 80MB + 256MB +#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) = // 80MB + 256MB + +#define FLASH_BLOCK_SIZE 0x10000 + +#define CPU_EXTERNAL_CLOCK_FREQ 0x64 +#define CPU_FREQUENCY_MODE_100 0x64 +#define FREQUENCY_RESOLUTION_3182 0xc6e +#define NDIVIDER_BASE_VALUE 0x19d +#define MDIVIDER_VALUE_13 0xd + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId= .h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h new file mode 100644 index 0000000000..3545b2a05c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,29 @@ +/** @file +Defines Platform BoardIds + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_BOARD_ID_H_ +#define _PLATFORM_BOARD_ID_H_ + +#define FlavorUnknown 0x0 +#define FlavorMobile 0x1 +#define FlavorDesktop 0x2 +#define FlavorWorkstation 0x3 +#define FlavorUpServer 0x4 +#define FlavorEmbedded 0x5 +#define FlavorPlatformMax 0x6 + +#define TypeUnknown 0x0 +#define TypeTrad 0x1 +#define TypeUltUlx 0x2 + +#define BoardIdWhiskeyLakeRvp 0x60 + +#define BoardIdUnknown1 0xffff + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/Global= NvsArea.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalN= vsArea.h new file mode 100644 index 0000000000..b64cfff9a2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea= .h @@ -0,0 +1,47 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GLOBAL_NVS_AREA_H_ +#define _GLOBAL_NVS_AREA_H_ + +// +// Includes +// +#define GLOBAL_NVS_DEVICE_ENABLE 1 +#define GLOBAL_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// + +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL; + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ +{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xd= c } + +#define GLOBAL_NVS_AREA_REVISION 16 +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +// +// Global NVS Area definition +// +#include + +// +// Global NVS Area Protocol +// +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + EFI_GLOBAL_NVS_AREA *Area; +} EFI_GLOBAL_NVS_AREA_PROTOCOL; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h b/Platf= orm/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h new file mode 100644 index 0000000000..6dd6795a52 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h @@ -0,0 +1,144 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SETUP__H__ +#define __SETUP__H__ + +#ifndef MDEPKG_NDEBUG +#define DEBUG_INTERFACE_FORM_ENABLE +#endif // MDEPKG_NDEBUG +// +// Form class guid for the forms those will be showed on first front page. +// +#define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a,= 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } } +// +// Form class guid for the forms those will be showed on boot maintenance = manager menu. +// +#define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a,= 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } } + +// VFR common Definitions +#define INVENTORY(Name,Value) \ + text \ + help =3D STRING_TOKEN(STR_EMPTY), \ + text =3D Name, \ + text =3D Value, \ + flags =3D 0, \ + key =3D 0; + +#define SUBTITLE(Text) subtitle text =3D Text; +#define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY)) + +#define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\ + grayoutif TRUE;\ + oneof varid =3D SETUP_DATA.InteractiveText,\ + questionid =3D Key,\ + prompt =3D CaptionToken,\ + help =3D HelpToken,\ + option text =3D ValueToken, value =3D 0, flags =3D INTERACTIVE = | DEFAULT;\ + refresh interval =3D 1 \ + endoneof;\ + endif; + +#define SUPPRESS_GRAYOUT_ENDIF endif; endif; +#define DEFAULT_FLAG + +#define SYSTEM_ACCESS_KEY_ID 0xF000 +// +// System Access defintions. +// +#define SYSTEM_ACCESS_GUID \ + { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE,= 0xAC }} + +#define SYSTEM_PASSWORD_ADMIN 0 +#define SYSTEM_PASSWORD_USER 1 +#define ADMIN_PW_CLEAR 0 +#define ADMIN_PW_SET 1 + + +typedef struct _SYSTEM_ACCESS +{ + // + // Passwords + // + UINT8 Access; +} SYSTEM_ACCESS; + +// +// Record the password status. +// +typedef struct { + UINT8 AdminName; + UINT8 UserName; +} EFI_PASSWORD_STATUS; + +// +// Config Data +// +typedef struct { + UINT8 SerialDebug; + UINT8 SerialDebugBaudRate; + UINT8 RamDebugInterface; + UINT8 UartDebugInterface; + UINT8 Usb3DebugInterface; + UINT8 SerialIoDebugInterface; + UINT8 TraceHubDebugInterface; +} DEBUG_CONFIG_DATA; + +// +// Config Data Hob +// +#define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA + +// +// Secure Boot Data +// +typedef struct{ + UINT8 SecureBoot; +} SECURE_BOOT_VARIABLE; + +#pragma pack() + +// +// Varstore statement +// Setup is EfiVarStore that is related to EFI variable with attribute 0x0= 7 +// (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARI= ABLE_RUNTIME_ACCESS) +// +#define SETUP_DATA_VARSTORE\ + efivarstore SETUP_DATA, varid =3D 1,\ + attribute =3D 0x7, name =3D Setup, guid =3D SETUP_GUID; +#define SA_SETUP_VARSTORE\ + efivarstore SA_SETUP, varid =3D 2,\ + attribute =3D 0x7, name =3D SaSetup, guid =3D SA_SETUP_GUID; +#define CPU_SETUP_VARSTORE\ + efivarstore CPU_SETUP, varid =3D 3,\ + attribute =3D 0x7, name =3D CpuSetup, guid =3D CPU_SETUP_GUID; +#define ME_SETUP_VARSTORE\ + efivarstore ME_SETUP, varid =3D 4,\ + attribute =3D 0x7, name =3D MeSetup, guid =3D ME_SETUP_GUID; +#define PCH_SETUP_VARSTORE\ + efivarstore PCH_SETUP, varid =3D 5,\ + attribute =3D 0x7, name =3D PchSetup, guid =3D PCH_SETUP_GUID; +#define SI_SETUP_VARSTORE\ + efivarstore SI_SETUP, varid =3D 6,\ + attribute =3D 0x7, name =3D SiSetup, guid =3D SI_SETUP_GUID; +#ifdef DEBUG_INTERFACE_FORM_ENABLE +#define DEBUG_CONFIG_DATA_ID 0xF001 +#define DEBUG_CONFIG_DATA_VARSTORE\ + efivarstore DEBUG_CONFIG_DATA, varid =3D DEBUG_CONFIG_DATA_ID,\ + attribute =3D 0x7, name =3D DebugConfigData, guid =3D DEBUG_CONFIG= _GUID; +#endif // DEBUG_INTERFACE_FORM_ENABLE +#define SYSTEM_ACCESS_VARSTORE\ + varstore SYSTEM_ACCESS, varid =3D SYSTEM_ACCESS_KEY_ID,\ + name =3D SystemAccess, guid =3D SYSTEM_ACCESS_GUID; +#define SYSTEM_PASSWORD_VARSTORE\ + varstore EFI_PASSWORD_STATUS,\ + name =3D PasswordStatus, guid =3D SYSTEM_ACCESS_GUID; + +#define BOOT_FLOW_CONDITION_RECOVERY 2 +#define BOOT_FLOW_CONDITION_FIRST_BOOT 4 + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h b/Pla= tform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..4ce85de5bd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,157 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define BASE_ADDRESS_HIGH1 0x62 +#define BASE_ADDRESS_LOW1 0x63 +#define BASE_ADDRESS_HIGH2 0x64 +#define BASE_ADDRESS_LOW2 0x65 +#define BASE_ADDRESS_HIGH3 0x66 +#define BASE_ADDRESS_LOW3 0x67 +#define PRIMARY_INTERRUPT_SELECT 0x70 +#define WAKEUP_ON_IRQ_EN 0x70 +#define INTERRUPT_TYPE 0x71 +#define DMA_CHANNEL_SELECT0 0x74 +#define DMA_CHANNEL_SELECT1 0x75 + + + +// +//Port address for PILOT - III +// +#define PILOTIII_CHIP_ID 0x03 +#define PILOTIII_SIO_INDEX_PORT 0x04E +#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1) + +#define PILOTIII_UNLOCK 0x5A +#define PILOTIII_LOCK 0xA5 + +// +// logical device in PILOT-III +// +#define PILOTIII_SIO_PSR 0x00 +#define PILOTIII_SIO_COM2 0x01 +#define PILOTIII_SIO_COM1 0x02 +#define PILOTIII_SIO_SWCP 0x03 +#define PILOTIII_SIO_GPIO 0x04 +#define PILOTIII_SIO_WDT 0x05 +#define PILOTIII_SIO_KCS3 0x08 +#define PILOTIII_SIO_KCS4 0x09 +#define PILOTIII_SIO_KCS5 0x0A +#define PILOTIII_SIO_BT 0x0B +#define PILOTIII_SIO_SMIC 0x0C +#define PILOTIII_SIO_MAILBOX 0x0D +#define PILOTIII_SIO_RTC 0x0E +#define PILOTIII_SIO_SPI 0x0F +#define PILOTIII_SIO_TAP 0x10 +// +// Regisgers for Pilot-III +// +#define PILOTIII_CHIP_ID_REG 0x20 +#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PILOTIII_ACTIVATE ACTIVATE +#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1 +#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1 +#define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT + +// +// Port address for PC8374 +// +#define PC8374_SIO_INDEX_PORT 0x02E +#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1) + +// +// Logical device in PC8374 +// +#define PC8374_SIO_FLOPPY 0x00 +#define PC8374_SIO_PARA 0x01 +#define PC8374_SIO_COM2 0x02 +#define PC8374_SIO_COM1 0x03 +#define PC8374_SIO_MOUSE 0x05 +#define PC8374_SIO_KYBD 0x06 +#define PC8374_SIO_GPIO 0x07 + +// +// Registers specific for PC8374 +// +#define PC8374_CLOCK_SELECT 0x2D +#define PC8374_CLOCK_CONFIG 0x29 + +// +// Registers for PC8374 +// +#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PC8374_ACTIVATE ACTIVATE +#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT +#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0 + +#define PC87427_SERVERIO_CNF2 0x22 + + +// +// Pilot III Mailbox Data Register definitions +// +#define MBDAT00_OFFSET 0x00 +#define MBDAT01_OFFSET 0x01 +#define MBDAT02_OFFSET 0x02 +#define MBDAT03_OFFSET 0x03 +#define MBDAT04_OFFSET 0x04 +#define MBDAT05_OFFSET 0x05 +#define MBDAT06_OFFSET 0x06 +#define MBDAT07_OFFSET 0x07 +#define MBDAT08_OFFSET 0x08 +#define MBDAT09_OFFSET 0x09 +#define MBDAT10_OFFSET 0x0A +#define MBDAT11_OFFSET 0x0B +#define MBDAT12_OFFSET 0x0C +#define MBDAT13_OFFSET 0x0D +#define MBDAT14_OFFSET 0x0E +#define MBDAT15_OFFSET 0x0F +#define MBST0_OFFSET 0x10 +#define MBST1_OFFSET 0x11 +#define MBBINT_OFFSET 0x12 + +// +// Mailbox Bit definitions... +// +#define MBBINT_MBBIST_BIT 0x80 +// If both are there, use the default one +// +#define W83527_EXIST BIT2 +#define PC8374_EXIST BIT1 +#define PILOTIII_EXIST BIT0 +#define DEFAULT_SIO PILOTIII_EXIST +#define DEFAULT_KDB PC8374_EXIST + +#define IPMI_DEFAULT_SMM_IO_BASE 0xca2 +// +// For Pilot III +// + +#define PILOTIII_SWC_BASE_ADDRESS 0xA00 +#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80 +#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84 +#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86 +#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4 +#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5 +#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2 +#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3 +#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600 +#define PILOTIII_MAILBOX_MASK 0xFFE0 +#define BMC_KCS_BASE_ADDRESS 0x0CA0 +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.= asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl new file mode 100644 index 0000000000..af753e1dce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl @@ -0,0 +1,112 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) + Field(GNVS,AnyAcc,Lock,Preserve) + { + // + // Miscellaneous Dynamic Registers: + // + Offset(0), OSYS, 16, // Offset(0), Operating System + Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SM= I via I/O Trap) + Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value + Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode =3D 1) + // + // Thermal Policy Registers: + // + Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable + Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call + // + // CPU Identification Registers: + // + Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC = Enabled =3D 1) + Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads + // + // PCIe Hot Plug + // + Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control + Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value + // + // Global Variables + // + Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag. + Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt= Mode Flag. + Offset(16), L01C, 8, // Offset(16), Global L01 Counter. + Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting = Enable + Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting = Enable + Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting = Enable + Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting = Enable + Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting = Enable + Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting = Enable + Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting = Enable + Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting = Enable + Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting = Enable + Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting = Enable + Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting = Enable + Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting = Enable + Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting = Enable + Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting = Enable + Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting = Enable + Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting = Enable + Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting = Enable + Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting = Enable + Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting = Enable + Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting = Enable + Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting = Enable + Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting = Enable + Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting = Enable + Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting = Enable + Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and F= ill + Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and F= ill + Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and F= ill + Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and F= ill + Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and F= ill + Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and F= ill + Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and F= ill + Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and F= ill + Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and F= ill + Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and F= ill + Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and F= ill + Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and F= ill + Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and F= ill + Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and F= ill + Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and F= ill + Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and F= ill + Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and F= ill + Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and F= ill + Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and F= ill + Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and F= ill + Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and F= ill + Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and F= ill + Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and F= ill + Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and F= ill + Offset(65), RTD3, 8, // Offset(65), Runtime D3 support. + Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable + Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify S= leep State Change + Offset(68), PSCP, 8, // Offset(68), P-state Capping + Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable + Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enabl= e + // + // Driver Mode + // + Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ + Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering = CS + Offset(76), PLVL, 16, // Offset(76), PL1 limit value + Offset(78), PB1E, 8, // Offset(78), 10sec Power button support + Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr + Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support + Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug + Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port se= lector + Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port se= lector + } + --=20 2.16.2.windows.1