From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.2147.1667993479682229264 for ; Wed, 09 Nov 2022 03:31:19 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=it9oXE7d; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ted.kuo@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667993479; x=1699529479; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Drp7HgcsdMiVHCwj/TcPTgujLYI9UqTmfCXFRe6Quwc=; b=it9oXE7d6mUjUBW0jexhdDQTmJxNSeOWP9VfKwNBhuvPlawjtMAxkupc EADIA+L1JDyOx5TNTT6S6X51PHtfQMDk+sQEg8wAgaU9Bocm881BGEOgK 0xvLZxZ4f9GARQ6hoxgHD18XuQmgNLdZt8qTafMmltqKSWGttx+5DlDw0 5jit+ZCG8CjQdcUzImmR384/JUg7/8+tcXwRIbfu1SoKiz6lgCeWsFJie uDVflqpA922E3tyeDtSqTqmBO1eOxYy1Blf7rcFTfz7WCn1RiTZDKLJ4Z hcmgpeA6iRNc6dktuDIkrFqxI7gSfzuRROoTVQxRCi0VkQA0c8lkSjigU Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="312753426" X-IronPort-AV: E=Sophos;i="5.96,150,1665471600"; d="scan'208";a="312753426" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 03:31:11 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="639167475" X-IronPort-AV: E=Sophos;i="5.96,150,1665471600"; d="scan'208";a="639167475" Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 03:31:09 -0800 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S , Chinni B Duggapu Subject: [edk2-devel][PATCH v1] IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T Date: Wed, 9 Nov 2022 19:30:57 +0800 Message-Id: <982993884529155a9bba1fa0a09a33301a0ded35.1667982515.git.ted.kuo@intel.com> X-Mailer: git-send-email 2.35.3.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Signed-off-by: Ted Kuo --- .../FspSecCore/Ia32/FspApiEntryT.nasm | 17 +++-- IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm | 4 +- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 74 ++++++++++--------- IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 4 +- 5 files changed, 55 insertions(+), 46 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 73821ad22a..2cff8b3643 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi): SAVE_EAX=0D SAVE_EDX=0D =0D + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D + SAVE_ECX ; save UPD param to slot 3 in xmm= 6=0D +=0D ;=0D ; Sec Platform Init=0D ;=0D - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D CALL_MMX ASM_PFX(SecPlatformInit)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D ; Load microcode=0D LOAD_ESP=0D - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D + LOAD_ECX=0D CALL_MMX ASM_PFX(LoadMicrocodeDefault)=0D - SXMMN xmm6, 3, eax ;Save microcode return status in ECX-S= LOT 3 in xmm6.=0D + SAVE_UCODE_STATUS ; Save microcode return status in slot= 1 in xmm5.=0D ;@note If return value eax is not 0, microcode did not load, but continu= e and attempt to boot.=0D =0D ; Call Sec CAR Init=0D LOAD_ESP=0D - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D + LOAD_ECX=0D CALL_MMX ASM_PFX(SecCarInit)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D LOAD_ESP=0D - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D - mov edi, ecx ; Save UPD param to EDI for later= code use=0D + LOAD_ECX=0D + mov edi, ecx ; Save UPD param to EDI for later code= use=0D CALL_MMX ASM_PFX(EstablishStackFsp)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error f= rom ECX-SLOT 3 in xmm6.=0D - SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 = in xmm6.=0D + LOAD_UCODE_STATUS ; Restore microcode status if no CAR i= nit error from slot 1 in xmm5.=0D =0D TempRamInitExit:=0D mov bl, al ; save al data in bl=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm b/IntelFsp2Pkg/Fsp= SecCore/Ia32/FspHelper.nasm index e3e1945473..3c63f6eea5 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm @@ -7,6 +7,8 @@ =0D SECTION .text=0D =0D +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch=0D +=0D global ASM_PFX(FspInfoHeaderRelativeOff)=0D ASM_PFX(FspInfoHeaderRelativeOff):=0D DD 0x12345678 ; This value must be patched by the buil= d script=0D @@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): global ASM_PFX(AsmGetFspBaseAddress)=0D ASM_PFX(AsmGetFspBaseAddress):=0D call ASM_PFX(AsmGetFspInfoHeader)=0D - add eax, 0x1C=0D + add eax, FSP_HEADER_IMGBASE_OFFSET=0D mov eax, dword [eax]=0D ret=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..a222f2e376 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= -----=0D ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Abstract:=0D @@ -16,21 +16,21 @@ ;=0D ; Define SSE macros using SSE 4.1 instructions=0D ; args 1:XMM, 2:IDX, 3:REG=0D -%macro SXMMN 3=0D +%macro SXMMN 3=0D pinsrd %1, %3, (%2 & 3)=0D %endmacro=0D =0D ;=0D ;args 1:XMM, 2:REG, 3:IDX=0D ;=0D -%macro LXMMN 3=0D +%macro LXMMN 3=0D pextrd %2, %1, (%3 & 3)=0D %endmacro=0D %else=0D ;=0D ; Define SSE macros using SSE 2 instructions=0D ; args 1:XMM, 2:IDX, 3:REG=0D -%macro SXMMN 3=0D +%macro SXMMN 3=0D pinsrw %1, %3, (%2 & 3) * 2=0D ror %3, 16=0D pinsrw %1, %3, (%2 & 3) * 2 + 1=0D @@ -38,19 +38,19 @@ %endmacro=0D =0D ;=0D -;args 1:XMM, 2:REG, 3:IDX=0D +;args 1:XMM, 2:REG, 3:IDX=0D ;=0D %macro LXMMN 3=0D - pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)=0D + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)=0D movd %2, %1=0D - pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FF= h)=0D + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh= )=0D %endmacro=0D %endif=0D =0D ;=0D -; XMM7 to save/restore EBP, EBX, ESI, EDI=0D +; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slo= t 3=0D ;=0D -%macro SAVE_REGS 0=0D +%macro SAVE_REGS 0=0D SXMMN xmm7, 0, ebp=0D SXMMN xmm7, 1, ebx=0D SXMMN xmm7, 2, esi=0D @@ -67,63 +67,67 @@ %endmacro=0D =0D ;=0D -; XMM6 to save/restore EAX, EDX, ECX, ESP=0D +; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slo= t 3=0D ;=0D -%macro LOAD_EAX 0=0D +%macro LOAD_ESP 0=0D + movd esp, xmm6=0D + %endmacro=0D +=0D +%macro SAVE_ESP 0=0D + SXMMN xmm6, 0, esp=0D + %endmacro=0D +=0D +%macro LOAD_EAX 0=0D LXMMN xmm6, eax, 1=0D %endmacro=0D =0D -%macro SAVE_EAX 0=0D +%macro SAVE_EAX 0=0D SXMMN xmm6, 1, eax=0D %endmacro=0D =0D -%macro LOAD_EDX 0=0D +%macro LOAD_EDX 0=0D LXMMN xmm6, edx, 2=0D %endmacro=0D =0D -%macro SAVE_EDX 0=0D +%macro SAVE_EDX 0=0D SXMMN xmm6, 2, edx=0D %endmacro=0D =0D -%macro SAVE_ECX 0=0D - SXMMN xmm6, 3, ecx=0D - %endmacro=0D -=0D -%macro LOAD_ECX 0=0D +%macro LOAD_ECX 0=0D LXMMN xmm6, ecx, 3=0D %endmacro=0D =0D -%macro SAVE_ESP 0=0D - SXMMN xmm6, 0, esp=0D +%macro SAVE_ECX 0=0D + SXMMN xmm6, 3, ecx=0D %endmacro=0D =0D -%macro LOAD_ESP 0=0D - movd esp, xmm6=0D - %endmacro=0D ;=0D -; XMM5 for calling stack=0D +; XMM5 slot 0 for calling stack=0D ; arg 1:Entry=0D %macro CALL_XMM 1=0D mov esi, %%ReturnAddress=0D - pslldq xmm5, 4=0D -%ifdef USE_SSE41_FLAG=0D - pinsrd xmm5, esi, 0=0D -%else=0D - pinsrw xmm5, esi, 0=0D - ror esi, 16=0D - pinsrw xmm5, esi, 1=0D -%endif=0D + SXMMN xmm5, 0, esi=0D mov esi, %1=0D jmp esi=0D %%ReturnAddress:=0D %endmacro=0D =0D %macro RET_XMM 0=0D - movd esi, xmm5=0D - psrldq xmm5, 4=0D + LXMMN xmm5, esi, 0=0D jmp esi=0D %endmacro=0D =0D +;=0D +; XMM5 slot 1 for uCode status=0D +;=0D +%macro LOAD_UCODE_STATUS 0=0D + LXMMN xmm5, eax, 1=0D + %endmacro=0D +=0D +%macro SAVE_UCODE_STATUS 0=0D + SXMMN xmm5, 1, eax=0D + %endmacro=0D +=0D %macro ENABLE_SSE 0=0D ;=0D ; Initialize floating point units=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.h index d7a5976c12..693af29f20 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h @@ -79,7 +79,7 @@ AsmGetFspBaseAddress ( /**=0D This interface gets FspInfoHeader pointer=0D =0D - @return FSP binary base address.=0D + @return FSP info header.=0D =0D **/=0D UINTN=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspS= ecCore/X64/FspHelper.nasm index 122fa1d174..71624a3aad 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -7,10 +7,12 @@ DEFAULT REL=0D SECTION .text=0D =0D +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch=0D +=0D global ASM_PFX(AsmGetFspBaseAddress)=0D ASM_PFX(AsmGetFspBaseAddress):=0D call ASM_PFX(AsmGetFspInfoHeader)=0D - add rax, 0x1C=0D + add rax, FSP_HEADER_IMGBASE_OFFSET=0D mov eax, [rax]=0D ret=0D =0D --=20 2.35.3.windows.1