[edk2-platforms] [PATCH V2 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[edk2-platforms] [PATCH V2 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[Nate DeSimone]

Changes in V2:
 - Moved FSP dispatch mode PCD additions for GalagoPro3 to a seperate patch series

This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT
to 1 and 3 respectively. This will enable OS power management to set the CPU
clock speed in the P_CNT register on these platforms.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Heng Luo <heng.luo@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Nate DeSimone (4):
  KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

 .../CometlakeURvp/OpenBoardPkgPcd.dsc                 |  9 ++++++++-
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc             |  9 ++++++++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc                    |  8 +++++++-
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc                  | 11 +++++++++--
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc                 | 10 +++++++++-
 .../UpXtreme/OpenBoardPkgPcd.dsc                      |  9 ++++++++-
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc               |  9 ++++++++-
 7 files changed, 57 insertions(+), 8 deletions(-)

-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc             |  9 ++++++++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc                    |  8 +++++++-
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc                  | 11 +++++++++--
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the Aspire VN7-572G board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -346,6 +346,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..dce4db17c2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the GalagoPro3 board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -251,6 +251,12 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
   gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
   gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 725596cbf7..ccf757e202 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the KabylakeRvp3 board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -78,6 +78,7 @@
   # so FSP needs more temporary memory for FSP heap + stack size.
   #
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
+
   #
   # FSP API mode does not need to enlarge the boot loader stack size
   # since the stacks are separate.
@@ -290,6 +291,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
@@ -346,7 +354,6 @@
   gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 !endif
 
-
   ######################################
   # Board Configuration
   ######################################
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++-
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index 84d4ec1331..8f3cc6ba28 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the UpXtreme board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -259,6 +259,13 @@
   gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
   gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 4a7ba4d5f0..4a5d5ef03b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the WhiskeylakeURvp board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -242,6 +242,13 @@
   ######################################
   gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
   #
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V2 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the TigerlakeURvp board.
 #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -118,6 +118,14 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
 #!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
 [PcdsFeatureFlag.common]
   ######################################
   # Edk2 Configuration
-- 
2.27.0.windows.1

Re: [edk2-devel] [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 6/6/2022 7:16 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Benjamin Doron <benjamin.doron00@gmail.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc             |  9 ++++++++-
>   .../GalagoPro3/OpenBoardPkgPcd.dsc                    |  8 +++++++-
>   .../KabylakeRvp3/OpenBoardPkgPcd.dsc                  | 11 +++++++++--
>   3 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> index 21ee86403d..02080aa864 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the Aspire VN7-572G board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -346,6 +346,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..dce4db17c2 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the GalagoPro3 board.
>   #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -251,6 +251,12 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
>     gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>     gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
>   
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> index 725596cbf7..ccf757e202 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the KabylakeRvp3 board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -78,6 +78,7 @@
>     # so FSP needs more temporary memory for FSP heap + stack size.
>     #
>     gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> +
>     #
>     # FSP API mode does not need to enlarge the boot loader stack size
>     # since the stacks are separate.
> @@ -290,6 +291,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> @@ -346,7 +354,6 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>   !endif
>   
> -
>     ######################################
>     # Board Configuration
>     ######################################

Re: [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Chiu, Chasel]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

Thanks,
Chasel


> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 7:17 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>; Benjamin Doron
> <benjamin.doron00@gmail.com>; Soller, Jeremy <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Benjamin Doron <benjamin.doron00@gmail.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc             |  9 ++++++++-
>  .../GalagoPro3/OpenBoardPkgPcd.dsc                    |  8 +++++++-
>  .../KabylakeRvp3/OpenBoardPkgPcd.dsc                  | 11 +++++++++--
>  3 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> index 21ee86403d..02080aa864 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
> +++ Pcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the Aspire VN7-572G board.
>  #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -346,6 +346,13 @@
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and
> BIOS Guard not present, measured boot enforcement checking code not present
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..dce4db17c2 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the GalagoPro3 board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -251,6 +251,12 @@
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> 
> gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui
> d.PcdPciExpressBaseAddress
> 
> gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp
> aceGuid.PcdPciExpressRegionLength
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> index 725596cbf7..ccf757e202 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
> +++ sc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the KabylakeRvp3 board.
>  #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -78,6 +78,7 @@
>    # so FSP needs more temporary memory for FSP heap + stack size.
>    #
>    gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> +
>    #
>    # FSP API mode does not need to enlarge the boot loader stack size
>    # since the stacks are separate.
> @@ -290,6 +291,13 @@
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>    gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> @@ -346,7 +354,6 @@
>    gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}  !endif
> 
> -
>    ######################################
>    # Board Configuration
>    ######################################
> --
> 2.27.0.windows.1

Re: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Chiu, Chasel]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

Thanks,
Chasel


> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 7:17 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>
> Subject: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++-
>  .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> index 84d4ec1331..8f3cc6ba28 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
> +++ c
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the UpXtreme board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -259,6 +259,13 @@
>    gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa
> ceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> index 4a7ba4d5f0..4a5d5ef03b 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
> +++ gPcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the WhiskeylakeURvp board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -242,6 +242,13 @@
>    ######################################
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa
> ceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> --
> 2.27.0.windows.1

Re: [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Chiu, Chasel]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

Thanks,
Chasel


> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 7:17 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Esakkithevar, Kathappan
> <kathappan.esakkithevar@intel.com>
> Subject: [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> index 589b002d06..68dd08423b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the CometlakeURvp board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -253,6 +253,13 @@
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    #
>    # The PCDs are used to control the Windows SMM Security Mitigations Table -
> Protection Flags
>    #
> --
> 2.27.0.windows.1