From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web08.4048.1664532559809144706 for ; Fri, 30 Sep 2022 03:09:20 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72tJwDZjmygkAA--.631S2; Fri, 30 Sep 2022 18:09:13 +0800 (CST) Date: Fri, 30 Sep 2022 18:09:13 +0800 From: "Chao Li" To: Michael D Kinney Cc: Liming Gao , Zhiguang Liu , Baoqi Zhang , "=?utf-8?Q?=22_devel=40edk2.groups.io_=22?=" Message-ID: <9A9DFFB1-31DB-4C7C-8FF7-D5E7A5C34973@getmailspring.com> In-Reply-To: <1F8DF3E6-E3A3-41BF-9A53-48BABFD03BF0@getmailspring.com> References: <1F8DF3E6-E3A3-41BF-9A53-48BABFD03BF0@getmailspring.com> Subject: Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cx72tJwDZjmygkAA--.631S2 X-Coremail-Antispam: 1UD129KBjvJXoWfGr1rAF45Cw4kGw48KryxuFg_yoWkGw15pr 43trZrKan2gw43CF48G3s5GF15Aw4kWr4DGFZ0vw18Awn0vrykZrs8tr10gFW8urW7Ww18 WF13KF4Fk3WUAa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBmb7Iv0xC_KF4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I 8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVAYj202 j2C_Jr0_Gr1l5I8CrVACY4xI64kE6c02F40Ex7xfMc02F40Ew4AK048IF2xKxVW8JVW5Jw Av7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY 6r1j6r4UM4x0Y48IcxkI7VAKI48JMx8GjcxK6IxK0xIIj40E5I8CrwCY02Avz4vE-syl42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUGVWU WwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU41xRDUUUU X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAFCGM2YT47eQACsG Content-Type: multipart/alternative; boundary="6336c049_33c64965_1b923" --6336c049_33c64965_1b923 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, I'm guessing you're a little busy, or forgot about this issue. :) I have converted the inline assembly code to ASM code, please review this= patch again, thanks=21 Thanks, Chao -------- On 9=E6=9C=88 27 2022, at 7:27 =E6=99=9A=E4=B8=8A, chao li wrote: > Hi Mike, > I have converted the inline assembly code to ASM code, please review th= is patch again, thanks=21 > > > Thanks, > Chao > -------- > > On 9=E6=9C=88 27 2022, at 7:13 =E6=99=9A=E4=B8=8A, Chao Li wrote: > > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > > > Support LoongArch cache related functions. > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Zhiguang Liu > > > > Signed-off-by: Chao Li > > Co-authored-by: Baoqi Zhang > > --- > > .../BaseSynchronizationLib.inf =7C 6 + > > .../LoongArch64/AsmSynchronization.S =7C 122 +++++++++ > > .../LoongArch64/Synchronization.c =7C 233 ++++++++++++++++++ > > 3 files changed, 361 insertions(+) > > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/= AsmSynchronization.S > > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/= Synchronization.c > > > > diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizatio= nLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf > > index 02ba12961a..dd66ec1d03 100755 > > --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.in= f > > +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.in= f > > =40=40 -4,6 +4,7 =40=40 > > =23 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved= .
> > > > =23 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserve= d.
> > =23 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
> > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All= rights reserved.
> > =23 > > =23 SPDX-License-Identifier: BSD-2-Clause-Patent > > =23 > > =40=40 -82,6 +83,11 =40=40 > > Synchronization.c > > > > RiscV64/Synchronization.S > > > > > > +=5BSources.LOONGARCH64=5D > > + Synchronization.c > > + LoongArch64/Synchronization.c =7C GCC > > + LoongArch64/AsmSynchronization.S =7C GCC > > + > > =5BPackages=5D > > MdePkg/MdePkg.dec > > > > > > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSyn= chronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSyn= chronization.S > > new file mode 100644 > > index 0000000000..3f1b06172d > > --- /dev/null > > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchroniz= ation.S > > =40=40 -0,0 +1,122 =40=40 > > +=23-----------------------------------------------------------------= ------------- > > +=23 > > +=23 LoongArch synchronization ASM functions. > > +=23 > > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All= rights reserved.
> > +=23 > > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > > +=23 > > +=23-----------------------------------------------------------------= ------------- > > + > > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange16) > > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange32) > > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange64) > > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncIncrement) > > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncDecrement) > > + > > +/** > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncCompareExchange16 ( > > + IN volatile UINT32 *Ptr32, > > + IN UINT64 Mask, > > + IN UINT64 LocalCompareValue, > > + IN UINT64 LocalExchangeValue > > + ) > > +**/ > > +ASM=5FP=46X(AsmInternalSyncCompareExchange16): > > +1: > > + ll.w =24t0, =24a0, 0x0 > > + and =24t1, =24t0, =24a1 > > + bne =24t1, =24a2, 2f > > + andn =24t1, =24t0, =24a1 > > + or =24t1, =24t1, =24a3 > > + sc.w =24t1, =24a0, 0x0 > > + beqz =24t1, 1b > > + b 3f > > +2: > > + dbar 0 > > +3: > > + move =24a0, =24t0 > > + jirl =24zero, =24ra, 0 > > + > > +/** > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncCompareExchange32 ( > > + IN volatile UINT32 *Value, > > + IN UINT64 CompareValue, > > + IN UINT64 ExchangeValue > > + ) > > +**/ > > +ASM=5FP=46X(AsmInternalSyncCompareExchange32): > > +1: > > + ll.w =24t0, =24a0, 0x0 > > + bne =24t0, =24a1, 2f > > + move =24t0, =24a2 > > + sc.w =24t0, =24a0, 0x0 > > + beqz =24t0, 1b > > + b 3f > > +2: > > + dbar 0 > > +3: > > + move =24a0, =24t0 > > + jirl =24zero, =24ra, 0 > > + > > +/** > > +UINT64 > > +E=46IAPI > > +AsmInternalSyncCompareExchange64 ( > > + IN volatile UINT64 *Value, > > + IN UINT64 CompareValue, > > + IN UINT64 ExchangeValue > > + ) > > +**/ > > +ASM=5FP=46X(AsmInternalSyncCompareExchange64): > > +1: > > + ll.d =24t0, =24a0, 0x0 > > + bne =24t0, =24a1, 2f > > + move =24t0, =24a2 > > + sc.d =24t0, =24a0, 0x0 > > + beqz =24t0, 1b > > + b 3f > > +2: > > + dbar 0 > > +3: > > + move =24a0, =24t0 > > + jirl =24zero, =24ra, 0 > > + > > +/** > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncIncrement ( > > + IN volatile UINT32 *Value > > + ) > > +**/ > > +ASM=5FP=46X(AsmInternalSyncIncrement): > > + move =24t0, =24a0 > > + dbar 0 > > + ld.w =24t1, =24t0, 0x0 > > + li.w =24t2, 1 > > + amadd.w =24t1, =24t2, =24t0 > > + > > + ld.w =24a0, =24t0, 0x0 > > + jirl =24zero, =24ra, 0 > > + > > +/** > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncDecrement ( > > + IN volatile UINT32 *Value > > + ) > > +**/ > > +ASM=5FP=46X(AsmInternalSyncDecrement): > > + move =24t0, =24a0 > > + dbar 0 > > + ld.w =24t1, =24t0, 0x0 > > + li.w =24t2, -1 > > + amadd.w =24t1, =24t2, =24t0 > > + > > + ld.w =24a0, =24t0, 0x0 > > + jirl =24zero, =24ra, 0 > > +.end > > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchr= onization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchroni= zation.c > > new file mode 100644 > > index 0000000000..d696c8ce10 > > --- /dev/null > > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronizati= on.c > > =40=40 -0,0 +1,233 =40=40 > > +/** =40file > > > > + LoongArch synchronization functions. > > + > > + Copyright (c) 2022, Loongson Technology Corporation Limited. All ri= ghts reserved.
> > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +=23include > > + > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncCompareExchange16 ( > > + IN volatile UINT32 *, > > + IN UINT64, > > + IN UINT64, > > + IN UINT64 > > + ); > > + > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncCompareExchange32 ( > > + IN volatile UINT32 *, > > + IN UINT64, > > + IN UINT64 > > + ); > > + > > +UINT64 > > +E=46IAPI > > +AsmInternalSyncCompareExchange64 ( > > + IN volatile UINT64 *, > > + IN UINT64, > > + IN UINT64 > > + ); > > + > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncIncrement ( > > + IN volatile UINT32 * > > + ); > > + > > +UINT32 > > +E=46IAPI > > +AsmInternalSyncDecrement ( > > + IN volatile UINT32 * > > + ); > > + > > +/** > > + Performs an atomic compare exchange operation on a 16-bit > > + unsigned integer. > > + > > + Performs an atomic compare exchange operation on the 16-bit > > + unsigned integer specified by Value. If Value is equal to > > + CompareValue, then Value is set to ExchangeValue and > > + CompareValue is returned. If Value is not equal to > > + CompareValue, then Value is returned. The compare exchange > > + operation must be performed using MP safe mechanisms. > > + > > + =40param=5Bin=5D Value A pointer to the 16-bit value for the > > + compare exchange operation. > > + =40param=5Bin=5D CompareValue 16-bit value used in compare operatio= n. > > + =40param=5Bin=5D ExchangeValue 16-bit value used in exchange operat= ion. > > + > > + =40return The original *Value before exchange. > > + > > +**/ > > +UINT16 > > +E=46IAPI > > +InternalSyncCompareExchange16 ( > > + IN volatile UINT16 *Value, > > + IN UINT16 CompareValue, > > + IN UINT16 ExchangeValue > > + ) > > +=7B > > + UINT32 RetValue; > > + UINT32 Shift; > > + UINT64 Mask; > > + UINT64 LocalCompareValue; > > + UINT64 LocalExchangeValue; > > + volatile UINT32 *Ptr32; > > + > > + /* Check that ptr is naturally aligned */ > > + ASSERT (=21((UINT64)Value & (sizeof (Value) - 1))); > > + > > + /* Mask inputs to the correct size. */ > > + Mask =3D (((=7E0UL) - (1UL << (0)) + 1) & (=7E0UL >> (64 - 1 - ((si= zeof (UINT16) * 8) - 1)))); > > + LocalCompareValue =3D ((UINT64)CompareValue) & Mask; > > + LocalExchangeValue =3D ((UINT64)ExchangeValue) & Mask; > > + > > + /* > > + * Calculate a shift & mask that correspond to the value we wish to > > + * compare & exchange within the naturally aligned 4 byte integer > > + * that includes it. > > + */ > > + Shift =3D (UINT64)Value & 0x3; > > + Shift *=3D 8; /* BITS=5FPER=5FBYTE */ > > + LocalCompareValue <<=3D Shift; > > + LocalExchangeValue <<=3D Shift; > > + Mask <<=3D Shift; > > + > > + /* > > + * Calculate a pointer to the naturally aligned 4 byte integer that > > + * includes our byte of interest, and load its value. > > + */ > > + Ptr32 =3D (UINT32 *)((UINT64)Value & =7E0x3); > > + > > + RetValue =3D AsmInternalSyncCompareExchange16 ( > > + Ptr32, > > + Mask, > > + LocalCompareValue, > > + LocalExchangeValue > > + ); > > + > > + return (RetValue & Mask) >> Shift; > > +=7D > > + > > +/** > > + Performs an atomic compare exchange operation on a 32-bit > > + unsigned integer. > > + > > + Performs an atomic compare exchange operation on the 32-bit > > + unsigned integer specified by Value. If Value is equal to > > + CompareValue, then Value is set to ExchangeValue and > > + CompareValue is returned. If Value is not equal to > > + CompareValue, then Value is returned. The compare exchange > > + operation must be performed using MP safe mechanisms. > > + > > + =40param=5Bin=5D Value A pointer to the 32-bit value for the > > + compare exchange operation. > > + =40param=5Bin=5D CompareValue 32-bit value used in compare operatio= n. > > + =40param=5Bin=5D ExchangeValue 32-bit value used in exchange operat= ion. > > + > > + =40return The original *Value before exchange. > > + > > +**/ > > +UINT32 > > +E=46IAPI > > +InternalSyncCompareExchange32 ( > > + IN volatile UINT32 *Value, > > + IN UINT32 CompareValue, > > + IN UINT32 ExchangeValue > > + ) > > +=7B > > + UINT32 RetValue; > > + > > + RetValue =3D AsmInternalSyncCompareExchange32 ( > > + Value, > > + CompareValue, > > + ExchangeValue > > + ); > > + > > + return RetValue; > > +=7D > > + > > +/** > > + Performs an atomic compare exchange operation on a 64-bit unsigned = integer. > > + > > + Performs an atomic compare exchange operation on the 64-bit unsigne= d integer specified > > + by Value. If Value is equal to CompareValue, then Value is set to E= xchangeValue and > > + CompareValue is returned. If Value is not equal to CompareValue, th= en Value is returned. > > + The compare exchange operation must be performed using MP safe mech= anisms. > > + > > + =40param=5Bin=5D Value A pointer to the 64-bit value for the compar= e exchange > > + operation. > > + =40param=5Bin=5D CompareValue 64-bit value used in compare operatio= n. > > + =40param=5Bin=5D ExchangeValue 64-bit value used in exchange operat= ion. > > + > > + =40return The original *Value before exchange. > > + > > +**/ > > +UINT64 > > +E=46IAPI > > +InternalSyncCompareExchange64 ( > > + IN volatile UINT64 *Value, > > + IN UINT64 CompareValue, > > + IN UINT64 ExchangeValue > > + ) > > +=7B > > + UINT64 RetValue; > > + > > + RetValue =3D AsmInternalSyncCompareExchange64 ( > > + Value, > > + CompareValue, > > + ExchangeValue > > + ); > > + > > + return RetValue; > > +=7D > > + > > +/** > > + Performs an atomic increment of an 32-bit unsigned integer. > > + > > + Performs an atomic increment of the 32-bit unsigned integer specifi= ed by > > + Value and returns the incremented value. The increment operation mu= st be > > + performed using MP safe mechanisms. The state of the return value i= s not > > + guaranteed to be MP safe. > > + > > + =40param=5Bin=5D Value A pointer to the 32-bit value to increment. > > + > > + =40return The incremented value. > > + > > +**/ > > +UINT32 > > +E=46IAPI > > +InternalSyncIncrement ( > > + IN volatile UINT32 *Value > > + ) > > +=7B > > + return AsmInternalSyncIncrement (Value); > > +=7D > > + > > +/** > > + Performs an atomic decrement of an 32-bit unsigned integer. > > + > > + Performs an atomic decrement of the 32-bit unsigned integer specifi= ed by > > + Value and returns the decrement value. The decrement operation must= be > > + performed using MP safe mechanisms. The state of the return value i= s not > > + guaranteed to be MP safe. > > + > > + =40param=5Bin=5D Value A pointer to the 32-bit value to decrement. > > + > > + =40return The decrement value. > > + > > +**/ > > +UINT32 > > +E=46IAPI > > +InternalSyncDecrement ( > > + IN volatile UINT32 *Value > > + ) > > +=7B > > + return AsmInternalSyncDecrement (Value); > > +=7D > > -- > > 2.27.0 > > > --6336c049_33c64965_1b923 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike,
I'm guessing you're a little busy, or forgot about this issue. :)
I have converted the inline assembly code to ASM code, please revie= w this patch again, thanks=21


= Thanks,
Chao
--------

On 9=E6=9C=88 27 2022, at 7:27 =E6=99=9A=E4= =B8=8A, chao li <lichao=40loongson.cn> wrote:
Hi Mike,
I have converted the inline assembly code to ASM code= , please review this patch again, thanks=21


<= span style=3D=22color:grey=22>Thanks,<= /font>
Chao
--------

On 9=E6=9C=88 27= 2022, at 7:13 =E6=99=9A=E4=B8=8A, Chao Li <lichao=40loongson.cn> w= rote:
RE=46: https://bugzilla.tianocore.org/sh= ow=5Fbug.cgi=3Fid=3D4053

Support LoongArch cache related fu= nctions.

Cc: Michael D Kinney <michael.d.kinney=40intel.= com>
Cc: Liming Gao <gaoliming=40byosoft.com.cn>
=
Cc: Zhiguang Liu <zhiguang.liu=40intel.com>

Sign= ed-off-by: Chao Li <lichao=40loongson.cn>
Co-authored-by:= Baoqi Zhang <zhangbaoqi=40loongson.cn>
---
...= /BaseSynchronizationLib.inf =7C 6 +
.../LoongArch64/AsmSynchron= ization.S =7C 122 +++++++++
.../LoongArch64/Synchronization.c =7C= 233 ++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch6= 4/AsmSynchronization.S
create mode 100644 MdePkg/Library/BaseSy= nchronizationLib/LoongArch64/Synchronization.c

diff --git a= /MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePk= g/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
ind= ex 02ba12961a..dd66ec1d03 100755
--- a/MdePkg/Library/BaseSynch= ronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/B= aseSynchronizationLib/BaseSynchronizationLib.inf
=40=40 -4,6 +4= ,7 =40=40
=23 Copyright (c) 2007 - 2018, Intel Corporation. All= rights reserved.<BR>

=23 Portions copyright (c) 2008= - 2009, Apple Inc. All rights reserved.<BR>

=23 Copy= right (c) 2020, Hewlett Packard Enterprise Development LP. All rights res= erved.<BR>

+=23 Copyright (c) 2022, Loongson Technolo= gy Corporation Limited. All rights reserved.<BR>

=23<= /div>
=23 SPDX-License-Identifier: BSD-2-Clause-Patent

<= div>=23

=40=40 -82,6 +83,11 =40=40
Synchronizatio= n.c

RiscV64/Synchronization.S



+=5BSou= rces.LOONGARCH64=5D

+ Synchronization.c

+ Loo= ngArch64/Synchronization.c =7C GCC

+ LoongArch64/AsmSynchro= nization.S =7C GCC

+

=5BPackages=5D

=
MdePkg/MdePkg.dec



diff --git a/MdePkg/Library/= BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/= BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
new fil= e mode 100644
index 0000000000..3f1b06172d
--- /dev/n= ull
+++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Asm= Synchronization.S
=40=40 -0,0 +1,122 =40=40
+=23-----= -------------------------------------------------------------------------=
+=23
+=23 LoongArch synchronization ASM functions.
+=23
+=23 Copyright (c) 2022, Loongson Technology Corp= oration Limited. All rights reserved.<BR>
+=23
= +=23 SPDX-License-Identifier: BSD-2-Clause-Patent
+=23
+=23-------------------------------------------------------------------= -----------
+
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSy= ncCompareExchange16)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncC= ompareExchange32)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncComp= areExchange64)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncIncreme= nt)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncDecrement)
+
+/**
+UINT32
+E=46IAPI
+AsmI= nternalSyncCompareExchange16 (
+ IN volatile UINT32 *Ptr32,
+ IN UINT64 Mask,
+ IN UINT64 LocalCompareValue,
+ IN UINT64 LocalExchangeValue
+ )
+**/
= +ASM=5FP=46X(AsmInternalSyncCompareExchange16):
+1:
+= ll.w =24t0, =24a0, 0x0
+ and =24t1, =24t0, =24a1
+ b= ne =24t1, =24a2, 2f
+ andn =24t1, =24t0, =24a1
+ or =24= t1, =24t1, =24a3
+ sc.w =24t1, =24a0, 0x0
+ beqz =24t= 1, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move =24a0, =24t0
+ jirl =24zero, =24ra, 0
+=
+/**
+UINT32
+E=46IAPI
+AsmInter= nalSyncCompareExchange32 (
+ IN volatile UINT32 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+**/
+ASM=5FP=46X(AsmInternalSyncCompareExchang= e32):
+1:
+ ll.w =24t0, =24a0, 0x0
+ bne =24= t0, =24a1, 2f
+ move =24t0, =24a2
+ sc.w =24t0, =24a0= , 0x0
+ beqz =24t0, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move =24a0, =24t0
+ jirl =24= zero, =24ra, 0
+
+/**
+UINT64
+E=46= IAPI
+AsmInternalSyncCompareExchange64 (
+ IN volatil= e UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT6= 4 ExchangeValue
+ )
+**/
+ASM=5FP=46X(AsmIn= ternalSyncCompareExchange64):
+1:
+ ll.d =24t0, =24a0= , 0x0
+ bne =24t0, =24a1, 2f
+ move =24t0, =24a2
+ sc.d =24t0, =24a0, 0x0
+ beqz =24t0, 1b
+ b 3= f
+2:
+ dbar 0
+3:
+ move =24a0, = =24t0
+ jirl =24zero, =24ra, 0
+
+/**
=
+UINT32
+E=46IAPI
+AsmInternalSyncIncrement (
+ IN volatile UINT32 *Value
+ )
+**/
+ASM=5FP=46X(AsmInternalSyncIncrement):
+ move =24t0, =24a0
+ dbar 0
+ ld.w =24t1, =24t0, 0x0
+ li.w =24= t2, 1
+ amadd.w =24t1, =24t2, =24t0
+
+ ld.= w =24a0, =24t0, 0x0
+ jirl =24zero, =24ra, 0
+
<= div>+/**
+UINT32
+E=46IAPI
+AsmInternalSync= Decrement (
+ IN volatile UINT32 *Value
+ )
+**/
+ASM=5FP=46X(AsmInternalSyncDecrement):
+ move = =24t0, =24a0
+ dbar 0
+ ld.w =24t1, =24t0, 0x0
<= div>+ li.w =24t2, -1
+ amadd.w =24t1, =24t2, =24t0
+<= /div>
+ ld.w =24a0, =24t0, 0x0
+ jirl =24zero, =24ra, 0
+.end
diff --git a/MdePkg/Library/BaseSynchronizationLib= /LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/Lo= ongArch64/Synchronization.c
new file mode 100644
inde= x 0000000000..d696c8ce10
--- /dev/null
+++ b/MdePkg/L= ibrary/BaseSynchronizationLib/LoongArch64/Synchronization.c
=40= =40 -0,0 +1,233 =40=40
+/** =40file

+ LoongArch s= ynchronization functions.

+

+ Copyright (c) 2= 022, Loongson Technology Corporation Limited. All rights reserved.<BR&= gt;

+

+ SPDX-License-Identifier: BSD-2-Clause= -Patent

+

+**/

+

= +=23include <Library/DebugLib.h>

+

+UIN= T32

+E=46IAPI

+AsmInternalSyncCompareExchange= 16 (

+ IN volatile UINT32 *,

+ IN UINT64,
+ IN UINT64,

+ IN UINT64

+ );
+

+UINT32

+E=46IAPI

+= AsmInternalSyncCompareExchange32 (

+ IN volatile UINT32 *,<= /div>
+ IN UINT64,

+ IN UINT64

+ );
+

+UINT64

+E=46IAPI

+AsmInternalSyncCompareExchange64 (

+ IN volatile UINT64 = *,

+ IN UINT64,

+ IN UINT64

+ )= ;

+

+UINT32

+E=46IAPI

=
+AsmInternalSyncIncrement (

+ IN volatile UINT32 *
+ );

+

+UINT32

+E=46= IAPI

+AsmInternalSyncDecrement (

+ IN volatil= e UINT32 *

+ );

+

+/**
+ Performs an atomic compare exchange operation on a 16-bit
+ unsigned integer.

+

+ Performs an at= omic compare exchange operation on the 16-bit

+ unsigned in= teger specified by Value. If Value is equal to

+ CompareVal= ue, then Value is set to ExchangeValue and

+ CompareValue i= s returned. If Value is not equal to

+ CompareValue, then V= alue is returned. The compare exchange

+ operation must be = performed using MP safe mechanisms.

+

+ =40pa= ram=5Bin=5D Value A pointer to the 16-bit value for the

+ c= ompare exchange operation.

+ =40param=5Bin=5D CompareValue = 16-bit value used in compare operation.

+ =40param=5Bin=5D = ExchangeValue 16-bit value used in exchange operation.

+
+ =40return The original *Value before exchange.

+

+**/

+UINT16

+E=46IAPI
+InternalSyncCompareExchange16 (

+ IN volatile UI= NT16 *Value,

+ IN UINT16 CompareValue,

+ IN U= INT16 ExchangeValue

+ )

+=7B

+ = UINT32 RetValue;

+ UINT32 Shift;

+ UINT64 Mas= k;

+ UINT64 LocalCompareValue;

+ UINT64 Local= ExchangeValue;

+ volatile UINT32 *Ptr32;

+
+ /* Check that ptr is naturally aligned */

+ A= SSERT (=21((UINT64)Value & (sizeof (Value) - 1)));

+
+ /* Mask inputs to the correct size. */

+ Mask= =3D (((=7E0UL) - (1UL << (0)) + 1) & (=7E0UL >> (64 - 1 = - ((sizeof (UINT16) * 8) - 1))));

+ LocalCompareValue =3D (= (UINT64)CompareValue) & Mask;

+ LocalExchangeValue =3D = ((UINT64)ExchangeValue) & Mask;

+

+ /*
+ * Calculate a shift & mask that correspond to the value= we wish to

+ * compare & exchange within the naturally= aligned 4 byte integer

+ * that includes it.

+ */

+ Shift =3D (UINT64)Value & 0x3;

+ = Shift *=3D 8; /* BITS=5FPER=5FBYTE */

+ LocalCompareValue &= lt;<=3D Shift;

+ LocalExchangeValue <<=3D Shift;
+ Mask <<=3D Shift;

+

+ /*=

+ * Calculate a pointer to the naturally aligned 4 byte in= teger that

+ * includes our byte of interest, and load its = value.

+ */

+ Ptr32 =3D (UINT32 *)((UINT64)Va= lue & =7E0x3);

+

+ RetValue =3D AsmIntern= alSyncCompareExchange16 (

+ Ptr32,

+ Mask,
+ LocalCompareValue,

+ LocalExchangeValue
=
+ );

+

+ return (RetValue & Mask= ) >> Shift;

+=7D

+

+/**
+ Performs an atomic compare exchange operation on a 32-bit<= /div>
+ unsigned integer.

+

+ Perform= s an atomic compare exchange operation on the 32-bit

+ unsi= gned integer specified by Value. If Value is equal to

+ Com= pareValue, then Value is set to ExchangeValue and

+ Compare= Value is returned. If Value is not equal to

+ CompareValue,= then Value is returned. The compare exchange

+ operation m= ust be performed using MP safe mechanisms.

+

= + =40param=5Bin=5D Value A pointer to the 32-bit value for the

<= div>+ compare exchange operation.

+ =40param=5Bin=5D Compar= eValue 32-bit value used in compare operation.

+ =40param=5B= in=5D ExchangeValue 32-bit value used in exchange operation.

+

+ =40return The original *Value before exchange.
<= br>
+

+**/

+UINT32

+E=46IAP= I

+InternalSyncCompareExchange32 (

+ IN volat= ile UINT32 *Value,

+ IN UINT32 CompareValue,

= + IN UINT32 ExchangeValue

+ )

+=7B

<= div>+ UINT32 RetValue;

+

+ RetValue =3D AsmIn= ternalSyncCompareExchange32 (

+ Value,

+ Comp= areValue,

+ ExchangeValue

+ );

= +

+ return RetValue;

+=7D

+
+/**

+ Performs an atomic compare exchange opera= tion on a 64-bit unsigned integer.

+

+ Perfor= ms an atomic compare exchange operation on the 64-bit unsigned integer sp= ecified

+ by Value. If Value is equal to CompareValue, then= Value is set to ExchangeValue and

+ CompareValue is return= ed. If Value is not equal to CompareValue, then Value is returned.
<= br>
+ The compare exchange operation must be performed using MP safe = mechanisms.

+

+ =40param=5Bin=5D Value A poin= ter to the 64-bit value for the compare exchange

+ operatio= n.

+ =40param=5Bin=5D CompareValue 64-bit value used in com= pare operation.

+ =40param=5Bin=5D ExchangeValue 64-bit val= ue used in exchange operation.

+

+ =40return = The original *Value before exchange.

+

+**/
+UINT64

+E=46IAPI

+InternalSyncC= ompareExchange64 (

+ IN volatile UINT64 *Value,

+ IN UINT64 CompareValue,

+ IN UINT64 ExchangeValue
+ )

+=7B

+ UINT64 RetValue;
+

+ RetValue =3D AsmInternalSyncCompareExchange64 (<= /div>
+ Value,

+ CompareValue,

+ Exch= angeValue

+ );

+

+ return RetVa= lue;

+=7D

+

+/**

= + Performs an atomic increment of an 32-bit unsigned integer.

+

+ Performs an atomic increment of the 32-bit unsigned = integer specified by

+ Value and returns the incremented va= lue. The increment operation must be

+ performed using MP s= afe mechanisms. The state of the return value is not

+ guar= anteed to be MP safe.

+

+ =40param=5Bin=5D Va= lue A pointer to the 32-bit value to increment.

+

=
+ =40return The incremented value.

+

+**= /

+UINT32

+E=46IAPI

+InternalSy= ncIncrement (

+ IN volatile UINT32 *Value

+ )=

+=7B

+ return AsmInternalSyncIncrement (Valu= e);

+=7D

+

+/**

+= Performs an atomic decrement of an 32-bit unsigned integer.

+

+ Performs an atomic decrement of the 32-bit unsigned i= nteger specified by

+ Value and returns the decrement value= . The decrement operation must be

+ performed using MP safe= mechanisms. The state of the return value is not

+ guarant= eed to be MP safe.

+

+ =40param=5Bin=5D Value= A pointer to the 32-bit value to decrement.

+

+ =40return The decrement value.

+

+**/
+UINT32

+E=46IAPI

+InternalSyncDec= rement (

+ IN volatile UINT32 *Value

+ )
+=7B

+ return AsmInternalSyncDecrement (Value);
+=7D

--
2.27.0
--6336c049_33c64965_1b923--