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x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v1 07/12] ArmPkg: Fix return value for ArmGicV2AcknowledgeInterrupt To: Pedro Falcato Cc: devel@edk2.groups.io, ardb+tianocore@kernel.org, quic_llindhol@quicinc.com, neil.jones@blaize.com, pierre.gondois@arm.com, Matteo.Carlini@arm.com, Akanksha.Jain2@arm.com, Ben.Adderson@arm.com, Sibel.Allinson@arm.com, nd@arm.com References: <20230523130421.10804-1-sami.mujawar@arm.com> <20230523130421.10804-8-sami.mujawar@arm.com> From: "Sami Mujawar" In-Reply-To: X-ClientProxiedBy: LO4P265CA0066.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2af::9) To AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AS8PR08MB6806:EE_|PAWPR08MB10019:EE_|AM7EUR03FT004:EE_|DB5PR08MB10235:EE_ X-MS-Office365-Filtering-Correlation-Id: c15c6b92-6f91-4052-f0e0-08db5ba0e383 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 15:17:57.2245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c15c6b92-6f91-4052-f0e0-08db5ba0e383 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR08MB10235 Content-Type: multipart/alternative; boundary="------------auWVqPJaFveEmMngy5a0J8y0" --------------auWVqPJaFveEmMngy5a0J8y0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Pedro, Thank you for the feedback. Please see my response inline marked [SAMI]. Regards, Sami Mujawar On 23/05/2023 02:32 pm, Pedro Falcato wrote: > On Tue, May 23, 2023 at 2:04 PM Sami Mujawar wrote: >> The IAR register of the Gic CPU interface is 32 bit, while >> the value returned by ArmGicV2AcknowledgeInterrupt() is >> UINTN. Therefore, typecast the return value to UINTN before >> returning. > Since IAR is 32-bit, doesn't it make sense to return UINT32 here? Is > this for compatibility with GICv3 or...? [SAMI] IAR in GICv3 is 32-bit as well. I think this is done to keep compatibility with HARDWARE_INTERRUPT_SOURCE which is UINTN. >> Signed-off-by: Sami Mujawar >> --- >> ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c >> index f403bec367b5254c248e620e56471904e520f9f2..80115b243afabd5e4faad88089af738b19ce4cd1 100644 >> --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c >> +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c >> @@ -16,7 +16,7 @@ ArmGicV2AcknowledgeInterrupt ( >> ) >> { >> // Read the Interrupt Acknowledge Register >> - return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); >> + return (UINTN)MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); >> } > You don't need to cast from UINT32 to UINTN IMO. UINTN is, as far as I > know, always going to be at least 32-bits, so casting makes little > sense here, in my view, as UINTN >= UINT32. [SAMI] Ack. I will drop this patch. > --------------auWVqPJaFveEmMngy5a0J8y0 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit

Hi Pedro,

Thank you for the feedback.

Please see my response inline marked [SAMI].

Regards,

Sami Mujawar

On 23/05/2023 02:32 pm, Pedro Falcato wrote:
On Tue, May 23, 2023 at 2:04 PM Sami Mujawar <sami.mujawar@arm.com> wrote:

The IAR register of the Gic CPU interface is 32 bit, while
the value returned by ArmGicV2AcknowledgeInterrupt() is
UINTN. Therefore, typecast the return value to UINTN before
returning.

Since IAR is 32-bit, doesn't it make sense to return UINT32 here? Is
this for compatibility with GICv3 or...?

[SAMI] IAR in GICv3 is 32-bit as well. I think this is done to keep compatibility with HARDWARE_INTERRUPT_SOURCE which is UINTN.


      

        
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
 ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
index f403bec367b5254c248e620e56471904e520f9f2..80115b243afabd5e4faad88089af738b19ce4cd1 100644
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
@@ -16,7 +16,7 @@ ArmGicV2AcknowledgeInterrupt (
   )
 {
   // Read the Interrupt Acknowledge Register
-  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+  return (UINTN)MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
 }


      

      
You don't need to cast from UINT32 to UINTN IMO. UINTN is, as far as I
know, always going to be at least 32-bits, so casting makes little
sense here, in my view, as UINTN >= UINT32.

    

    [SAMI] Ack. I will drop this patch.

    

      



    

  


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