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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AM5PR0801MB2100.eurprd08.prod.outlook.com (2603:10a6:203:50::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Tue, 22 Jun 2021 15:10:16 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::5c0d:142c:27df:c52b]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::5c0d:142c:27df:c52b%5]) with mapi id 15.20.4242.023; Tue, 22 Jun 2021 15:10:16 +0000 Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 1/4] Silicon/ARM/NeoverseN1Soc: Add mem regions to support multi-chip usecase To: devel@edk2.groups.io, khasim.mohammed@arm.com, nd References: <20210602124701.18045-1-khasim.mohammed@arm.com> <20210602124701.18045-2-khasim.mohammed@arm.com> From: "Sami Mujawar" Message-ID: <9ec1ea69-e767-e7fb-c9ae-7d8a0a666be2@arm.com> Date: Tue, 22 Jun 2021 16:10:14 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2021 15:10:58.2954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05665d7b-31fd-4190-b8bb-08d9358ff09c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3453 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-GB Hi Khasim, I think this patch needs to be split. Also the commit message and the code changes look out of place. Can you fix this, please? From what I can see this patch includes the following changes: - Fixes the missing function documentation. Thank you for that, but this should be a separate patch. - Defines new PCDs and configures the memory map. Other than that one minor suggestion marked inline as [SAMI]. Regards, Sami Mujawar On 02/06/2021 01:46 PM, Khasim Mohammed via groups.io wrote: > This patch adds resource descriptor for multi-chip usecase and > introduces corresponding PCD definitions. > > Signed-off-by: Chandni Cherukuri > Signed-off-by: Khasim Syed Mohammed > --- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec |= 30 ++++++- > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf |= 28 ++++--- > Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |= 10 +-- > Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c |= 18 ++--- > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c |= 43 ++++++++-- > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |= 84 +++++++++++++++++--- > 6 files changed, 172 insertions(+), 41 deletions(-) > > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Ne= overseN1Soc/NeoverseN1Soc.dec > index 54b793a937ff..8789795bbae3 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -1,5 +1,7 @@ > +## @file > +# Describes the entire platform configuration. > # > -# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -33,8 +35,8 @@ [PcdsFixedAtBuild] > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 > - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x0= 0000008 > - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x0000= 0009 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00= 000008 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x000000= 09 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT3= 2|0x0000000A > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0= x0000000B > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT3= 2|0x0000000C > @@ -44,3 +46,25 @@ [PcdsFixedAtBuild] > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UIN= T64|0x00000010 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64= |0x00000011 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0= x00000012 > + > + # CCIX > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|U= INT32|0x00000019 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x000= 0001B > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x000000= 1C > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32= |0x00000001D > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x= 0000001E > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32= |0x00000001F > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x= 00000020 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x= 00000021 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|= 0x00000022 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT= 64|0x00000023 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|= 0x00000024 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x= 00000025 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x620= 00000|UINT32|0x00000026 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x000010= 00|UINT32|0x00000027 > + > + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64= |0x00000029 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.in= f b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 166c9e044483..8e2154aadf47 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -1,6 +1,7 @@ > ## @file > +# Platform Library for N1Sdp. > # > -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -29,13 +30,17 @@ [Sources.AARCH64] > AArch64/Helper.S | GCC > > [FixedPcd] > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > - > - gArmTokenSpaceGuid.PcdSystemMemoryBase > - gArmTokenSpaceGuid.PcdSystemMemorySize > - gArmTokenSpaceGuid.PcdArmPrimaryCore > - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > - > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base > @@ -45,7 +50,12 @@ [FixedPcd] > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize > > - gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > > [Guids] > gEfiHobListGuid ## CONSUMES ## SystemTable > diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/= ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > index 097160c7e2d1..309a5c627845 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > @@ -1,9 +1,9 @@ > /** @file > -* > -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > + > + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > **/ > > #ifndef NEOVERSEN1SOC_PLATFORM_H_ > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBr= idgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridg= eLib.c > index 9332939f63eb..ac88415fd24c 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib= .c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib= .c > @@ -1,10 +1,10 @@ > /** @file > -* PCI Host Bridge Library instance for ARM Neoverse N1 platform > -* > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > + PCI Host Bridge Library instance for ARM Neoverse N1 platform > + > + Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > **/ > > #include > @@ -96,7 +96,7 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { > /** > Return all the root bridge instances in an array. > > - @param Count Return the count of root bridge instances. > + @param Count Return the count of root bridge instances. > > @return All the root bridge instances in an array. > The array should be passed into PciHostBridgeFreeRootBridges(= ) > @@ -115,8 +115,8 @@ PciHostBridgeGetRootBridges ( > /** > Free the root bridge instances array returned from PciHostBridgeGetRo= otBridges(). > > - @param Bridges The root bridge instances array. > - @param Count The count of the array. > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > **/ > VOID > EFIAPI > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > index f722080e566b..d5ec0ff30d10 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > @@ -1,9 +1,9 @@ > /** @file > -* > -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > + > + Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > **/ > > #include > @@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { > { 0x1, 0x1 } // Cluster 1, Core 1 > }; > > +/** > + Return the current Boot Mode. > + > + This function returns the boot reason on the platform. > + > +**/ > EFI_BOOT_MODE > ArmPlatformGetBootMode ( > VOID > @@ -25,6 +31,15 @@ ArmPlatformGetBootMode ( > return BOOT_WITH_FULL_CONFIGURATION; > } > > +/** > + Initialize controllers that must be setup in the normal world. > + > + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pe= i/PlatformPeim > + in the PEI phase. > + > + @param[in] MpId Processor ID > + > +**/ > RETURN_STATUS > ArmPlatformInitialize ( > IN UINTN MpId > @@ -33,6 +48,15 @@ ArmPlatformInitialize ( > return RETURN_SUCCESS; > } > > +/** > + Populate the Platform core information. > + > + This function populates the ARM_MP_CORE_INFO_PPI with information abou= t the cores. > + > + @param[out] CoreCount Number of cores > + @param[out] ArmCoreTable Table containing information about the cor= es > + > +**/ > EFI_STATUS > PrePeiCoreGetMpCoreInfo ( > OUT UINTN *CoreCount, > @@ -56,6 +80,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { > } > }; > > +/** > + Return the Platform specific PPIs > + > + This function exposes the N1Sdp Specific PPIs. > + > + @param[out] PpiListSize Size in Bytes of the Platform PPI List > + @param[out] PpiList Platform PPI List > + > +**/ > VOID > ArmPlatformGetPlatformPpiList ( > OUT UINTN *PpiListSize, > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem= .c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index f9b3d037537d..ebdcf437599a 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -1,9 +1,9 @@ > /** @file > -* > -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > + > + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > **/ > > #include > @@ -13,7 +13,7 @@ > #include > > // The total number of descriptors, including the final "end-of-table" = descriptor. > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 > > /** > Returns the Virtual Memory Map of the platform. > @@ -21,21 +21,23 @@ > This Virtual Memory Map is used by MemoryInitPei Module to initialize= the MMU > on your platform. > > - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des= cribing > - a Physical-to-Virtual Memory mapping. Thi= s array > - must be ended by a zero-filled entry. > + @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR d= escribing > + a Physical-to-Virtual Memory mapping. T= his array > + must be ended by a zero-filled entry. > **/ > VOID > ArmPlatformGetVirtualMemoryMap ( > IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > ) > { > - UINTN Index =3D 0; > + UINTN Index; > ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT64 DramBlock2Size; > + UINT64 RemoteDdrSize; > > + Index =3D 0; > PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUC= T_BASE; > DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - > NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB)= * > @@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap ( > FixedPcdGet64 (PcdDramBlock2Base), > DramBlock2Size); > > + if (PlatInfo->MultichipMode =3D=3D 1) { > + RemoteDdrSize =3D ((PlatInfo->RemoteDdrSize - 2) * 1024UL * 1024UL *= 1024UL); [SAMI] Can SIZE_1GB be used instead of 1024UL*...? > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemory= Base), > + PcdGet64 (PcdSystemMemorySize) > + ); > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Ba= se), > + RemoteDdrSize > + ); > + } > + > ASSERT (VirtualMemoryMap !=3D NULL); > Index =3D 0; > > @@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64= Size); > VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE; > > + // CCIX RC Configuration Space > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixRootPor= tConfigBaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixRootPor= tConfigBaseAddress); > + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixRootPor= tConfigBaseSize); > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; > + > + // CCIX ECAM Configuration Space > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixExpress= BaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixExpress= BaseAddress); > + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdCcixB= usMax) - > + FixedPcdGet32 (PcdCcixBus= Min) + 1) * > + SIZE_1MB; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; > + > + // CCIX MMIO32 Memory Space > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixMmio32B= ase); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixMmio32B= ase); > + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixMmio32S= ize); > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; > + > + // CCIX MMIO64 Memory Space > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdCcixMmio64B= ase); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdCcixMmio64B= ase); > + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdCcixMmio64S= ize); > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; > + > // SubSystem Pheripherals - UART0 > VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BAS= E; > VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BAS= E; > @@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIP= H_BASE0_SZ; > VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE; > > + if (PlatInfo->MultichipMode =3D=3D 1) { > + //Remote DDR (2GB) > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemory= Space) + > + PcdGet64 (PcdSystemMemor= yBase); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemory= Space) + > + PcdGet64 (PcdSystemMemor= yBase); > + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMem= orySize); > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTR= IBUTE_WRITE_THROUGH; > + > + //Remote DDR > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemory= Space) + > + PcdGet64 (PcdDramBlock2B= ase); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemory= Space) + > + PcdGet64 (PcdDramBlock2B= ase); > + VirtualMemoryTable[Index].Length =3D RemoteDdrSize; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTR= IBUTE_WRITE_THROUGH; > + } > + > // End of Table > VirtualMemoryTable[++Index].PhysicalBase =3D 0; > VirtualMemoryTable[Index].VirtualBase =3D 0; IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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