From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.431.1649264644096687714 for ; Wed, 06 Apr 2022 10:04:05 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=WesRUT3H; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: ted.kuo@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649264645; x=1680800645; h=from:to:cc:subject:date:message-id; bh=aklANU9FbpqmQMFCNZRulggtXQFiQUnAtQu1xDBYRq0=; b=WesRUT3HWFXnAK248FGtyVM3UyhhLaGqoHlYDk8183Kq88tAdoJPlHIK PrcxVOhzW2A2l20ZRhDXPcDA/9kjqZ2g4oAMMalaJPHIlq396fL6zzD6l 1wigqyQOeOLqd94QC3I/0hzVsx+lPGMtmPxP1f4LC/JlTga4noJ2RYtHV 0IUD9ZlDo3Cmpl8avcZ3WXAGb/qjKNvy08cN2Ntfmz2mcfLCQCZfoLefw zVs4n4x4nhw2zeQoFglbzrLyahXc1WZI48za8G9uolDQTJD3pMLVdhjet rdRLQCz7rBWVGuNBriUr60ezFlzIQY/5Z1EELKLITf/bNvqWtvo7w/yR/ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="347548612" X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="347548612" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:02:58 -0700 X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="642137751" Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:02:56 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH v3 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64 Date: Thu, 7 Apr 2022 01:02:34 +0800 Message-Id: <9f8e6d30d79f5a3fbaa198eef91fdc70c151659e.1649264447.git.ted.kuo@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: References: In-Reply-To: References: REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support both IA32 and X64. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- IntelFsp2Pkg/Include/FspGlobalData.h | 51 +++++++++++++++++++++++++----------- 2 files changed, 37 insertions(+), 16 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 85fbc7664c..1ead3c9ce6 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -130,7 +130,7 @@ FspGlobalDataInit ( ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA)); PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE; - PeiFspData->Version = 0; + PeiFspData->Version = FSP_GLOBAL_DATA_VERSION; PeiFspData->CoreStack = BootLoaderStack; PeiFspData->PerfIdx = 2; PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE; diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h index 2b534075ae..dcfeed7501 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -10,8 +10,9 @@ #include -#define FSP_IN_API_MODE 0 -#define FSP_IN_DISPATCH_MODE 1 +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 +#define FSP_GLOBAL_DATA_VERSION 1 #pragma pack(1) @@ -28,10 +29,11 @@ typedef enum { typedef struct { VOID *DataPtr; - UINT32 MicrocodeRegionBase; - UINT32 MicrocodeRegionSize; - UINT32 CodeRegionBase; - UINT32 CodeRegionSize; + UINTN MicrocodeRegionBase; + UINTN MicrocodeRegionSize; + UINTN CodeRegionBase; + UINTN CodeRegionSize; + UINTN Reserved; } FSP_PLAT_DATA; #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') @@ -42,15 +44,15 @@ typedef struct { UINT32 Signature; UINT8 Version; UINT8 Reserved1[3]; + /// + /// Offset 0x08 + /// UINTN CoreStack; + UINTN Reserved2; + /// + /// IA32: Offset 0x10; X64: Offset 0x18 + /// UINT32 StatusCode; - UINT32 Reserved2[8]; - FSP_PLAT_DATA PlatformData; - FSP_INFO_HEADER *FspInfoHeader; - VOID *UpdDataPtr; - VOID *TempRamInitUpdPtr; - VOID *MemoryInitUpdPtr; - VOID *SiliconInitUpdPtr; UINT8 ApiIdx; /// /// 0: FSP in API mode; 1: FSP in DISPATCH mode @@ -60,15 +62,34 @@ typedef struct { UINT8 Reserved3; UINT32 NumberOfPhases; UINT32 PhasesExecuted; + UINT32 Reserved4[8]; /// + /// IA32: Offset 0x40; X64: Offset 0x48 + /// Start of UINTN and pointer section + /// All UINTN and pointer members must be put in this section + /// except CoreStack and Reserved2. In addition, the number of + /// UINTN and pointer members must be even for natural alignment + /// in both IA32 and X64. + /// + FSP_PLAT_DATA PlatformData; + VOID *TempRamInitUpdPtr; + VOID *MemoryInitUpdPtr; + VOID *SiliconInitUpdPtr; + /// + /// IA32: Offset 0x64; X64: Offset 0x90 /// To store function parameters pointer /// so it can be retrieved after stack switched. /// VOID *FunctionParameterPtr; - UINT8 Reserved4[16]; + FSP_INFO_HEADER *FspInfoHeader; + VOID *UpdDataPtr; + /// + /// End of UINTN and pointer section + /// + UINT8 Reserved5[16]; UINT32 PerfSig; UINT16 PerfLen; - UINT16 Reserved5; + UINT16 Reserved6; UINT32 PerfIdx; UINT64 PerfData[32]; } FSP_GLOBAL_DATA; -- 2.16.2.windows.1