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Fri, 25 Feb 2022 20:43:42 -0800 From: "Ashish Singhal" To: , , , , CC: Ashish Singhal Subject: [PATCH v2] ArmPkg: Invalidate Instruction Cache On MMU Enable Date: Fri, 25 Feb 2022 21:43:37 -0700 Message-ID: <9f95ba0bb19fd034af27f4f564e5eeff0ec19fff.1645850486.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 99cfcc16-c4ef-479a-7d2d-08d9f8e29238 X-MS-TrafficTypeDiagnostic: BL0PR12MB4674:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IZC+uiRFOaH9sjlZZ9xIBUnwIDzDgtj5LzODOjE+WCN8wTO2+O+zkYx0e6loqKfhrldmcbl6M7jhgnOYTBVgSRielQqpC1aQdLqgLujyvxEn1Kkz1Yw4+2681Zl28lwV1DJbEGDXrZ9i7uOl8QcPC2Nsgs2Hhh8d1e+DVlH3v/ggbVA8mEw8HyBQDA5NbfQkNiKwkWHCS49X664/xv/XqSkNR5LfaLsOM2VLaqraCZExzVpe/1MgMQp1gt1p1xOIxBNvmR9zAvo5YmUhl8NrUoGVBEKXO+FpxRGDlUvUFiFPvOmO1y+nQChUCVTchOoaHG9BG7u1xqqCq938Hrs/abvop8IOzVSzGGQwl8qF0MSCqrBV4pLNHGUj4g9AfaBOoeJmaPljErq3DNSDSMKJzuHdH1DSlm+WNCI5N4aVb2xjvJ6UmxV33wWPjY1eg0fMMaSf/7Rtvb56pVyd2xOoj54Z9omGSumGEsPc72AQLdzE4F9I7eMXkBRKIYKJExStYZdLuSjRtmNQLSYa/KiQzgdZyYYD6gpZ/FUplHWrdZdavIrWpEdYh1HHcMtlHxVQ4JPxZe0SBVi8SLh/HIRzcdg6eGmFO8nUHK8SYsfI9VC9IWGMXQM4qwxYNv++Ch17/EzafFZVcaGzhg+4DvR57dc4agNN84hv+TDWPEcgMm086/uH9i2lnA1HD0vooOzLB3lc7GmLbxi+8V5X+LTOzQ== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(5660300002)(2616005)(107886003)(8936002)(83380400001)(40460700003)(4326008)(508600001)(36756003)(26005)(186003)(6666004)(7696005)(8676002)(86362001)(82310400004)(356005)(81166007)(316002)(426003)(336012)(47076005)(36860700001)(70586007)(70206006)(19627235002)(2906002)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2022 04:43:44.8015 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99cfcc16-c4ef-479a-7d2d-08d9f8e29238 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4674 Content-Type: text/plain Even with MMU turned off, instruction cache can speculate and fetch instructions. This can cause a crash if region being executed has been modified recently. With this patch, we ensure that instruction cache is invalidated right after MMU has been enabled and any potentially stale instruction fetched earlier has been discarded. This is specially helpful when the memory attributes of a region in MMU are being changed and some instructions operating on the region are prefetched in the instruction cache. Signed-off-by: Ashish Singhal --- ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 4 +++- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index d3cc1e8671..047192ec91 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -89,7 +89,9 @@ ASM_FUNC(ArmEnableMmu) dsb nsh isb msr sctlr_el3, x0 // Write back -4: isb +4: ic iallu + dsb nsh + isb ret diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S index 66ebca571e..4fe75ec841 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S @@ -37,6 +37,8 @@ // re-enable the MMU msr sctlr_el\el, x8 + ic iallu + dsb nsh isb .endm -- 2.17.1