From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web10.4207.1663907844120356571 for ; Thu, 22 Sep 2022 21:37:25 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxTWv+Ny1j6XsgAA--.60358S2; Fri, 23 Sep 2022 12:37:18 +0800 (CST) Date: Fri, 23 Sep 2022 12:37:18 +0800 From: "Chao Li" To: Michael D Kinney Cc: Liming Gao , Zhiguang Liu , Baoqi Zhang , "=?utf-8?Q?devel=40edk2.groups.io?=" Message-ID: In-Reply-To: <20220914094111.3696725-1-lichao@loongson.cn> References: <20220914094111.3696725-1-lichao@loongson.cn> Subject: Re: [PATCH v2 23/34] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxTWv+Ny1j6XsgAA--.60358S2 X-Coremail-Antispam: 1UD129KBjvAXoWfGw4kWr1xGFy5Gw45ZrWfAFb_yoW8WF15Go WUZrn7uw4UAr18ArykZrsxJr12qr1xWF45Jr40gFy8GF45t3WDGr4DJw18Gw13GF98GFn8 G34UJws7ta9rtr18n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYN7k0a2IF6w4kM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0 x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj4 1l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0 I7IYx2IY6xkF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwV C2z280aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40Eb7x2 x7xS6r1j6r4UMc02F40EFcxC0VAKzVAqx4xG6I80ewAqx4xG64kEw2xG04xIwI0_Xr0_Wr 1lYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkE bVWUJVW8JwACjcxG0xvY0x0EwIxGrwCjr7xvwVCIw2I0I7xG6c02F41lc2xSY4AK6svPMx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_JrI_ JrWlx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8 JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU5CiiDUUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQASCGMsUF0RcwAAs7 Content-Type: multipart/alternative; boundary="632d37fe_4b94f0ec_dbe1" --632d37fe_4b94f0ec_dbe1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, In the V2, I removed the unaligned read/write functions in LoongArch libr= ary and used the generic implementation, can you review it again=3F Thanks, Chao -------- On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao Li wrote: > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > Add LoongArch LOONGARCH64 BaseLib functions. > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > > Signed-off-by: Chao Li > Co-authored-by: Baoqi Zhang > --- > MdePkg/Include/Library/BaseLib.h =7C 24 ++++++++ > MdePkg/Library/BaseLib/BaseLib.inf =7C 16 ++++- > MdePkg/Library/BaseLib/LoongArch64/Barrier.S =7C 28 +++++++++ > .../BaseLib/LoongArch64/CpuBreakpoint.S =7C 24 ++++++++ > MdePkg/Library/BaseLib/LoongArch64/CpuPause.S =7C 31 ++++++++++ > .../BaseLib/LoongArch64/DisableInterrupts.S =7C 21 +++++++ > .../BaseLib/LoongArch64/EnableInterrupts.S =7C 21 +++++++ > .../BaseLib/LoongArch64/GetInterruptState.S =7C 35 +++++++++++ > .../BaseLib/LoongArch64/InternalSwitchStack.c =7C 58 ++++++++++++++++++= + > .../Library/BaseLib/LoongArch64/Memory=46ence.S =7C 18 ++++++ > .../BaseLib/LoongArch64/SetJumpLongJump.S =7C 49 ++++++++++++++++ > .../Library/BaseLib/LoongArch64/SwitchStack.S =7C 39 +++++++++++++ > 12 files changed, 363 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Barrier.S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts= .S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.= S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/GetInterruptState= .S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/InternalSwitchSta= ck.c > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Memory=46ence.S > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S= > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S > > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/= BaseLib.h > index a6f9a194ef..f3f59f21c2 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > =40=40 -6,6 +6,7 =40=40 Copyright (c) 2006 - 2021, Intel Corporation. A= ll rights reserved.
> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= > > Copyright (c) Microsoft Corporation.
> Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.
> +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All rights reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > =40=40 -152,6 +153,29 =40=40 typedef struct =7B > > =23endif // defined (MDE=5FCPU=5FRISCV64) > > > +=23if defined (MDE=5FCPU=5FLOONGARCH64) > +/// > +/// The LoongArch architecture context buffer used by SetJump() and Lo= ngJump() > +/// > +typedef struct =7B > + UINT64 S0; > + UINT64 S1; > + UINT64 S2; > + UINT64 S3; > + UINT64 S4; > + UINT64 S5; > + UINT64 S6; > + UINT64 S7; > + UINT64 S8; > + UINT64 SP; > + UINT64 =46P; > + UINT64 RA; > +=7D BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER; > + > +=23define BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER=5FALIGNMENT 8 > + > +=23endif // defined (MDE=5FCPU=5FLOONGARCH64) > + > // > // String Services > // > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLi= b/BaseLib.inf > index 6be5be9428..9ed46a584a 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > =40=40 -21,7 +21,7 =40=40 > LIBRARY=5FCLASS =3D BaseLib > > > > =23 > -=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 > +=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOONGAR= CH64 > =23 > > > =5BSources=5D > =40=40 -402,6 +402,20 =40=40 > RiscV64/RiscVInterrupt.S =7C GCC > > RiscV64/=46lushCache.S =7C GCC > > > +=5BSources.LOONGARCH64=5D > + Math64.c > + Unaligned.c > + LoongArch64/InternalSwitchStack.c > + LoongArch64/GetInterruptState.S =7C GCC > + LoongArch64/EnableInterrupts.S =7C GCC > + LoongArch64/DisableInterrupts.S =7C GCC > + LoongArch64/Barrier.S =7C GCC > + LoongArch64/Memory=46ence.S =7C GCC > + LoongArch64/CpuBreakpoint.S =7C GCC > + LoongArch64/CpuPause.S =7C GCC > + LoongArch64/SetJumpLongJump.S =7C GCC > + LoongArch64/SwitchStack.S =7C GCC > + > =5BPackages=5D > MdePkg/MdePkg.dec > > > diff --git a/MdePkg/Library/BaseLib/LoongArch64/Barrier.S b/MdePkg/Libr= ary/BaseLib/LoongArch64/Barrier.S > new file mode 100644 > index 0000000000..58f21ad725 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S > =40=40 -0,0 +1,28 =40=40 > +=23-------------------------------------------------------------------= ----------- > +=23 > +=23 LoongArch Barrier Operations > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(AsmDataBarrierLoongArch) > +ASM=5FGLOBAL ASM=5FP=46X(AsmInstructionBarrierLoongArch) > + > +=23 > +=23 Data barrier operation for LoongArch. > +=23 > +ASM=5FP=46X(AsmDataBarrierLoongArch): > + dbar 0 > + jirl =24zero, =24ra, 0 > + > +=23 > +=23 Instruction barrier operation for LoongArch. > +=23 > +ASM=5FP=46X(AsmInstructionBarrierLoongArch): > + ibar 0 > + jirl =24zero, =24ra, 0 > + > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S b/MdePk= g/Library/BaseLib/LoongArch64/CpuBreakpoint.S > new file mode 100644 > index 0000000000..4e022e9bb5 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S > =40=40 -0,0 +1,24 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 CpuBreakpoint for LoongArch > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(CpuBreakpoint) > + > +=23/** > +=23 Generates a breakpoint on the CPU. > +=23 > +=23 Generates a breakpoint on the CPU. The breakpoint must be implemen= ted such > +=23 that code can resume normal execution after the breakpoint. > +=23 > +=23**/ > + > +ASM=5FP=46X(CpuBreakpoint): > + break 3 > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Lib= rary/BaseLib/LoongArch64/CpuPause.S > new file mode 100644 > index 0000000000..e9140e8742 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S > =40=40 -0,0 +1,31 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 CpuPause for LoongArch > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(CpuPause) > + > +=23/** > +=23 Requests CPU to pause for a short period of time. > +=23 > +=23 Requests CPU to pause for a short period of time. Typically used i= n MP > +=23 systems to prevent memory starvation while waiting for a spin lock= . > +=23 > +=23**/ > + > +ASM=5FP=46X(CpuPause): > + nop > + nop > + nop > + nop > + nop > + nop > + nop > + nop > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/M= dePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S > new file mode 100644 > index 0000000000..0f228339af > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S > =40=40 -0,0 +1,21 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 LoongArch interrupt disable > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(DisableInterrupts) > + > +=23/** > +=23 Disables CPU interrupts. > +=23**/ > + > +ASM=5FP=46X(DisableInterrupts): > + li.w =24t0, 0x4 > + csrxchg =24zero, =24t0, 0x0 > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/Md= ePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S > new file mode 100644 > index 0000000000..3c34fb2cdd > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S > =40=40 -0,0 +1,21 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 LoongArch interrupt enable > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(EnableInterrupts) > + > +=23/** > +=23 Enables CPU interrupts. > +=23**/ > + > +ASM=5FP=46X(EnableInterrupts): > + li.w =24t0, 0x4 > + csrxchg =24t0, =24t0, 0x0 > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S b/M= dePkg/Library/BaseLib/LoongArch64/GetInterruptState.S > new file mode 100644 > index 0000000000..bfd1f2d5f7 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S > =40=40 -0,0 +1,35 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 Get LoongArch interrupt status > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(GetInterruptState) > + > +=23/** > +=23 Retrieves the current CPU interrupt state. > +=23 > +=23 Returns TRUE means interrupts are currently enabled. Otherwise, > +=23 returns =46ALSE. > +=23 > +=23 =40retval TRUE CPU interrupts are enabled. > +=23 =40retval =46ALSE CPU interrupts are disabled. > +=23 > +=23**/ > + > +ASM=5FP=46X(GetInterruptState): > + li.w =24t1, 0x4 > + csrrd =24t0, 0x0 > + and =24t0, =24t0, =24t1 > + beqz =24t0, 1f > + li.w =24a0, 0x1 > + b 2f > +1: > + li.w =24a0, 0x0 > +2: > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c b= /MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c > new file mode 100644 > index 0000000000..859bc96329 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c > =40=40 -0,0 +1,58 =40=40 > +/** =40file > > + SwitchStack() function for LoongArch. > + > + Copyright (c) 2022, Loongson Technology Corporation Limited. All righ= ts reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +=23include =22BaseLibInternals.h=22 > + > +UINTN > +E=46IAPI > +InternalSwitchStackAsm ( > + IN BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER *JumpBuffer > + ); > + > +/** > + Transfers control to a function starting with a new stack. > + > + Transfers control to the function specified by EntryPoint using the > + new stack specified by NewStack and passing in the parameters specifi= ed > + by Context1 and Context2. Context1 and Context2 are optional and may > + be NULL. The function EntryPoint must never return. > + > + If EntryPoint is NULL, then ASSERT(). > + If NewStack is NULL, then ASSERT(). > + > + =40param=5Bin=5D EntryPoint A pointer to function to call with the ne= w stack. > + =40param=5Bin=5D Context1 A pointer to the context to pass into the E= ntryPoint > + function. > + =40param=5Bin=5D Context2 A pointer to the context to pass into the E= ntryPoint > + function. > + =40param=5Bin=5D NewStack A pointer to the new stack to use for the E= ntryPoint > + function. > + =40param=5Bin=5D Marker VA=5FLIST marker for the variable argument li= st. > + > +**/ > +VOID > +E=46IAPI > +InternalSwitchStack ( > + IN SWITCH=5FSTACK=5FENTRY=5FPOINT EntryPoint, > + IN VOID *Context1 OPTIONAL, > + IN VOID *Context2 OPTIONAL, > + IN VOID *NewStack, > + IN VA=5FLIST Marker > + ) > + > +=7B > + BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER JumpBuffer; > + > + JumpBuffer.RA =3D (UINTN)EntryPoint; > + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *); > + JumpBuffer.SP -=3D sizeof (Context1) + sizeof (Context2); > + ((VOID **)(UINTN)JumpBuffer.SP)=5B0=5D =3D Context1; > + ((VOID **)(UINTN)JumpBuffer.SP)=5B1=5D =3D Context2; > + > + InternalSwitchStackAsm (&JumpBuffer); > +=7D > diff --git a/MdePkg/Library/BaseLib/LoongArch64/Memory=46ence.S b/MdePk= g/Library/BaseLib/LoongArch64/Memory=46ence.S > new file mode 100644 > index 0000000000..2b3d34366f > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/Memory=46ence.S > =40=40 -0,0 +1,18 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 Memory=46ence() for LoongArch > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(Memory=46ence) > + > +=23 > +=23 Memory fence for LoongArch > +=23 > +ASM=5FP=46X(Memory=46ence): > + b AsmDataBarrierLoongArch > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S b/Mde= Pkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S > new file mode 100644 > index 0000000000..1c6ee54b6f > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S > =40=40 -0,0 +1,49 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 Set/Long jump for LoongArch > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +=23define STORE st.d /* 64 bit mode regsave instruction */ > +=23define LOAD ld.d /* 64 bit mode regload instruction */ > +=23define RSIZE 8 /* 64 bit mode register size */ > + > +ASM=5FGLOBAL ASM=5FP=46X(SetJump) > +ASM=5FGLOBAL ASM=5FP=46X(InternalLongJump) > + > +ASM=5FP=46X(SetJump): > + STORE =24s0, =24a0, RSIZE * 0 > + STORE =24s1, =24a0, RSIZE * 1 > + STORE =24s2, =24a0, RSIZE * 2 > + STORE =24s3, =24a0, RSIZE * 3 > + STORE =24s4, =24a0, RSIZE * 4 > + STORE =24s5, =24a0, RSIZE * 5 > + STORE =24s6, =24a0, RSIZE * 6 > + STORE =24s7, =24a0, RSIZE * 7 > + STORE =24s8, =24a0, RSIZE * 8 > + STORE =24sp, =24a0, RSIZE * 9 > + STORE =24fp, =24a0, RSIZE * 10 > + STORE =24ra, =24a0, RSIZE * 11 > + li.w =24a0, 0 =23 Setjmp return > + jirl =24zero, =24ra, 0 > + > +ASM=5FP=46X(InternalLongJump): > + LOAD =24ra, =24a0, RSIZE * 11 > + LOAD =24s0, =24a0, RSIZE * 0 > + LOAD =24s1, =24a0, RSIZE * 1 > + LOAD =24s2, =24a0, RSIZE * 2 > + LOAD =24s3, =24a0, RSIZE * 3 > + LOAD =24s4, =24a0, RSIZE * 4 > + LOAD =24s5, =24a0, RSIZE * 5 > + LOAD =24s6, =24a0, RSIZE * 6 > + LOAD =24s7, =24a0, RSIZE * 7 > + LOAD =24s8, =24a0, RSIZE * 8 > + LOAD =24sp, =24a0, RSIZE * 9 > + LOAD =24fp, =24a0, RSIZE * 10 > + move =24a0, =24a1 > + jirl =24zero, =24ra, 0 > + .end > diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S b/MdePkg/= Library/BaseLib/LoongArch64/SwitchStack.S > new file mode 100644 > index 0000000000..ad9aa8b343 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S > =40=40 -0,0 +1,39 =40=40 > +=23-------------------------------------------------------------------= ----------- > > +=23 > +=23 InternalSwitchStackAsm for LoongArch > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +=23define STORE st.d /* 64 bit mode regsave instruction */ > +=23define LOAD ld.d /* 64 bit mode regload instruction */ > +=23define RSIZE 8 /* 64 bit mode register size */ > + > +ASM=5FGLOBAL ASM=5FP=46X(InternalSwitchStackAsm) > + > +/** > + This allows the caller to switch the stack and goes to the new entry = point > + > + =40param JumpBuffer A pointer to CPU context buffer. > +**/ > + > +ASM=5FP=46X(InternalSwitchStackAsm): > + LOAD =24ra, =24a0, RSIZE * 11 > + LOAD =24s0, =24a0, RSIZE * 0 > + LOAD =24s1, =24a0, RSIZE * 1 > + LOAD =24s2, =24a0, RSIZE * 2 > + LOAD =24s3, =24a0, RSIZE * 3 > + LOAD =24s4, =24a0, RSIZE * 4 > + LOAD =24s5, =24a0, RSIZE * 5 > + LOAD =24s6, =24a0, RSIZE * 6 > + LOAD =24s7, =24a0, RSIZE * 7 > + LOAD =24s8, =24a0, RSIZE * 8 > + LOAD =24sp, =24a0, RSIZE * 9 > + LOAD =24fp, =24a0, RSIZE * 10 > + LOAD =24a0, =24sp, 0 > + LOAD =24a1, =24sp, 8 > + jirl =24zero, =24ra, 0 > + .end > -- > 2.27.0 > --632d37fe_4b94f0ec_dbe1 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike,
In the V2, I removed the unaligned read/write fun= ctions in LoongArch library and used the generic implementation, can you = review it again=3F


Thanks,
Chao
= --------

On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao= Li <lichao=40loongson.cn> wrote:
RE=46:= https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053

= Add LoongArch LOONGARCH64 BaseLib functions.

Cc: Michael D = Kinney <michael.d.kinney=40intel.com>
Cc: Liming Gao <= gaoliming=40byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.li= u=40intel.com>

Signed-off-by: Chao Li <lichao=40loong= son.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi=40loongso= n.cn>
---
MdePkg/Include/Library/BaseLib.h =7C 24 = ++++++++
MdePkg/Library/BaseLib/BaseLib.inf =7C 16 ++++-
<= div>MdePkg/Library/BaseLib/LoongArch64/Barrier.S =7C 28 +++++++++
.../BaseLib/LoongArch64/CpuBreakpoint.S =7C 24 ++++++++
MdeP= kg/Library/BaseLib/LoongArch64/CpuPause.S =7C 31 ++++++++++
...= /BaseLib/LoongArch64/DisableInterrupts.S =7C 21 +++++++
.../Bas= eLib/LoongArch64/EnableInterrupts.S =7C 21 +++++++
.../BaseLib/= LoongArch64/GetInterruptState.S =7C 35 +++++++++++
.../BaseLib/= LoongArch64/InternalSwitchStack.c =7C 58 +++++++++++++++++++
..= ./Library/BaseLib/LoongArch64/Memory=46ence.S =7C 18 ++++++
...= /BaseLib/LoongArch64/SetJumpLongJump.S =7C 49 ++++++++++++++++
= .../Library/BaseLib/LoongArch64/SwitchStack.S =7C 39 +++++++++++++
<= div>12 files changed, 363 insertions(+), 1 deletion(-)
create m= ode 100644 MdePkg/Library/BaseLib/LoongArch64/Barrier.S
create = mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
= create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts= .S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Enable= Interrupts.S
create mode 100644 MdePkg/Library/BaseLib/LoongArc= h64/GetInterruptState.S
create mode 100644 MdePkg/Library/BaseL= ib/LoongArch64/InternalSwitchStack.c
create mode 100644 MdePkg/= Library/BaseLib/LoongArch64/Memory=46ence.S
create mode 100644 = MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
create mod= e 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S

d= iff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Bas= eLib.h
index a6f9a194ef..f3f59f21c2 100644
--- a/MdeP= kg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseL= ib.h
=40=40 -6,6 +6,7 =40=40 Copyright (c) 2006 - 2021, Intel C= orporation. All rights reserved.<BR>
Portions copyright (= c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

C= opyright (c) Microsoft Corporation.<BR>

Portions Copy= right (c) 2020, Hewlett Packard Enterprise Development LP. All rights res= erved.<BR>

+Portions Copyright (c) 2022, Loongson Tec= hnology Corporation Limited. All rights reserved.<BR>


=
SPDX-License-Identifier: BSD-2-Clause-Patent



=40=40 -152,6 +153,29 =40=40 typedef struct =7B

=23e= ndif // defined (MDE=5FCPU=5FRISCV64)



+=23if define= d (MDE=5FCPU=5FLOONGARCH64)

+///

+/// The Loo= ngArch architecture context buffer used by SetJump() and LongJump()
=
+///

+typedef struct =7B

+ UINT64 S0= ;

+ UINT64 S1;

+ UINT64 S2;

+ U= INT64 S3;

+ UINT64 S4;

+ UINT64 S5;

=
+ UINT64 S6;

+ UINT64 S7;

+ UINT64 S8;
+ UINT64 SP;

+ UINT64 =46P;

+ UI= NT64 RA;

+=7D BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER;

=
+

+=23define BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER=5FALIG= NMENT 8

+

+=23endif // defined (MDE=5FCPU=5FL= OONGARCH64)

+

//

// String Serv= ices

//

diff --git a/MdePkg/Library/BaseLib/B= aseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 6be5be942= 8..9ed46a584a 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
=40=40 -21,7 = +21,7 =40=40
LIBRARY=5FCLASS =3D BaseLib



= =23

-=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64= RISCV64

+=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AA= RCH64 RISCV64 LOONGARCH64

=23



=5BSour= ces=5D

=40=40 -402,6 +402,20 =40=40
RiscV64/RiscV= Interrupt.S =7C GCC

RiscV64/=46lushCache.S =7C GCC


+=5BSources.LOONGARCH64=5D

+ Math64.c
+ Unaligned.c

+ LoongArch64/InternalSwitchStack.c
+ LoongArch64/GetInterruptState.S =7C GCC

+ Loo= ngArch64/EnableInterrupts.S =7C GCC

+ LoongArch64/DisableIn= terrupts.S =7C GCC

+ LoongArch64/Barrier.S =7C GCC
+ LoongArch64/Memory=46ence.S =7C GCC

+ LoongArch64/C= puBreakpoint.S =7C GCC

+ LoongArch64/CpuPause.S =7C GCC
+ LoongArch64/SetJumpLongJump.S =7C GCC

+ LoongA= rch64/SwitchStack.S =7C GCC

+

=5BPackages=5D<= /div>
MdePkg/MdePkg.dec



diff --git a/MdePkg= /Library/BaseLib/LoongArch64/Barrier.S b/MdePkg/Library/BaseLib/LoongArch= 64/Barrier.S
new file mode 100644
index 0000000000..5= 8f21ad725
--- /dev/null
+++ b/MdePkg/Library/BaseLib/= LoongArch64/Barrier.S
=40=40 -0,0 +1,28 =40=40
+=23--= -------------------------------------------------------------------------= ---
+=23
+=23 LoongArch Barrier Operations
= +=23
+=23 Copyright (c) 2022, Loongson Technology Corporation L= imited. All rights reserved.<BR>
+=23
+=23 SPDX= -License-Identifier: BSD-2-Clause-Patent
+=23
+=23---= -------------------------------------------------------------------------= --
+
+ASM=5FGLOBAL ASM=5FP=46X(AsmDataBarrierLoongArc= h)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInstructionBarrierLoongArch)
+
+=23
+=23 Data barrier operation for LoongA= rch.
+=23
+ASM=5FP=46X(AsmDataBarrierLoongArch):
+ dbar 0
+ jirl =24zero, =24ra, 0
+
+= =23
+=23 Instruction barrier operation for LoongArch.
+=23
+ASM=5FP=46X(AsmInstructionBarrierLoongArch):
+= ibar 0
+ jirl =24zero, =24ra, 0
+
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S = b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
new file m= ode 100644
index 0000000000..4e022e9bb5
--- /dev/null=
+++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
=
=40=40 -0,0 +1,24 =40=40
+=23-----------------------------= -------------------------------------------------

+=23
+=23 CpuBreakpoint for LoongArch

+=23

+=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.<BR>

+=23

+=23 SPDX-Lic= ense-Identifier: BSD-2-Clause-Patent

+=23

+=23= -------------------------------------------------------------------------= -----

+

+ASM=5FGLOBAL ASM=5FP=46X(CpuBreakpoi= nt)

+

+=23/**

+=23 Generates a = breakpoint on the CPU.

+=23

+=23 Generates a = breakpoint on the CPU. The breakpoint must be implemented such

<= div>+=23 that code can resume normal execution after the breakpoint.
+=23

+=23**/

+

+ASM=5F= P=46X(CpuBreakpoint):

+ break 3

+ jirl =24zer= o, =24ra, 0

+ .end

diff --git a/MdePkg/Librar= y/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Library/BaseLib/LoongArch64/Cpu= Pause.S
new file mode 100644
index 0000000000..e9140e= 8742
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Loong= Arch64/CpuPause.S
=40=40 -0,0 +1,31 =40=40
+=23------= ------------------------------------------------------------------------<= /div>
+=23

+=23 CpuPause for LoongArch

+=23

+=23 Copyright (c) 2022, Loongson Technology Corpora= tion Limited. All rights reserved.<BR>

+=23

=
+=23 SPDX-License-Identifier: BSD-2-Clause-Patent

+=23=

+=23------------------------------------------------------= ------------------------

+

+ASM=5FGLOBAL ASM=5F= P=46X(CpuPause)

+

+=23/**

+=23 = Requests CPU to pause for a short period of time.

+=23
+=23 Requests CPU to pause for a short period of time. Typicall= y used in MP

+=23 systems to prevent memory starvation whil= e waiting for a spin lock.

+=23

+=23**/
=
+

+ASM=5FP=46X(CpuPause):

+ nop
+ nop

+ nop

+ nop

+ n= op

+ nop

+ nop

+ nop

<= div>+ jirl =24zero, =24ra, 0

+ .end

diff --gi= t a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePkg/Libra= ry/BaseLib/LoongArch64/DisableInterrupts.S
new file mode 100644=
index 0000000000..0f228339af
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
=40= =40 -0,0 +1,21 =40=40
+=23-------------------------------------= -----------------------------------------

+=23

+=23 LoongArch interrupt disable

+=23

+=23 = Copyright (c) 2022, Loongson Technology Corporation Limited. All rights r= eserved.<BR>

+=23

+=23 SPDX-License-Ide= ntifier: BSD-2-Clause-Patent

+=23

+=23-------= -----------------------------------------------------------------------
+

+ASM=5FGLOBAL ASM=5FP=46X(DisableInterrupts)=

+

+=23/**

+=23 Disables CPU in= terrupts.

+=23**/

+

+ASM=5FP=46= X(DisableInterrupts):

+ li.w =24t0, 0x4

+ csr= xchg =24zero, =24t0, 0x0

+ jirl =24zero, =24ra, 0

=
+ .end

diff --git a/MdePkg/Library/BaseLib/LoongArch64= /EnableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts= .S
new file mode 100644
index 0000000000..3c34fb2cdd<= /div>
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch6= 4/EnableInterrupts.S
=40=40 -0,0 +1,21 =40=40
+=23---= -------------------------------------------------------------------------= --

+=23

+=23 LoongArch interrupt enable
=
+=23

+=23 Copyright (c) 2022, Loongson Technology = Corporation Limited. All rights reserved.<BR>

+=23
+=23 SPDX-License-Identifier: BSD-2-Clause-Patent

+=23

+=23-----------------------------------------------= -------------------------------

+

+ASM=5FGLOB= AL ASM=5FP=46X(EnableInterrupts)

+

+=23/**
+=23 Enables CPU interrupts.

+=23**/

<= div>+

+ASM=5FP=46X(EnableInterrupts):

+ li.w = =24t0, 0x4

+ csrxchg =24t0, =24t0, 0x0

+ jirl= =24zero, =24ra, 0

+ .end

diff --git a/MdePkg= /Library/BaseLib/LoongArch64/GetInterruptState.S b/MdePkg/Library/BaseLib= /LoongArch64/GetInterruptState.S
new file mode 100644
index 0000000000..bfd1f2d5f7
--- /dev/null
+++ b/Mde= Pkg/Library/BaseLib/LoongArch64/GetInterruptState.S
=40=40 -0,0= +1,35 =40=40
+=23---------------------------------------------= ---------------------------------

+=23

+=23 G= et LoongArch interrupt status

+=23

+=23 Copyr= ight (c) 2022, Loongson Technology Corporation Limited. All rights reserv= ed.<BR>

+=23

+=23 SPDX-License-Identifi= er: BSD-2-Clause-Patent

+=23

+=23------------= ------------------------------------------------------------------
<= br>
+

+ASM=5FGLOBAL ASM=5FP=46X(GetInterruptState)
+

+=23/**

+=23 Retrieves the curren= t CPU interrupt state.

+=23

+=23 Returns TRUE= means interrupts are currently enabled. Otherwise,

+=23 re= turns =46ALSE.

+=23

+=23 =40retval TRUE CPU i= nterrupts are enabled.

+=23 =40retval =46ALSE CPU interrupt= s are disabled.

+=23

+=23**/

+<= /div>
+ASM=5FP=46X(GetInterruptState):

+ li.w =24t1= , 0x4

+ csrrd =24t0, 0x0

+ and =24t0, =24t0, = =24t1

+ beqz =24t0, 1f

+ li.w =24a0, 0x1
+ b 2f

+1:

+ li.w =24a0, 0x0
<= br>
+2:

+ jirl =24zero, =24ra, 0

+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwit= chStack.c b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
new file mode 100644
index 0000000000..859bc96329
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Inter= nalSwitchStack.c
=40=40 -0,0 +1,58 =40=40
+/** =40fil= e

+ SwitchStack() function for LoongArch.

+
+ Copyright (c) 2022, Loongson Technology Corporation Limite= d. All rights reserved.<BR>

+

+ SPDX-Li= cense-Identifier: BSD-2-Clause-Patent

+**/

+<= /div>
+=23include =22BaseLibInternals.h=22

+
<= br>
+UINTN

+E=46IAPI

+InternalSwitchStack= Asm (

+ IN BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER *JumpBuffer
+ );

+

+/**

+ Tran= sfers control to a function starting with a new stack.

+
+ Transfers control to the function specified by EntryPoint u= sing the

+ new stack specified by NewStack and passing in t= he parameters specified

+ by Context1 and Context2. Context= 1 and Context2 are optional and may

+ be NULL. The function= EntryPoint must never return.

+

+ If EntryPo= int is NULL, then ASSERT().

+ If NewStack is NULL, then ASS= ERT().

+

+ =40param=5Bin=5D EntryPoint A poin= ter to function to call with the new stack.

+ =40param=5Bin= =5D Context1 A pointer to the context to pass into the EntryPoint
+ function.

+ =40param=5Bin=5D Context2 A pointer to= the context to pass into the EntryPoint

+ function.
<= br>
+ =40param=5Bin=5D NewStack A pointer to the new stack to use for= the EntryPoint

+ function.

+ =40param=5Bin=5D= Marker VA=5FLIST marker for the variable argument list.

+<= /div>
+**/

+VOID

+E=46IAPI

<= div>+InternalSwitchStack (

+ IN SWITCH=5FSTACK=5FENTRY=5FPO= INT EntryPoint,

+ IN VOID *Context1 OPTIONAL,

+ IN VOID *Context2 OPTIONAL,

+ IN VOID *NewStack,
+ IN VA=5FLIST Marker

+ )

+

<= div>+=7B

+ BASE=5FLIBRARY=5FJUMP=5FBU=46=46ER JumpBuffer;
+

+ JumpBuffer.RA =3D (UINTN)EntryPoint;
=
+ JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *);

=
+ JumpBuffer.SP -=3D sizeof (Context1) + sizeof (Context2);
+ ((VOID **)(UINTN)JumpBuffer.SP)=5B0=5D =3D Context1;

+ ((VOID **)(UINTN)JumpBuffer.SP)=5B1=5D =3D Context2;

+<= /div>
+ InternalSwitchStackAsm (&JumpBuffer);

+= =7D

diff --git a/MdePkg/Library/BaseLib/LoongArch64/Memory=46= ence.S b/MdePkg/Library/BaseLib/LoongArch64/Memory=46ence.S
new= file mode 100644
index 0000000000..2b3d34366f
--- /d= ev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Memory=46ence.= S
=40=40 -0,0 +1,18 =40=40
+=23----------------------= --------------------------------------------------------

+=23=

+=23 Memory=46ence() for LoongArch

+=23
+=23 Copyright (c) 2022, Loongson Technology Corporation Limite= d. All rights reserved.<BR>

+=23

+=23 S= PDX-License-Identifier: BSD-2-Clause-Patent

+=23

<= div>+=23-----------------------------------------------------------------= -------------

+

+ASM=5FGLOBAL ASM=5FP=46X(Mem= ory=46ence)

+

+=23

+=23 Memory = fence for LoongArch

+=23

+ASM=5FP=46X(Memory=46= ence):

+ b AsmDataBarrierLoongArch

+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJum= p.S b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
new = file mode 100644
index 0000000000..1c6ee54b6f
--- /de= v/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump= .S
=40=40 -0,0 +1,49 =40=40
+=23---------------------= ---------------------------------------------------------

+= =23

+=23 Set/Long jump for LoongArch

+=23
+=23 Copyright (c) 2022, Loongson Technology Corporation Limit= ed. All rights reserved.<BR>

+=23

+=23 = SPDX-License-Identifier: BSD-2-Clause-Patent

+=23

=
+=23----------------------------------------------------------------= --------------

+

+=23define STORE st.d /* 64 = bit mode regsave instruction */

+=23define LOAD ld.d /* 64 = bit mode regload instruction */

+=23define RSIZE 8 /* 64 bi= t mode register size */

+

+ASM=5FGLOBAL ASM=5F= P=46X(SetJump)

+ASM=5FGLOBAL ASM=5FP=46X(InternalLongJump)<= /div>
+

+ASM=5FP=46X(SetJump):

+ STOR= E =24s0, =24a0, RSIZE * 0

+ STORE =24s1, =24a0, RSIZE * 1
+ STORE =24s2, =24a0, RSIZE * 2

+ STORE =24s3,= =24a0, RSIZE * 3

+ STORE =24s4, =24a0, RSIZE * 4

=
+ STORE =24s5, =24a0, RSIZE * 5

+ STORE =24s6, =24a0, = RSIZE * 6

+ STORE =24s7, =24a0, RSIZE * 7

+ S= TORE =24s8, =24a0, RSIZE * 8

+ STORE =24sp, =24a0, RSIZE * = 9

+ STORE =24fp, =24a0, RSIZE * 10

+ STORE =24= ra, =24a0, RSIZE * 11

+ li.w =24a0, 0 =23 Setjmp return
+ jirl =24zero, =24ra, 0

+

+ASM=5F= P=46X(InternalLongJump):

+ LOAD =24ra, =24a0, RSIZE * 11
+ LOAD =24s0, =24a0, RSIZE * 0

+ LOAD =24s1, =24= a0, RSIZE * 1

+ LOAD =24s2, =24a0, RSIZE * 2

= + LOAD =24s3, =24a0, RSIZE * 3

+ LOAD =24s4, =24a0, RSIZE *= 4

+ LOAD =24s5, =24a0, RSIZE * 5

+ LOAD =24s= 6, =24a0, RSIZE * 6

+ LOAD =24s7, =24a0, RSIZE * 7
+ LOAD =24s8, =24a0, RSIZE * 8

+ LOAD =24sp, =24a0, R= SIZE * 9

+ LOAD =24fp, =24a0, RSIZE * 10

+ mo= ve =24a0, =24a1

+ jirl =24zero, =24ra, 0

+ .e= nd

diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchSt= ack.S b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
new fi= le mode 100644
index 0000000000..ad9aa8b343
--- /dev/= null
+++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
=40=40 -0,0 +1,39 =40=40
+=23---------------------------= ---------------------------------------------------

+=23
+=23 InternalSwitchStackAsm for LoongArch

+=23<= /div>
+=23 Copyright (c) 2022, Loongson Technology Corporation Li= mited. All rights reserved.<BR>

+=23

+=23= SPDX-License-Identifier: BSD-2-Clause-Patent

+=23
+=23---------------------------------------------------------------= ---------------

+

+=23define STORE st.d /* 64= bit mode regsave instruction */

+=23define LOAD ld.d /* 64= bit mode regload instruction */

+=23define RSIZE 8 /* 64 b= it mode register size */

+

+ASM=5FGLOBAL ASM=5F= P=46X(InternalSwitchStackAsm)

+

+/**
+ This allows the caller to switch the stack and goes to the new en= try point

+

+ =40param JumpBuffer A pointer t= o CPU context buffer.

+**/

+

+A= SM=5FP=46X(InternalSwitchStackAsm):

+ LOAD =24ra, =24a0, RS= IZE * 11

+ LOAD =24s0, =24a0, RSIZE * 0

+ LOA= D =24s1, =24a0, RSIZE * 1

+ LOAD =24s2, =24a0, RSIZE * 2
+ LOAD =24s3, =24a0, RSIZE * 3

+ LOAD =24s4, =24= a0, RSIZE * 4

+ LOAD =24s5, =24a0, RSIZE * 5

= + LOAD =24s6, =24a0, RSIZE * 6

+ LOAD =24s7, =24a0, RSIZE *= 7

+ LOAD =24s8, =24a0, RSIZE * 8

+ LOAD =24s= p, =24a0, RSIZE * 9

+ LOAD =24fp, =24a0, RSIZE * 10
+ LOAD =24a0, =24sp, 0

+ LOAD =24a1, =24sp, 8
<= br>
+ jirl =24zero, =24ra, 0

+ .end

--
2.27.0
--632d37fe_4b94f0ec_dbe1--