From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=yi.qian@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C35521197B20 for ; Tue, 19 Mar 2019 01:20:44 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:20:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="126645782" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga008.jf.intel.com with ESMTP; 19 Mar 2019 01:20:43 -0700 Received: from fmsmsx118.amr.corp.intel.com (10.18.116.18) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Mar 2019 01:20:42 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx118.amr.corp.intel.com (10.18.116.18) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Mar 2019 01:20:42 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.163]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.158]) with mapi id 14.03.0415.000; Tue, 19 Mar 2019 16:20:40 +0800 From: "Qian, Yi" To: "Sun, Zailiang" , "edk2-devel@lists.01.org" CC: "Wei, David" , "Kinney, Michael D" Thread-Topic: [PATCH] Vlv2TbltDevicePkg: SPI lock Thread-Index: AQHU3ZBaHbYnsSjynkG7bIyvWlvZBKYSnZIA Date: Tue, 19 Mar 2019 08:20:39 +0000 Message-ID: References: <20190318134131.25384-1-zailiang.sun@intel.com> In-Reply-To: <20190318134131.25384-1-zailiang.sun@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] Vlv2TbltDevicePkg: SPI lock X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Mar 2019 08:20:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed by Qian, Yi Thanks Qian Yi > -----Original Message----- > From: Sun, Zailiang > Sent: Monday, March 18, 2019 9:42 PM > To: edk2-devel@lists.01.org > Cc: Wei, David ; Qian, Yi ; Kinne= y, > Michael D > Subject: [PATCH] Vlv2TbltDevicePkg: SPI lock >=20 > https://vthsd.intel.com/hsd/tiano/tracker/default.aspx?tracker_id=3D22154= 9 >=20 > Set protection bit such as BCR, PR0, PR1 and HSFS bits in SPI registers. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Zailiang Sun > Cc: David Wei > Cc: Yi Qian > Cc: Michael Kinney > --- > Vlv2TbltDevicePkg/PlatformDxe/Platform.c | 74 +++++++++++++++++-- > Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf | 8 ++ > 2 files changed, 75 insertions(+), 7 deletions(-) >=20 > diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c > b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c > index ad18da5c61..02538fd6f0 100644 > --- a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c > +++ b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c > @@ -51,7 +51,8 @@ Abstract: > #include > #include > #include > - > +#include > +#include >=20 > // > // VLV2 GPIO GROUP OFFSET > @@ -441,6 +442,21 @@ SpiBiosProtectionFunction( > UINTN BiosFlaLower1; > UINTN BiosFlaLimit1; >=20 > + EFI_SMM_BASE2_PROTOCOL *SmmBase2; > + EFI_STATUS Status; > + UINT32 Data32; > + UINT16 Data16; > + > + // > + // This feature requires smm stack. check whether smm stack is ready. > + if not, just return // Status =3D gBS->LocateProtocol > + (&gEfiSmmBase2ProtocolGuid, NULL, (VOID**) &SmmBase2); if > (EFI_ERROR > + (Status)) { > + DEBUG((EFI_D_INFO, "smm stack is not ready\n")); > + return; > + } else { > + DEBUG((EFI_D_INFO, "smm stack is ready\n")); } >=20 > BiosFlaLower0 =3D PcdGet32(PcdFlashMicroCodeAddress)- > PcdGet32(PcdBiosImageBase); > BiosFlaLimit0 =3D PcdGet32(PcdFlashMicroCodeSize)-1; > @@ -461,6 +477,7 @@ SpiBiosProtectionFunction( > ); > SpiBase =3D MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE)= & > B_PCH_LPC_SPI_BASE_BAR; >=20 > + DEBUG((EFI_D_INFO, "SpiBase =3D 0x%x\n", (UINTN)SpiBase)); > // > //Set SMM_BWP, WPD and LE bit > // > @@ -468,6 +485,16 @@ SpiBiosProtectionFunction( > MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), > (UINT8)(~B_PCH_SPI_BCR_BIOSWE)); > MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) > B_PCH_SPI_BCR_BLE); >=20 > + Data32 =3D MmioRead32 (SpiBase + R_PCH_SPI_BCR); > + S3BootScriptSaveMemWrite ( > + S3BootScriptWidthUint32, > + (UINTN)(SpiBase + R_PCH_SPI_BCR), > + 1, > + &Data32 > + ); > + DEBUG((EFI_D_INFO, "R_PCH_SPI_BCR \n")); DEBUG((EFI_D_INFO, > + "MmioRead32 (0x%x, 0x%x) =3D 0x%x \n", (UINTN) SpiBase, (UINT8) > + R_PCH_SPI_BCR, (UINT32) Data32)); > + > // > //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of = them > set already. > // > @@ -487,6 +514,16 @@ SpiBiosProtectionFunction( > B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\ >=20 > (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL > _MASK&(BiosFlaLimit0>>12)<<16)); >=20 > + Data32 =3D MmioRead32 (SpiBase + R_PCH_SPI_PR0); > + S3BootScriptSaveMemWrite ( > + S3BootScriptWidthUint32, > + (UINTN)(SpiBase + R_PCH_SPI_PR0), > + 1, > + &Data32 > + ); > + DEBUG((EFI_D_INFO, "R_PCH_SPI_PR0 \n")); DEBUG((EFI_D_INFO, > + "MmioRead32 (0x%x, 0x%x) =3D 0x%x \n", (UINTN) SpiBase, (UINT8) > + R_PCH_SPI_PR0, (UINT32) Data32)); > + > // > //Set PR1 > // > @@ -494,12 +531,31 @@ SpiBiosProtectionFunction( > MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1), > B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\ >=20 > (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL > _MASK&(BiosFlaLimit1>>12)<<16)); > + Data32 =3D MmioRead32 (SpiBase + R_PCH_SPI_PR1); > + S3BootScriptSaveMemWrite ( > + S3BootScriptWidthUint32, > + (UINTN)(SpiBase + R_PCH_SPI_PR1), > + 1, > + &Data32 > + ); > + DEBUG((EFI_D_INFO, "R_PCH_SPI_PR1 \n")); DEBUG((EFI_D_INFO, > + "MmioRead32 (0x%x, 0x%x) =3D 0x%x \n", (UINTN) SpiBase, (UINT8) > + R_PCH_SPI_PR1, (UINT32) Data32)); >=20 > // > //Lock down PRx > // > MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) > (B_PCH_SPI_HSFS_FLOCKDN)); >=20 > + Data16 =3D MmioRead16 (SpiBase + R_PCH_SPI_HSFS); > + S3BootScriptSaveMemWrite ( > + S3BootScriptWidthUint16, > + (UINTN)(SpiBase + R_PCH_SPI_HSFS), > + 1, > + &Data16 > + ); > + DEBUG((EFI_D_INFO, "R_PCH_SPI_HSFS \n")); DEBUG((EFI_D_INFO, > + "MmioRead16 (0x%x, 0x%x) =3D 0x%x \n", (UINTN) SpiBase, (UINT8) > + R_PCH_SPI_HSFS, (UINT16) Data16)); > + > // > // Verify if it's really locked. > // > @@ -783,6 +839,7 @@ InitializePlatform ( > EFI_HANDLE Handle =3D NULL; > EFI_EVENT mEfiExitBootServicesEvent; > EFI_EVENT RtcEvent; > + EFI_EVENT mEndOfExeEvent; > VOID *RtcCallbackReg =3D NULL; >=20 > mImageHandle =3D ImageHandle; > @@ -879,12 +936,15 @@ InitializePlatform ( > // Create a ReadyToBoot Event to run enable PR0/PR1 and lock > down,unlock variable region > // > if(mSystemConfiguration.SpiRwProtect=3D=3D1) { > - Status =3D EfiCreateEventReadyToBootEx ( > - TPL_CALLBACK, > - SpiBiosProtectionFunction, > - NULL, > - &mReadyToBootEvent > - ); > + Status =3D gBS->CreateEventEx ( > + EVT_NOTIFY_SIGNAL, > + TPL_CALLBACK, > + SpiBiosProtectionFunction, > + NULL, > + &gEfiEndOfDxeEventGroupGuid, > + &mEndOfExeEvent > + ); > + DEBUG ((EFI_D_INFO, "Create a EndofExeEvent to run enable PRx and > + lock down \n")); > } > // > // Create a ReadyToBoot Event to run the thermalzone init process diff= --git > a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf > b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf > index f1e1d9e5f1..2d9a088bd9 100644 > --- a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf > +++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf > @@ -96,6 +96,7 @@ > gEfiNormalSetupGuid > gEfiGlobalVariableGuid > gEfiEventExitBootServicesGuid > + gEfiEndOfDxeEventGroupGuid = ## > SOMETIMES_CONSUMES ## Event > gEfiVlv2VariableGuid > gEfiSecureBootEnableDisableGuid > gSystemRtcTimeVariableGuid > @@ -131,6 +132,7 @@ > gIgdOpRegionProtocolGuid > gExitPmAuthProtocolGuid > gEdkiiVariableLockProtocolGuid > + gEfiSmmBase2ProtocolGuid = ## > SOMETIMES_CONSUMES >=20 > [Pcd.common] > gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval > @@ -144,6 +146,12 @@ > gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize > gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase > gPlatformModuleTokenSpaceGuid.PcdRtcPowerFailure > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase > ## CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > ## CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase > ## CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > ## CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase > ## CONSUMES > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > ## CONSUMES >=20 >=20 > [Depex] > -- > 2.19.1.windows.1