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contact devel+owner@edk2.groups.io Resent-Date: Wed, 03 Apr 2024 23:43:59 -0700 Resent-From: yeoreum.yun@arm.com Reply-To: devel@edk2.groups.io,yeoreum.yun@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Yi2Pnsyef2UdloofPo5CWC4Ux7686176AA= Content-Language: en-GB Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=pPP0erfA; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: levi.yun ________________________________________ From: devel@edk2.groups.io on behalf of Prabin CA vi= a groups.io Sent: 03 April 2024 18:33 To: devel@edk2.groups.io Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham Subject: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD = value for L2 cache size in PPTT table The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU. Use the size specified by this PCD in the PPTT table of the RD-N2 platform. The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of the CPU's L2 cache and this allows changing the value of the L2 cache size depending the variant of the RD-N2 platform being build. RD-V2 platform is an example of such a variant. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 ++++ Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 4 +++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/R= dN2.dsc index 49a317a930e0..634edc2416c4 100644 --- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc +++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc @@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmPlatformTokenSpaceGuid.PcdClusterCount|16 +!ifdef $(PLAT_L2_CACHE_SIZE) + gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE) +!endif + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index afc38385c051..fb5e6e72c9e8 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -64,6 +64,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdL2CacheSize gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdN2/Pptt.aslc index b8cb04459be2..c37f04582f9c 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -21,6 +21,8 @@ #include "SgiAcpiHeader.h" #include "SgiPlatform.h" +#define L2_CACHE_SIZE FixedPcdGet32 (PcdL2CacheSize) + /** Define helper macro for populating processor core information. @param [in] PackageId Package instance number. @@ -81,7 +83,7 @@ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ - SIZE_1MB, /* Size */ = \ + L2_CACHE_SIZE, /* Size */ = \ 2048, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ -- 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. 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