[edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[Prabin CA]

Each CPUs of RD-V2 has 64KB of L1 instruction/data cache, 2MB of L2
cache and 32MB of system level cache. The system architecture of the
RD-V2 platform is similar to the RD-N2 platform, except for the CPU
and L2 cache size. So existing RD-N2 SMBIOS support is extended for
RD-V2 platform to reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.

Each CPUs of RD-Fremont include 64KB L1 instruction/data cache, 2MB L2
cache and 2MB of system level cache. This patch series adding the
extended SMBIOS support for RD-Fremont platform.

In addition to patches that extend the SMBIO support for these two
platforms, there are two patches that update support for existing
platforms. The first patch in this series introduce a PCD to specify
L2 cache size. The second patch make use of this PCD in PPTT table.

Link to gitlab branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdv2/?ref_type=heads

Prabin CA (3):
  Platform/Sgi: Add a new PCD for L2 cache size
  Platform/Sgi: Use PCD value for L2 cache size in PPTT table
  Platform/Sgi: Extend SMBIOS support for RD-Fremont

Pranav Madhu (2):
  Platform/Sgi: Define RD-V2 platform id values
  Platform/Sgi: Extend SMBIOS support for RD-V2 platform

 Platform/ARM/SgiPkg/SgiPlatform.dec                                       |  3 +++
 Platform/ARM/SgiPkg/RdN2/RdN2.dsc                                         |  4 ++++
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf                         |  1 +
 Platform/ARM/SgiPkg/Include/SgiPlatform.h                                 | 12 ++++++++++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    | 10 ++++++++--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 12 ++++++++---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 21 +++++++++++++++++++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c                     | 14 ++++++++++++-
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc                             |  4 +++-
 9 files changed, 72 insertions(+), 9 deletions(-)

-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v1 1/5] Platform/Sgi: Add a new PCD for L2 cache size

[Prabin CA]

A new PCD named PcdL2CacheSize is introduced to specify the size of the
CPU's L2 cache. This PCD can be used in PPTT tables for a reference
design platform. The default value of this PCD is set to 1MB but can be
changed depending on the variant of the reference design platform.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/SgiPlatform.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index af7887e54126..d540dbff2d19 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -37,6 +37,9 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002
   gArmSgiTokenSpaceGuid.PcdDramBlock2Size|0|UINT64|0x00000003
 
+  # L2 Cache size
+  gArmSgiTokenSpaceGuid.PcdL2CacheSize|0x100000|UINT32|0x0000002F
+
   # Virtio Block device
   gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00000004
   gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table

[Prabin CA]

The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU.
Use the size specified by this PCD in the PPTT table of the
RD-N2 platform.

The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of
the CPU's L2 cache and this allows changing the value of the L2 cache
size depending the variant of the RD-N2 platform being build. RD-V2
platform is an example of such a variant.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/RdN2/RdN2.dsc                 | 4 ++++
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 +
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc     | 4 +++-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
index 49a317a930e0..634edc2416c4 100644
--- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
+++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
@@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCoreCount|1
   gArmPlatformTokenSpaceGuid.PcdClusterCount|16
 
+!ifdef $(PLAT_L2_CACHE_SIZE)
+   gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE)
+!endif
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index afc38385c051..fb5e6e72c9e8 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -64,6 +64,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable
+  gArmSgiTokenSpaceGuid.PcdL2CacheSize
   gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdOscCppcEnable
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
index b8cb04459be2..c37f04582f9c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -21,6 +21,8 @@
 #include "SgiAcpiHeader.h"
 #include "SgiPlatform.h"
 
+#define L2_CACHE_SIZE  FixedPcdGet32 (PcdL2CacheSize)
+
 /** Define helper macro for populating processor core information.
 
   @param [in] PackageId Package instance number.
@@ -81,7 +83,7 @@
     EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
       PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
       0,                                    /* Next level of cache */          \
-      SIZE_1MB,                             /* Size */                         \
+      L2_CACHE_SIZE,                        /* Size */                         \
       2048,                                 /* Num of sets */                  \
       8,                                    /* Associativity */                \
       PPTT_UNIFIED_CACHE_ATTR,              /* Attributes */                   \
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v1 3/5] Platform/Sgi: Define RD-V2 platform id values

[Prabin CA]

From: Pranav Madhu <pranav.madhu@arm.com>

Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h             | 7 ++++++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e83853664c4c..6fa39d407bc9 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -47,6 +47,10 @@
 #define RD_N2_PART_NUM                            0x7B7
 #define RD_N2_CONF_ID                             0x1
 
+// RD-V2 Platform Identification values
+#define RD_V2_PART_NUM                            0x7F2
+#define RD_V2_CONF_ID                             0x1
+
 #define SGI_CONFIG_MASK                           0x0F
 #define SGI_CONFIG_SHIFT                          0x1C
 #define SGI_PART_NUM_MASK                         0xFFF
@@ -85,6 +89,7 @@ typedef enum {
   RdN2,
   RdN2Cfg1,
   RdN2Cfg2,
+  RdV2,
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index fa006320025b..14b06796ae9c 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -79,6 +79,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
     RD_N2_CONF_ID,
     1
   },
+  {
+    RdV2,
+    RD_V2_PART_NUM,
+    RD_V2_CONF_ID,
+    0
+  },
 };
 
 EFI_BOOT_MODE
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v1 4/5] Platform/Sgi: Extend SMBIOS support for RD-V2 platform

[Prabin CA]

From: Pranav Madhu <pranav.madhu@arm.com>

The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    |  7 +++++--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |  9 ++++++---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 20 +++++++++++++++++++-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..edf2a5f63c63 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -5,7 +5,7 @@
   Reference Design platforms. Type 1 table defines attributes of the
   overall system such as manufacturer, product name, UUID etc.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -33,7 +33,8 @@
   "RdV1Mc\0"                                            \
   "RdN2\0"                                              \
   "RdN2Cfg1\0"                                          \
-  "RdN2Cfg2\0"
+  "RdN2Cfg2\0"                                          \
+  "RdV2\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 0xda}},
   /* Rd-N2-Cfg2    */
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}},
+  /* Rd-V2         */
+  {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}},
 };
 
 /* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..ee269f707714 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -6,7 +6,7 @@
   family, processor id, maximum operating frequency, and other information
   related to the processor.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -27,7 +27,7 @@
 #define SOCKET_TYPE_BASE        3
 #define SOCKET_TYPE_NUM         1
 #define PROCESSOR_VERSION_BASE  (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM   10
+#define PROCESSOR_VERSION_NUM   11
 #define SERIAL_NUMBER_BASE      (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
 #define TYPE4_STRINGS                                   \
   "0x000\0"                     /* Part Number */       \
@@ -43,6 +43,7 @@
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
+  "Neoverse-V2\0"                                       \
   "000-0\0"                     /* Serial number */     \
   "783-3\0"                                             \
   "786-1\0"                                             \
@@ -52,7 +53,8 @@
   "78A-2\0"                                             \
   "7B7-1\0"                                             \
   "7B6-1\0"                                             \
-  "7B7-1\0"
+  "7B7-1\0"                                             \
+  "7F2-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
     break;
   case RdN2:
   case RdN2Cfg1:
+  case RdV2:
     mArmRdSmbiosType4.Base.CoreCount = CoreCount;
     mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
     mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..4af72919a3f1 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -6,7 +6,7 @@
   implemented, cache configuration, ways of associativity and other
   information related to cache memory installed.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -334,6 +334,24 @@ InstallType7CacheInformation (
     mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192;     // 8MB SLC
     mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
     break;
+  case RdV2:
+    /* L1 instruction cache */
+    mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+    /* L1 data cache */
+    mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[1].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+    /* L2 cache */
+    mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 2048;  // 2MB
+    mArmRdSmbiosType7[2].Base.InstalledSize2 = 2048;     // 2MB
+    mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+    /* System level cache */
+    mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768; // 32MB SLC
+    mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768;    // 32MB SLC
+    mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
+    break;
   }
 
   /* Install valid cache information tables */
-- 
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[edk2-devel] [edk2-platforms][PATCH v1 5/5] Platform/Sgi: Extend SMBIOS support for RD-Fremont

[Prabin CA]

Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h                                 | 5 +++++
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    | 5 ++++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 ++++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c                     | 6 ++++++
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
 #define RD_V2_PART_NUM                            0x7F2
 #define RD_V2_CONF_ID                             0x1
 
+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM                       0x7EE
+#define RD_Fremont_CONF_ID                        0x1
+
 #define SGI_CONFIG_MASK                           0x0F
 #define SGI_CONFIG_SHIFT                          0x1C
 #define SGI_PART_NUM_MASK                         0xFFF
@@ -90,6 +94,7 @@ typedef enum {
   RdN2Cfg1,
   RdN2Cfg2,
   RdV2,
+  RdFremont,
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
   "RdN2\0"                                              \
   "RdN2Cfg1\0"                                          \
   "RdN2Cfg2\0"                                          \
-  "RdV2\0"
+  "RdV2\0"                                              \
+  "RdFremont\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}},
   /* Rd-V2         */
   {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}},
+  /* Rd-Fremont    */
+  {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 0x02}},
 };
 
 /* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
   "Neoverse-V2\0"                                       \
+  "Neoverse-Poseidon\0"                                 \
   "000-0\0"                     /* Serial number */     \
   "783-3\0"                                             \
   "786-1\0"                                             \
@@ -54,7 +55,8 @@
   "7B7-1\0"                                             \
   "7B6-1\0"                                             \
   "7B7-1\0"                                             \
-  "7F2-1\0"
+  "7F2-1\0"                                             \
+  "7EE-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
   case RdN2:
   case RdN2Cfg1:
   case RdV2:
+  case RdFremont:
     mArmRdSmbiosType4.Base.CoreCount = CoreCount;
     mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
     mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
     mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
     break;
   case RdV2:
+  case RdFremont:
     /* L1 instruction cache */
     mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;    // 64KB
     mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;       // 64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index 14b06796ae9c..ae31be142d12 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -85,6 +85,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
     RD_V2_CONF_ID,
     0
   },
+  {
+    RdFremont,
+    RD_Fremont_PART_NUM,
+    RD_Fremont_CONF_ID,
+    0
+  },
 };
 
 EFI_BOOT_MODE
-- 
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 1/5] Platform/Sgi: Add a new PCD for L2 cache size

[levi.yun]

Reviewed-by: levi.yun <yeoreum.yun@arm.com>

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Prabin CA via groups.io <prabin.ca=arm.com@groups.io>
Sent: 03 April 2024 18:33
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v1 1/5] Platform/Sgi: Add a new PCD for L2 cache size

A new PCD named PcdL2CacheSize is introduced to specify the size of the
CPU's L2 cache. This PCD can be used in PPTT tables for a reference
design platform. The default value of this PCD is set to 1MB but can be
changed depending on the variant of the reference design platform.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/SgiPlatform.dec | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index af7887e54126..d540dbff2d19 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -37,6 +37,9 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002
   gArmSgiTokenSpaceGuid.PcdDramBlock2Size|0|UINT64|0x00000003

+  # L2 Cache size
+  gArmSgiTokenSpaceGuid.PcdL2CacheSize|0x100000|UINT32|0x0000002F
+
   # Virtio Block device
   gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00000004
   gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005
--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table

[levi.yun]

Reviewed-by: levi.yun <yeoreum.yun@arm.com>

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Prabin CA via groups.io <prabin.ca=arm.com@groups.io>
Sent: 03 April 2024 18:33
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table

The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU.
Use the size specified by this PCD in the PPTT table of the
RD-N2 platform.

The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of
the CPU's L2 cache and this allows changing the value of the L2 cache
size depending the variant of the RD-N2 platform being build. RD-V2
platform is an example of such a variant.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/RdN2/RdN2.dsc                 | 4 ++++
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 +
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc     | 4 +++-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
index 49a317a930e0..634edc2416c4 100644
--- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
+++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
@@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCoreCount|1
   gArmPlatformTokenSpaceGuid.PcdClusterCount|16

+!ifdef $(PLAT_L2_CACHE_SIZE)
+   gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE)
+!endif
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index afc38385c051..fb5e6e72c9e8 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -64,6 +64,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable
+  gArmSgiTokenSpaceGuid.PcdL2CacheSize
   gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdOscCppcEnable
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
index b8cb04459be2..c37f04582f9c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -21,6 +21,8 @@
 #include "SgiAcpiHeader.h"
 #include "SgiPlatform.h"

+#define L2_CACHE_SIZE  FixedPcdGet32 (PcdL2CacheSize)
+
 /** Define helper macro for populating processor core information.

   @param [in] PackageId Package instance number.
@@ -81,7 +83,7 @@
     EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
       PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
       0,                                    /* Next level of cache */          \
-      SIZE_1MB,                             /* Size */                         \
+      L2_CACHE_SIZE,                        /* Size */                         \
       2048,                                 /* Num of sets */                  \
       8,                                    /* Associativity */                \
       PPTT_UNIFIED_CACHE_ATTR,              /* Attributes */                   \
--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 3/5] Platform/Sgi: Define RD-V2 platform id values

[levi.yun]

Reviewed-by: levi.yun <yeoreum.yun@arm.com>

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Prabin CA via groups.io <prabin.ca=arm.com@groups.io>
Sent: 03 April 2024 18:33
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v1 3/5] Platform/Sgi: Define RD-V2 platform id values

From: Pranav Madhu <pranav.madhu@arm.com>

Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h             | 7 ++++++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e83853664c4c..6fa39d407bc9 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -47,6 +47,10 @@
 #define RD_N2_PART_NUM                            0x7B7
 #define RD_N2_CONF_ID                             0x1

+// RD-V2 Platform Identification values
+#define RD_V2_PART_NUM                            0x7F2
+#define RD_V2_CONF_ID                             0x1
+
 #define SGI_CONFIG_MASK                           0x0F
 #define SGI_CONFIG_SHIFT                          0x1C
 #define SGI_PART_NUM_MASK                         0xFFF
@@ -85,6 +89,7 @@ typedef enum {
   RdN2,
   RdN2Cfg1,
   RdN2Cfg2,
+  RdV2,
 } ARM_RD_PRODUCT_ID;

 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index fa006320025b..14b06796ae9c 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+*  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -79,6 +79,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
     RD_N2_CONF_ID,
     1
   },
+  {
+    RdV2,
+    RD_V2_PART_NUM,
+    RD_V2_CONF_ID,
+    0
+  },
 };

 EFI_BOOT_MODE
--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 4/5] Platform/Sgi: Extend SMBIOS support for RD-V2 platform

[levi.yun]

Reviewed-by: levi.yun <yeoreum.yun@arm.com>

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Prabin CA via groups.io <prabin.ca=arm.com@groups.io>
Sent: 03 April 2024 18:33
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v1 4/5] Platform/Sgi: Extend SMBIOS support for RD-V2 platform

From: Pranav Madhu <pranav.madhu@arm.com>

The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    |  7 +++++--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |  9 ++++++---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 20 +++++++++++++++++++-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..edf2a5f63c63 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -5,7 +5,7 @@
   Reference Design platforms. Type 1 table defines attributes of the
   overall system such as manufacturer, product name, UUID etc.

-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent

   @par Specification Reference:
@@ -33,7 +33,8 @@
   "RdV1Mc\0"                                            \
   "RdN2\0"                                              \
   "RdN2Cfg1\0"                                          \
-  "RdN2Cfg2\0"
+  "RdN2Cfg2\0"                                          \
+  "RdV2\0"

 typedef enum {
   ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 0xda}},
   /* Rd-N2-Cfg2    */
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}},
+  /* Rd-V2         */
+  {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}},
 };

 /* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..ee269f707714 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -6,7 +6,7 @@
   family, processor id, maximum operating frequency, and other information
   related to the processor.

-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent

   @par Specification Reference:
@@ -27,7 +27,7 @@
 #define SOCKET_TYPE_BASE        3
 #define SOCKET_TYPE_NUM         1
 #define PROCESSOR_VERSION_BASE  (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM   10
+#define PROCESSOR_VERSION_NUM   11
 #define SERIAL_NUMBER_BASE      (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
 #define TYPE4_STRINGS                                   \
   "0x000\0"                     /* Part Number */       \
@@ -43,6 +43,7 @@
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
+  "Neoverse-V2\0"                                       \
   "000-0\0"                     /* Serial number */     \
   "783-3\0"                                             \
   "786-1\0"                                             \
@@ -52,7 +53,8 @@
   "78A-2\0"                                             \
   "7B7-1\0"                                             \
   "7B6-1\0"                                             \
-  "7B7-1\0"
+  "7B7-1\0"                                             \
+  "7F2-1\0"

 typedef enum {
   PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
     break;
   case RdN2:
   case RdN2Cfg1:
+  case RdV2:
     mArmRdSmbiosType4.Base.CoreCount = CoreCount;
     mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
     mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..4af72919a3f1 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -6,7 +6,7 @@
   implemented, cache configuration, ways of associativity and other
   information related to cache memory installed.

-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent

   @par Specification Reference:
@@ -334,6 +334,24 @@ InstallType7CacheInformation (
     mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192;     // 8MB SLC
     mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
     break;
+  case RdV2:
+    /* L1 instruction cache */
+    mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+    /* L1 data cache */
+    mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[1].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+    /* L2 cache */
+    mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 2048;  // 2MB
+    mArmRdSmbiosType7[2].Base.InstalledSize2 = 2048;     // 2MB
+    mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+    /* System level cache */
+    mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768; // 32MB SLC
+    mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768;    // 32MB SLC
+    mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
+    break;
   }

   /* Install valid cache information tables */
--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 5/5] Platform/Sgi: Extend SMBIOS support for RD-Fremont

[levi.yun]

Reviewed-by: levi.yun <yeoreum.yun@arm.com>

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Prabin CA via groups.io <prabin.ca=arm.com@groups.io>
Sent: 03 April 2024 18:33
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v1 5/5] Platform/Sgi: Extend SMBIOS support for RD-Fremont

Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.

Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h                                 | 5 +++++
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    | 5 ++++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 ++++-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c                     | 6 ++++++
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
 #define RD_V2_PART_NUM                            0x7F2
 #define RD_V2_CONF_ID                             0x1

+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM                       0x7EE
+#define RD_Fremont_CONF_ID                        0x1
+
 #define SGI_CONFIG_MASK                           0x0F
 #define SGI_CONFIG_SHIFT                          0x1C
 #define SGI_PART_NUM_MASK                         0xFFF
@@ -90,6 +94,7 @@ typedef enum {
   RdN2Cfg1,
   RdN2Cfg2,
   RdV2,
+  RdFremont,
 } ARM_RD_PRODUCT_ID;

 // Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
   "RdN2\0"                                              \
   "RdN2Cfg1\0"                                          \
   "RdN2Cfg2\0"                                          \
-  "RdV2\0"
+  "RdV2\0"                                              \
+  "RdFremont\0"

 typedef enum {
   ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}},
   /* Rd-V2         */
   {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}},
+  /* Rd-Fremont    */
+  {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 0x02}},
 };

 /* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
   "Neoverse-V2\0"                                       \
+  "Neoverse-Poseidon\0"                                 \
   "000-0\0"                     /* Serial number */     \
   "783-3\0"                                             \
   "786-1\0"                                             \
@@ -54,7 +55,8 @@
   "7B7-1\0"                                             \
   "7B6-1\0"                                             \
   "7B7-1\0"                                             \
-  "7F2-1\0"
+  "7F2-1\0"                                             \
+  "7EE-1\0"

 typedef enum {
   PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
   case RdN2:
   case RdN2Cfg1:
   case RdV2:
+  case RdFremont:
     mArmRdSmbiosType4.Base.CoreCount = CoreCount;
     mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
     mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
     mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
     break;
   case RdV2:
+  case RdFremont:
     /* L1 instruction cache */
     mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;    // 64KB
     mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;       // 64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index 14b06796ae9c..ae31be142d12 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -85,6 +85,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
     RD_V2_CONF_ID,
     0
   },
+  {
+    RdFremont,
+    RD_Fremont_PART_NUM,
+    RD_Fremont_CONF_ID,
+    0
+  },
 };

 EFI_BOOT_MODE
--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[Prabin CA]

[-- Attachment #1: Type: text/plain, Size: 504 bytes --]

Hi,

Need review on this patches, waiting for a month to get the review on this patch set. Any review on this would be really helpful.


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Re: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table

[Sami Mujawar]

[-- Attachment #1: Type: text/plain, Size: 4320 bytes --]

Hi Prabin,

Thank you for this patch.

Please see my response inline marked [SAMI].

With that fixed,

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 4/3/24 18:33, Prabin CA wrote:
> The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU.
> Use the size specified by this PCD in the PPTT table of the
> RD-N2 platform.
>
> The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of
> the CPU's L2 cache and this allows changing the value of the L2 cache
> size depending the variant of the RD-N2 platform being build. RD-V2
> platform is an example of such a variant.
>
> Signed-off-by: Prabin CA<prabin.ca@arm.com>
> ---
>   Platform/ARM/SgiPkg/RdN2/RdN2.dsc                 | 4 ++++
>   Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 +
>   Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc     | 4 +++-
>   3 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
> index 49a317a930e0..634edc2416c4 100644
> --- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
> +++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
> @@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common]
>     gArmPlatformTokenSpaceGuid.PcdCoreCount|1
>     gArmPlatformTokenSpaceGuid.PcdClusterCount|16
>   
> +!ifdef $(PLAT_L2_CACHE_SIZE)
> +   gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE)

[SAMI] I think there is no need for PLAT_L2_CACHE_SIZE. The pcd can be 
set from the build command line using the something like '--pcd 
PcdL2CacheSize=0x10000'.

Can you check, please?

Also update the commit message to document that the Pcd can be 
configured from the build command line and provide an example.

[/SAMI]

> +!endif
> +
>   ################################################################################
>   #
>   # Components Section - list of all EDK II Modules needed by this Platform
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
> index afc38385c051..fb5e6e72c9e8 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
> @@ -64,6 +64,7 @@ [FixedPcd]
>     gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
>     gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base
>     gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable
> +  gArmSgiTokenSpaceGuid.PcdL2CacheSize
>     gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
>     gArmSgiTokenSpaceGuid.PcdOscLpiEnable
>     gArmSgiTokenSpaceGuid.PcdOscCppcEnable
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> index b8cb04459be2..c37f04582f9c 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> @@ -21,6 +21,8 @@
>   #include "SgiAcpiHeader.h"
>   #include "SgiPlatform.h"
>   
> +#define L2_CACHE_SIZE  FixedPcdGet32 (PcdL2CacheSize)
> +
>   /** Define helper macro for populating processor core information.
>   
>     @param [in] PackageId Package instance number.
> @@ -81,7 +83,7 @@
>       EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (                                   \
>         PPTT_CACHE_STRUCTURE_FLAGS,           /* Flag */                         \
>         0,                                    /* Next level of cache */          \
> -      SIZE_1MB,                             /* Size */                         \
> +      L2_CACHE_SIZE,                        /* Size */                         \

[SAMI] I think you can use FixedPcdGet32 (PcdL2CacheSize) in the above 
macro directly.

[/SAMI]

>         2048,                                 /* Num of sets */                  \
>         8,                                    /* Associativity */                \
>         PPTT_UNIFIED_CACHE_ATTR,              /* Attributes */                   \


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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[Sami Mujawar]

Hi Prabin,

If you agree with my suggestions for patch 2/5, can you reply back on 
the list, please?

I will then fix that patch locally before merging.

Other than patch 2/5 the rest of the series looks good to me.

Reviewed-by: Sami Mujawar <sami.muajwar@arm.com>

Regards,

Sami Mujawar

On 4/3/24 18:33, Prabin CA wrote:
> Each CPUs of RD-V2 has 64KB of L1 instruction/data cache, 2MB of L2
> cache and 32MB of system level cache. The system architecture of the
> RD-V2 platform is similar to the RD-N2 platform, except for the CPU
> and L2 cache size. So existing RD-N2 SMBIOS support is extended for
> RD-V2 platform to reuse rest of the RD-N2 SMBIOS configuration for the
> RD-V2 platform.
>
> Each CPUs of RD-Fremont include 64KB L1 instruction/data cache, 2MB L2
> cache and 2MB of system level cache. This patch series adding the
> extended SMBIOS support for RD-Fremont platform.
>
> In addition to patches that extend the SMBIO support for these two
> platforms, there are two patches that update support for existing
> platforms. The first patch in this series introduce a PCD to specify
> L2 cache size. The second patch make use of this PCD in PPTT table.
>
> Link to gitlab branch with the patches in this series -
> https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdv2/?ref_type=heads
>
> Prabin CA (3):
>    Platform/Sgi: Add a new PCD for L2 cache size
>    Platform/Sgi: Use PCD value for L2 cache size in PPTT table
>    Platform/Sgi: Extend SMBIOS support for RD-Fremont
>
> Pranav Madhu (2):
>    Platform/Sgi: Define RD-V2 platform id values
>    Platform/Sgi: Extend SMBIOS support for RD-V2 platform
>
>   Platform/ARM/SgiPkg/SgiPlatform.dec                                       |  3 +++
>   Platform/ARM/SgiPkg/RdN2/RdN2.dsc                                         |  4 ++++
>   Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf                         |  1 +
>   Platform/ARM/SgiPkg/Include/SgiPlatform.h                                 | 12 ++++++++++-
>   Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    | 10 ++++++++--
>   Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 12 ++++++++---
>   Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 21 +++++++++++++++++++-
>   Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c                     | 14 ++++++++++++-
>   Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc                             |  4 +++-
>   9 files changed, 72 insertions(+), 9 deletions(-)
>


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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[Prabin CA]

[-- Attachment #1: Type: text/plain, Size: 516 bytes --]

Hi Sami,

Thank you for reviewing the patches. Yes that is fine, you can make the changes locally and merge to upstream.

*Thanks,*
*Prabin CA*


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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont

[Sami Mujawar]

[-- Attachment #1: Type: text/plain, Size: 1265 bytes --]

Merged as fc4cd3545fe6..8f05785753aa

Thanks.

Regards,

Sami Mujawar

From: "Prabin CA via Groups.Io" <prabin.ca=arm.com@groups.io>
Reply to: Prabin CA <Prabin.CA@arm.com>
Date: Wednesday 5 June 2024 at 16:38
To: Sami Mujawar <Sami.Mujawar@arm.com>, "devel@edk2.groups.io" <devel@edk2.groups.io>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Extend SMBIOS support for RD-V2 and RD-Fremont


Hi Sami,



Thank you for reviewing the patches. Yes that is fine, you can make the changes locally and merge to upstream.

Thanks,
Prabin CA

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