From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-db5eur01on062f.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe02::62f]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 674C61A1E10 for ; Fri, 14 Oct 2016 04:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=E39B4D+YvKHzSZNGyzGDQcWwkM3cW6EE0bLw2ENW+PI=; b=HZsIAvvce0fk40si2HOqOX2FmUYjAUIO9yAWlfcRweY+jlqPDEmbAzzlCH5Yix2PfsLOrynY/lT5a39fSZu7LQSsX3E8Tc1+r7B58V4abIDULkWuu/rMnpgokD8PVe+1Ogcd6ytLKCpTb0r9w4q9+z9e9/+ALUMRgLKPGQI0O7s= Received: from AM4PR0401MB2289.eurprd04.prod.outlook.com (10.165.45.12) by AM4PR0401MB2290.eurprd04.prod.outlook.com (10.165.45.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.659.8; Fri, 14 Oct 2016 11:21:03 +0000 Received: from AM4PR0401MB2289.eurprd04.prod.outlook.com ([10.165.45.12]) by AM4PR0401MB2289.eurprd04.prod.outlook.com ([10.165.45.12]) with mapi id 15.01.0659.020; Fri, 14 Oct 2016 11:21:03 +0000 From: Bhupesh Sharma To: Bhupesh Sharma , "edk2-devel@ml01.01.org" CC: "linaro-uefi@lists.linaro.org" , "Ard Biesheuvel" Thread-Topic: [PATCH 1/1] ArmPlatformPkg/ArmTrustZone: Add support for specifying Subregions to be disabled Thread-Index: AQHSJgpkODzakqTnNUuD7yKegHBMAqCnzbrw Date: Fri, 14 Oct 2016 11:21:03 +0000 Message-ID: References: <1476442321-30114-1-git-send-email-bhupesh.sharma@nxp.com> In-Reply-To: <1476442321-30114-1-git-send-email-bhupesh.sharma@nxp.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=bhupesh.sharma@nxp.com; x-originating-ip: [192.88.169.1] x-ms-office365-filtering-correlation-id: 21acb296-7297-458b-a7ea-08d3f4242f4e x-microsoft-exchange-diagnostics: 1; AM4PR0401MB2290; 7:invOXZ1txLoKAhHsCx2juUdG9GpmRkI4ZRrWlwgDDLky48/sUqwsnubY/j36PgDnRU7IOhuhcdDSXvH484+qv02OhlqqPSxUW6nvmjXizKmBgyKRiOg6dGXz7/mvf0hBI8AvtMO3xme3fhrvHBqNiKGXr/GYfnE8nbi1ukAGnRPlXlr5Fgqd3xdVtepJaAFKCCuRiBbZ6WzRhBUK8o5pTKNmtJdJjyRBxJgSUuVheLe+sStDLSSZOaml3jqhoUo49wrrV3Za4VsMQS3Rvih2pmnO9SP+4kfuh6ci0vklMQ1xdyVrIw7szBL8vo8vzhOcxHXT+VVKqq+K5kC7ClK5Z1lXjVToEFt1k6nKEXFGgGc= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR0401MB2290; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(192374486261705)(185117386973197)(1553240931313); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026); SRVR:AM4PR0401MB2290; BCL:0; PCL:0; RULEID:; SRVR:AM4PR0401MB2290; x-forefront-prvs: 0095BCF226 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(7916002)(189002)(13464003)(377454003)(199003)(2501003)(575784001)(101416001)(105586002)(2900100001)(2950100002)(15975445007)(77096005)(8936002)(7696004)(19580405001)(5660300001)(106116001)(9686002)(10400500002)(92566002)(68736007)(33656002)(6116002)(97736004)(122556002)(5001770100001)(3660700001)(7736002)(76576001)(586003)(11100500001)(4326007)(3846002)(66066001)(189998001)(19580395003)(76176999)(86362001)(106356001)(7846002)(5002640100001)(3280700002)(50986999)(305945005)(87936001)(81166006)(81156014)(2906002)(74316002)(8676002)(102836003)(54356999)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR0401MB2290; H:AM4PR0401MB2289.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2016 11:21:03.8195 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0401MB2290 Subject: Re: [PATCH 1/1] ArmPlatformPkg/ArmTrustZone: Add support for specifying Subregions to be disabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Oct 2016 11:21:07 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch is missing a .h file. Please discard. I will RESEND the patch with the fix. Apologies for the inconvenience.=20 Regards, Bhupesh > -----Original Message----- > From: Bhupesh Sharma [mailto:bhupesh.sharma@nxp.com] > Sent: Friday, October 14, 2016 4:22 PM > To: edk2-devel@ml01.01.org > Cc: linaro-uefi@lists.linaro.org; Bhupesh Sharma > ; Ard Biesheuvel > Subject: [PATCH 1/1] ArmPlatformPkg/ArmTrustZone: Add support for > specifying Subregions to be disabled >=20 > ARM TZASC-380 IP provides a mechanism to split memory regions being > protected via it into eight equal-sized sub-regions, with a bit setting > allowing the corresponding subregion to be disabled. >=20 > Several NXP/FSL SoCs support the TZASC-380 IP block and allow the DDR > connected via the TZASC to be partitioned into regions having different > security settings. >=20 > This patch enables this support and can be used for SoCs which support > such partition of DDR regions. >=20 > Details of the 'subregion_disable' register can be viewed here: > http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ddi0431c/CJ > ABCFHB.html >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Bhupesh Sharma > Cc: Ard Biesheuvel > --- > .../Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c | 21 > ++++++++++++++------- > ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c | 5 +++-- > 2 files changed, 17 insertions(+), 9 deletions(-) >=20 > diff --git > a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4S > ec.c > b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4S > ec.c > index 6fa0774..d358d65 100644 > --- > a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4S > ec.c > +++ > b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9 > +++ x4Sec.c > @@ -72,18 +72,21 @@ ArmPlatformSecTrustzoneInit ( > // NOR Flash 0 non secure (BootMon) > TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED, > ARM_VE_SMB_NOR0_BASE,0, > - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, > + 0); >=20 > // NOR Flash 1. The first half of the NOR Flash1 must be secure for > the secure firmware (sec_uefi.bin) > if (PcdGetBool (PcdTrustzoneSupport) =3D=3D TRUE) { > //Note: Your OS Kernel must be aware of the secure regions before > to enable this region > TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, > ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0, > - TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, > + 0); > } else { > TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, > ARM_VE_SMB_NOR1_BASE,0, > - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, > + 0); > } >=20 > // Base of SRAM. Only half of SRAM in Non Secure world @@ -92,22 > +95,26 @@ ArmPlatformSecTrustzoneInit ( > //Note: Your OS Kernel must be aware of the secure regions before > to enable this region > TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, > ARM_VE_SMB_SRAM_BASE,0, > - TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW, > + 0); > } else { > TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, > ARM_VE_SMB_SRAM_BASE,0, > - TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, > + 0); > } >=20 > // Memory Mapped Peripherals. All in non secure world > TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED, > ARM_VE_SMB_PERIPH_BASE,0, > - TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, > + 0); >=20 > // MotherBoard Peripherals and On-chip peripherals. > TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED, > ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0, > - TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW); > + TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW, > + 0); > } >=20 > /** > diff --git a/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c > b/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c > index 070c0dc..5cd41ef 100644 > --- a/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c > +++ b/ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.c > @@ -87,7 +87,8 @@ TZASCSetRegion ( > IN UINTN LowAddress, > IN UINTN HighAddress, > IN UINTN Size, > - IN UINTN Security > + IN UINTN Security, > + IN UINTN SubregionDisableMask > ) > { > UINT32* Region; > @@ -100,7 +101,7 @@ TZASCSetRegion ( >=20 > MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000); > MmioWrite32((UINTN)(Region+1), HighAddress); > - MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & > 0x3F) << 1) | (Enabled & 0x1)); > + MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | > + ((SubregionDisableMask & 0xFF) << 8) | ((Size & 0x3F) << 1) | > (Enabled > + & 0x1)); >=20 > return EFI_SUCCESS; > } > -- > 1.9.1 >=20