[PATCH 2/5] MdePkg/SPI: Add missing definitions.

["Marvin Häuser" <Marvin.Haeuser@outlook.com>]

The PI Specification lack a bunch of definitions required to
implement the protocol stack. Add definitions with bit values,
ordered in the same way as in the specification.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
---
 MdePkg/Include/Protocol/SpiConfiguration.h | 15 +++++++
 MdePkg/Include/Protocol/SpiHc.h            | 47 ++++++++++++++++++++
 MdePkg/Include/Protocol/SpiIo.h            | 23 ++++++++++
 3 files changed, 85 insertions(+)

diff --git a/MdePkg/Include/Protocol/SpiConfiguration.h b/MdePkg/Include/Protocol/SpiConfiguration.h
index c36a809f4232..9d6c1e94d12b 100644
--- a/MdePkg/Include/Protocol/SpiConfiguration.h
+++ b/MdePkg/Include/Protocol/SpiConfiguration.h
@@ -178,6 +178,21 @@ typedef struct _EFI_SPI_BUS {
   VOID                           *ClockParameter;
 } EFI_SPI_BUS;
 
+//
+// SPI Peripheral attributes.
+// Note: The UEFI PI 1.6 specification does not specify values for defines
+//       below. The order matches the specification.
+//
+
+///
+/// The SPI peripheral is wired to support a 2-bit data bus
+///
+#define SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH  BIT0
+///
+/// The SPI peripheral is wired to  support a 4-bit data bus
+///
+#define SPI_PART_SUPPORTS_4_BIT_DATA_BUS_WIDTH  BIT1
+
 ///
 /// The EFI_SPI_PERIPHERAL data structure describes how a specific block of
 /// logic which is connected to the SPI bus. This data structure also selects
diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiHc.h
index 71c75431e4e8..dabbc9ae231d 100644
--- a/MdePkg/Include/Protocol/SpiHc.h
+++ b/MdePkg/Include/Protocol/SpiHc.h
@@ -35,6 +35,53 @@
 
 typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;
 
+//
+// SPI Host Controller Attributes.
+// Note: The UEFI PI 1.6 specification does not specify values for defines
+//       below. The order matches the specification.
+//
+
+///
+/// The SPI Host Controller supports write-only operations.
+///
+#define HC_SUPPORTS_WRITE_ONLY_OPERATIONS       BIT0
+///
+/// The SPI Host Controller supports read-only operations.
+///
+#define HC_SUPPORTS_READ_ONLY_OPERATIONS        BIT1
+///
+/// The SPI Host Controller supports write-then-read operations.
+///
+#define HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS  BIT2
+///
+/// The SPI host controller requires the transmit frame to be in most
+/// significant bits instead of least significant bits.  The host driver will
+/// adjust the frames if necessary.
+///
+#define HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS    BIT3
+///
+/// The SPI host controller places the receive frame to be in most significant
+/// bits instead of least significant bits.  The host driver will adjust the
+/// frames to be in the least significant bits if necessary.
+///
+#define HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS    BIT4
+///
+/// The SPI controller supports a 2-bit data bus.
+///
+#define HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH        BIT5
+///
+/// The SPI controller supports a 4-bit data bus.
+///
+#define HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH        BIT6
+///
+/// Transfer size includes the opcode byte.
+///
+#define HC_TRANSFER_SIZE_INCLUDES_OPCODE        BIT7
+///
+/// Transfer size includes the 3 address bytes.
+///
+#define HC_TRANSFER_SIZE_INCLUDES_ADDRESS       BIT8
+
 /**
   Assert or deassert the SPI chip select.
 
diff --git a/MdePkg/Include/Protocol/SpiIo.h b/MdePkg/Include/Protocol/SpiIo.h
index 8c5d96bb04b2..92659122a37e 100644
--- a/MdePkg/Include/Protocol/SpiIo.h
+++ b/MdePkg/Include/Protocol/SpiIo.h
@@ -56,6 +56,29 @@ typedef enum {
   SPI_TRANSACTION_WRITE_THEN_READ
 } EFI_SPI_TRANSACTION_TYPE;
 
+//
+// SPI IO Attributes.
+// Note: The UEFI PI 1.6 specification does not specify values for defines
+//       below. The order matches the specification.
+//
+
+///
+/// The SPI host and peripheral supports a 2-bit data bus
+///
+#define SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH   BIT0
+///
+/// The SPI host and peripheral supports a 4-bit data bus
+///
+#define SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH   BIT1
+///
+/// Transfer size includes the opcode byte
+///
+#define SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE   BIT2
+///
+/// Transfer size includes the 3 address bytes
+///
+#define SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS  BIT3
+
 /**
   Initiate a SPI transaction between the host and a SPI peripheral.
 
-- 
2.16.0.windows.2